DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0019] While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that there is no intent to limit the invention to the particular forms disclosed, but on the contrary, the invention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the claims. Like numbers refer to like elements throughout the description of the figures. In the figures, the dimensions of layers and regions are exaggerated for clarity. Each embodiment described herein also includes its complementary conductivity type embodiment.

[0020] It will be understood that when an element such as a layer, region or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present. It will be understood that if part of an element, such as a surface, is referred to as “inner,” it is farther from the outside of the device than other parts of the element. Furthermore, relative terms such as “beneath” or “overlies” may be used herein to describe a relationship of one layer or region to another layer or region relative to a substrate or base layer as illustrated in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. Finally, the term “directly” means that there are no intervening elements. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

[0021] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first region, layer or section discussed below could be termed a second region, layer or section, and, similarly, a second without departing from the teachings of the present invention.

[0022] Embodiments of the present invention will now be described, generally, with reference to GaN-based light-emitting diodes (LEDs) on SiC-based substrates. The present invention, however, is not limited to such structures. Embodiments of the invention may use other substrates including combinations, such as an AlGaInP diode on a GaP substrate, a GaN diode on a SiC substrate, an SiC diode on an SiC substrate, and/or a nitride-based diode on a gallium nitride, silicon carbide, aluminum nitride, zinc oxide and/or other substrate. Moreover, the present invention is not limited to the use of a diode region as an active region. Other types of active regions may also be used in accordance with some embodiments of the present invention.

[0023] Examples of light-emitting devices that may be used in embodiments of the present invention include, but are not limited to, the devices described in the following U.S. Pat. Nos. 6,201,262, 6,187,606, 6,120,600, 5,912,477, 5,739,554, 5,631,190, 5,604,135, 5,523,589, 5,416,342, 5,393,993, 5,338,944, 5,210,051, 5,027,168, 5,027,168, 4,966,862 and/or 4,918,497, the disclosures of which are incorporated herein by reference. Other suitable LEDs and/or lasers are described in U.S. patent application Ser. No. 10/140,796, entitled “GROUP III NITRIDE BASED LIGHT EMITTING DIODE STRUCTURES WITH A QUANTUM WELL AND SUPERLATTICE, GROUP III NITRIDE BASED QUANTUM WELL STRUCTURES AND GROUP III NITRIDE BASED SUPERLATTICE STRUCTURES”, filed May 7, 2002, as well as U.S. patent application Ser. No. 10/057,821, filed Jan. 25, 2002 entitled “LIGHT EMITTING DIODES INCLUDING SUBSTRATE MODIFICATIONS FOR LIGHT EXTRACTION AND MANUFACTURING METHODS THEREFOR” the disclosures of which are incorporated herein as if set forth fully. Furthermore, phosphor coated LEDs, such as those described in U.S. patent application Ser. No. 10/659,241 entitled “PHOSPHOR-COATED LIGHT EMITTING DIODES INCLUDING TAPERED SIDEWALLS, AND FABRICATION METHODS THEREFOR,” filed Sep. 9, 2003, the disclosure of which is incorporated by reference herein as if set forth full, may also be suitable for use in embodiments of the present invention.

[0024] The LEDs and/or lasers may be configured to operate in a “flip-chip” configuration such that light emission occurs through the substrate. In such embodiments, the substrate may be patterned so as to enhance light output of the devices as is described, for example, in U.S. patent application Ser. No. 10/057,821, filed Jan. 25, 2002 entitled “LIGHT EMITTING DIODES INCLUDING SUBSTRATE MODIFICATIONS FOR LIGHT EXTRACTION AND MANUFACTURING METHODS THEREFOR” the disclosure of which is incorporated herein by reference as if set forth fully herein.

[0025] Referring now to FIGS. 2A-2H , light-emitting devices and methods of forming same, in accordance with some embodiments of the present invention, will now be described. As shown in FIG. 2A , a substrate 205 , such as, for example, a SiC substrate, is provided. The substrate 205 has a first surface 210 a and a second surface 210 b and may be at least partially transparent to optical radiation. A buffer layer or layers 220 comprising, for example, aluminum nitride may be formed on the first surface 210 a of the substrate 205 as described in the above-incorporated U.S. Pat. Nos. 5,393,993, 5,523,589, 6,177,688, and application Ser. No. 09/154,363 entitled Vertical Geometry InGaN Light Emitting Diode.

[0026] Referring now to FIGS. 2B and 2C , an active region, such as, for example, a diode region comprising an n-type layer 225 and a p-type layer 230 may be epitaxially grown on the buffer layer 220 . The diode region, including the n-type layer 225 and/or the p-type layer 230 may comprise gallium nitride-based semiconductor layers, including alloys thereof, such as indium gallium nitride, aluminum gallium nitride, and/or aluminum indium gallium nitride. The fabrication of gallium nitride layers is described, for example, in the above-incorporated U.S. Pat. No. 6,177,688. The n-type gallium nitride layer 225 may comprise silicon-doped gallium nitride, while the p-type gallium nitride layer 230 may comprise magnesium-doped gallium nitride.

[0027] Referring now to FIG. 2D , an ohmic contact layer 235 may be formed on the p-type gallium nitride layer 230 . In accordance with various embodiments of the present invention, the ohmic contact layer 235 may comprise TIN, platinum, nickel/gold, nickel oxide/gold, nickel oxide/platinum, Ti, titanium/gold and/or alloys thereof. The ohmic contact layer 235 may have a thickness between about 10 Å and about 100 Å and may be at least partially transparent to optical radiation in accordance with some embodiments of the present invention.

[0028] Referring now to FIG. 2E , a via is formed through the substrate 205 , the buffer layer 220 , and the diode region 225 , 230 . In some embodiments, the via may be formed by etching the substrate 205 , the buffer layer 220 , and the diode region 225 , 230 using the ohmic contact layer 235 as an etch stop layer. Various etching techniques may be used in accordance with different embodiments of the present invention, including, but not limited to, wet etching, dry etching, and micro-machining.

[0029] Referring now to FIGS. 2F-2H , exemplary operations for forming a dielectric spacer on sides of the via will now be described. As shown in FIG. 2F , the via is at least partially filled with a dielectric material 240 . By using, for example, sol-gel technology, spin-on-glass, a polyimide material, silicon dioxide and/or silicon nitride the dielectric material 240 may be formed in the via in the liquid state and later etched after curing to a solid. A mask 245 is formed on the second surface 210 b of the substrate 205 and patterned so as to expose a portion of the dielectric material 240 as shown in FIG. 2G . Referring now to FIG. 2H , the dielectric material 240 is etched through the mask 245 so as to leave a dielectric spacer 240 a and 240 b on sides of the via. Various etching techniques may be used in accordance with different embodiments of the present invention, including, but not limited to, wet etching, dry etching, and micro-machining.

[0030] Referring now to FIG. 2I , a contact plug 250 is formed in the via by, for example, plating the via with a conductive material, such as gold, silver, gold alloys, and/or silver alloys, in accordance with some embodiments of the present invention.

[0031] Referring now to FIG. 2J , a first electrical contact 255 is formed adjacent to the second surface 210 b such that the contact plug 250 couples the first electrical contact 255 to the p-type gallium nitride layer 230 via the ohmic contact layer 235 . Advantageously, because the ohmic contact layer 235 contacts the p-type gallium nitride layer 230 across a relatively broad surface area, improved current spreading may be provided. The first electrical contact 255 for the p-type gallium nitride layer 230 may comprise platinum, nickel, titanium/gold and/or alloys thereof. In other embodiments, a reflective ohmic contact comprising, for example, alumilium and/or silver, may be used to implement the first electrical contact 255 .

[0032] As shown in FIG. 2J , one or more second electrical contact(s) 260 are formed on the second surface 210 b of the substrate 205 . The second electrical contact(s) 260 for the n-type gallium nitride layer 225 may comprise aluminum, titanium and/or alloys thereof. Other suitable materials that form ohmic contact to n-type gallium nitride may be used for the second electrical contact(s) 260 . Examples of ohmic contacts to n-type gallium nitride layers and p-type gallium nitride layers are described, for example, in the above-incorporated U.S. Pat. No. 5,767,581. FIG. 2K shows the structure of FIG. 2J inverted with the diode region on top of the substrate 205 .

[0033] Advantageously, light-emitting devices, according to some embodiments of the present invention, may allow electrical contacts to be coplanar on a non-active side of a substrate, which may obviate the need to use relatively thick diode regions to reduce current crowding when electrical contacts are made coplanar on the active side of the substrate. As a result, more active devices may be formed on a single wafer.

[0034] Embodiments of the invention have been described above in which a diode is shown as an example of an active region. It should be understood, however, that an active region may include, but is not limited to, quantum wells, heterojunctions, homojunctions, multiple layers, combinations of the foregoing, or the like, in accordance with some embodiments of the present invention. For example, layers 225 and 230 may be embodied as described in the above-referenced patents and/or applications. Moreover, additional layers, such as lattice strain layers, may also be incorporated in light-emitting devices in accordance with further embodiments of the present invention.

[0035] In concluding the detailed description, it should be noted that many variations and modifications can be made to the prefen-ed embodiments without substantially departing from the principles of the present invention. All such variations and modifications are intended to be included herein within the scope of the present invention, as set forth in the following claims.