DETAILED DESCRIPTION

[0021] The present invention relates to an improvement in signal modulators. The following description is presented to enable one of ordinary skill in the art to make and use the invention as provided in the context of a particular application and its requirements. Various modifications to the preferred embodiment will be apparent to those with skill in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the present invention is not intended to be limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.

[0022] FIG. 3 is a block diagram of a modulator using multi-phase clocks with an analog-front end. Analog front end 30 receives analog input x(t) that is an input signal to be modulated. The modulated output is modulated carrier θR generated from rotated clock ΦR from phase rotator 34 .

[0023] Analog front end 30 outputs digital signal x1(n) to up/down counter 32 , which increments or decrements the count and the phase selected by phase rotator 34 from multi-phase clocks 20 . The selected phase clock is output as rotated clock ΦR, which is divided by output divider 36 to generate modulated carrier θR. Modulated carrier θR can be transmitted over a communications medium.

[0024] Phase rotator 34 has two outputs. One output has a fixed phase, while the other output varies in phase in response to the input from up/down counter 32 . Phase rotator 34 has a fixed-phase output that always outputs the first clock Φ0 of multi-phase clocks 20 , regardless of the input from up/down counter 32 .

[0025] The other output of phase rotator 34 varies in phase. Up/down counter 32 controls phase rotator 34 's selection of multi-phase clocks 20 for rotated output ΦR. Output ΦR is input to output divider 36 , which generates θR. Thus a fixed clock Φ0 is output to feedback divider 38 , but a phase-varying clock ΦR is output to output divider 36 . The modulated carrier θR is generated by output divider 36 by dividing the rotated phase ΦR by N.

[0026] Feedback divider 38 generates un-modulated carrier θ 0 by dividing the first clock Φ0 of multiphase clocks 20 by N. Un-modulated carrier θ 0 is used as a clock to update up/down counter 32 and to clock analog front end 30 .

[0027] Analog front end 30 acts as a delta modulator and performs an analog-to-digital conversion. Analog input x(t) is converted to digital signal x1(n) that controls incrementing and decrementing of up/down counter 32 . Voltage comparator 28 compares the voltage of input x(t) to that of analog-estimate signal x2(t). Voltage comparator 28 can be a voltage summing or difference circuit.

[0028] Limiter 26 limits the voltage difference from comparator 28 , which is a voltage representing the voltage difference between analog input x(t) and analog-estimate signal x2(t). Positive differences produce a 1 output from limiter 26 , while negative differences produce a 0 output on x1(N). The resulting binary sequence x1(n) from limiter 26 is the delta-modulated sequence.

[0029] The digital sequence x1(n) is applied to up/down counter 32 , which counts up or counts down in response to x1(n). Binary sequence x1(n) is also clocked by θ 0 in D-flip-flop 22 and input to integrator 24 . Integrator 24 converts the small digital changes in x1(n) into small analog signals, and then accumulates the converted small analog signals to produce analog-estimate x2(t). Integrator 24 can be an op amp with a feedback capacitor from its output to its negative input and an input resistor to its negative input. The positive input of the op amp can be tied to signal-ground. Filtering can be provided to integrator 24 by adding a feedback resistor from the output to the negative input of the op amp. Whereas up/down counter 32 holds the digital value estimate of analog input x(t), integrator 24 holds the analog value estimate of x(t).

[0030] FIG. 4 is a waveform showing modulation phase changes in response to the analog input. In this simple example, several multi-phase clocks (Φ0:5) encode the input signal. The analog input x(t) is converted to digital signal x1(n), which increments and decrements up/down counter 32 ( FIG. 3 ). The output of up/down is determined by this output of up/down counter 32 .

[0031] The discrete phase changes on modulated carrier θR contain the digitized information for the analog input x(t). The discrete phase changes on θR follow analog input x(t). Modulated carrier θR can be transmitted over a communications medium and received by a receiver that contains a demodulator.

[0032] FIG. 5 shows a de-modulator using multi-phase clocks and conversion to an analog output. A phase-modulated signal θi is received from a communications medium and input to phase comparator 48 . Phase comparator 48 compares the phase of the received signal θi to the phase of the feedback signal θF. Phase differences increment or decrement up/down counter 42 .

[0033] The count value from up/down counter 42 is sent to phase rotator 44 , causing one of multi-phase clocks 20 to be selected as the rotated clock ΦR. The phase selected varies with changes in the count value from up/down counter 42 , which changes as a result of phase differences detected by phase comparator 48 .

[0034] The selected clock ΦR is divided by divider 46 to generate the feedback signal θF to phase comparator 48 . Up/down counter 42 is clocked by feedback signal θF.

[0035] The count value from up/down counter 42 changes in response to phase changes on the phase-modulated input θi. Thus the count value in up/down counter 42 represents the phase encodings of the input signal θi. The count value from up/down counter 42 is applied to converter 40 , which converts the digital count values to analog voltages of analog signal x'(t). Analog signal x'(t) is a reconstruction of analog signal x(t) of FIG. 3 , which was the analog input that was transmitted as phase-modulated signal θR and θi. Phase-modulated carrier θR ( FIG. 3 ) is the transmitted signal while input signal θi ( FIG. 5 ) is the received signal. Both contain the same phase-encoded information.

[0036] Converter 40 can be a D/A converter followed by a low-pass filter. Low pass filtering after the D/A smoothes out a stair-step waveform from the D/A.

[0037] FIG. 6 shows a phase modulator using multi-phase clocks that receives a digital signal for phase encoding. Up/down counter 62 is incremented or decremented to encode values of digital input x(n). The count value from up/down counter 62 is applied to phase rotator 64 , which selects one of multi-phase clocks 20 as the rotated clock ΦR. The phase of rotated clock ΦR varies with the count value from up/down counter 62 . The modulated output θR is generated by output divider 66 by dividing rotated clock ΦR by divisor N.

[0038] A constant-phase feedback clock Φ0 is also output by phase rotator 64 . Feedback clock Φ0 can be the first phase clock of multi-phase clocks 20 , or can be another phase clock of multi-phase clocks 20 . However, the phase of feedback clock Φ0 remains constant and does not vary with the count value from up/down counter 62 . Feedback divider 68 divides feedback clock Φ0 by a divisor N to generate feedback signal θ 0 , which clocks up/down counter 62 and bit mapper 60 .

[0039] Digital input signal x(n) is encoded by bit mapper 60 . Bit mapper 60 assigns a group of bits (a symbol) from digital input x(n) to a specific phase of the multiphase clocks. For example, the following mapping can be used for a group of 3 binary bits: 1

[0040] Bit mapper 60 also ensures that a smooth phase transition occurs from one phase assignment to the next phase assignment. For example, if the current phase assignment is Φ3 and the next phase assignment is Φ6, bit mapper 60 first transitions from Φ3 to intermediate phase assignments Φ4 and Φ5, before finally transitioning to Φ6. Similarly, if the current phase assignment is Φ3 and the next phase assignment is Φ1, bit mapper 60 first transitions from Φ1 to Φ2 before finally transitioning to Φ1. The smooth phase transition is accomplished by simply incrementing or decrementing the up/down counter by one rather than larger values. A current phase assignment can be maintained by disabling the up/down counter or using a multi-bit increment-decrement signal.

[0041] FIG. 7 is a waveform showing phase-encoding of a digital input using multi-phase clocks. Digital input signal x(t) is grouped into 2-bit symbols that change every 8 clock cycles as shown below the x-axis. The individual bit rate of x(t) is one bit per 4 clock cycles.

[0042] The duration of each phase assignment is a few clock cycles of the modulation carrier, feedback signal θ 0 . In this example, a 2-bit mapping assigned 2-bit symbols of x(t) to four possible phase assignments Φ0, Φ1, Φ2, and Φ3. There are 8 clock cycles of the modulation carrier θ 0 for each symbol mapping. Modulated carrier θR is the phase-modulated output.

[0043] When digital input x(n) changes by a large value, such as from 00 to 11, the phase assignment θR changes over several clock cycles. The bit mapper first changes from 00 to 01, incrementing the counter and causing Φ1 to be selected, then increments to 10, selecting Φ2, before finally incrementing the counter to 11, selecting the final phase Φ 3 .

[0044] FIG. 8 shows a de-modulator using multi-phase clocks with a digital output. Phase-modulated signal θi is received from a communications medium and input to phase comparator 58 . Phase comparator 58 compares the phase of the received signal θi to the phase of the feedback signal θF. Phase differences increment or decrement up/down counter 52 .

[0045] The count value from up/down counter 52 is sent to phase rotator 54 , causing one of multi-phase clocks 20 to be selected as the rotated clock ΦR. The phase selected varies with changes in the count value from up/down counter 52 , which changes as a result of phase differences detected by phase comparator 58 . The selected clock ΦR is divided by divider 56 to generate the feedback signal θF to phase comparator 58 . Up/down counter 52 is clocked by feedback signal θF.

[0046] The count value from up/down counter 52 changes in response to phase changes on the phase-modulated input θi. Thus the count value in up/down counter 52 represents the phase encodings of the input signal θi. The count value from up/down counter 52 is applied to data detector 50 , which converts the digital count values to digital encodings of digital output signal x'(n).

[0047] Digital output signal x'(n) is a reconstruction of digital signal x(n) of FIG. 6 , which was the input signal that was transmitted as phase-modulated signal θR and θi.

[0048] Phase-modulated carrier θR ( FIG. 6 ) is the transmitted signal while input signal θi ( FIG. 8 ) is the received signal. Both contain the same phase-encoded information.

[0049] Data detector 50 is clocked by a symbol clock. The symbol clock can be derived from θ0. The symbol clock indicates the symbol boundary of the phase assignments. Data detector 50 de-maps the phase assignments stored in up/down counter 52 to the original binary sequence x(n). Data detector 50 can also provide filtering to the count values from up/down counter 50 to remove any potential transients in the demodulator.

[0050] Frequency Offset

[0051] The set of multiphase clocks can have the same exact frequency as the one used for the phase-modulated signal if it is available locally. A set of multiphase clocks which has a small frequency offset relative to the phase-modulated signal can also be used in demodulating the signal. If the frequency offset is within 100 parts-per-million (ppm), for instance, one clock cycle could potentially slip after 10,000 clock cycles (or an error of one tenth of a clock cycle after 1,000 clock cycles). The invention can also take advantage of the small frequency offset to demodulate an incoming signal. This can be done by periodically synchronizing the demodulator.

[0052] The information to be transmitted can be first divided into smaller frames or packets. Data encoding can be used so that a unique pattern can be defined as a “frame sync pattern”. The frame sync pattern, which is used to synchronize the demodulator, marks the beginning of a frame transmission. The frame sync pattern is followed by a data field. The frame then terminates with an “idle pattern”. The idle pattern serves as a gap between frame transmissions. A simple 3-bit to 6-bit encoding is shown below: 2

[0053] Data encoding can be done by preceding the 3-bit data with 000. The pattern 000 001 010 011 (octal 0123) can be defined as the frame sync pattern since it is a unique pattern. Another unique pattern could be defined as the idle pattern.

[0054] The receiver constantly searches for the frame sync pattern (a sequence of 4 consecutive phase assignments: Φ0, Φ1, Φ2, Φ3), which indicates the beginning of a new frame. The receiver then decodes the data field based on the content of the up/down counter that corresponds to the frame sync pattern for each frame reception. Thus, if the frame sync pattern corresponds to octal 1234 of the up/down counter, then the up/down counter values 001, 010, 011, . . . 111, 000 with each preceded by 000 correspond respectively to the originally transmitted binary values of 000,001,010, . . . 110, 111.

[0055] The frame sync pattern would correspond to different values of the up/down counter over time due to the frequency offset.

[0056] The digital nature of this class of digital PLL/demodulator makes it amenable for an all-digital VLSI implementation, alleviating some of the technical difficulties encountered in mixed-signal design applications. The dynamic behavior of this class of digital PLL/demodulator is not only well behaved, but is also inherently stable. The very fine phase resolution that can be provided by the multiphase clocks enables this class of digital PLL/demodulator to operate at high frequency.

ALTERNATE EMBODIMENTS

[0057] Several other embodiments are contemplated by the inventor. For example additional components may be added, and inversions or active-low signals may be used. Banks of phase rotators may be used. A nested counter and nested phase rotators may be used to select the multi-phase clock in a multi-level scheme. Various filtering can be added, such as to smooth the loop responses. Rather than use the first multi-phase clock Φ0 for feedback, other multi-phase clocks could be selected as the fixed clock. The feedback and output dividers could use different divisors N, P rather than the same divisor. The multi-phase clocks could be a subset of the possible phases, such as by skipping every other phase, or only using one-quarter of the possible phases.

[0058] Voltage limiter 26 can be combined with comparator 28 in some implementations. The voltage limiter can be voltage comparator. A voltage summing or difference circuit could also be used. The integrator could also be a capacitor with a current source. Other implementations are possible.

[0059] Converter 40 of FIG. 5 can be a conventional digital-to-analog converter (DAC) using a variety of implementations, such as a table converter, current-summing, or other converters. The bit mapper of FIG. 6 can use different numbers of bits per symbol, such as four or eight bits per symbol, when more phases of multi-phase clocks are used for encoding. The up/down counter could have separate increment and decrement signals, or a combined increment/decrement signal, or multi-bit encoded inputs that function as the increment and decrement signal or signals.

[0060] The fixed-phase clock Φ0 could be one of the multi-phase clocks or it could be another clock with a same frequency as the multi-phase clocks, or could have a frequency already divided down from the frequency of the multi-phase clocks.

[0061] The phase rotator can be implemented using transmission gates, multiplexers, or other selection logic. Since the up/down counter is incremented and decremented by one, and does not jump by values greater than one per clock cycle during normal operation, the phase selected by the phase rotator only changes by one phase offset per clock cycle. Large phase shifts can take place over several clock cycles. Other encodings may be used, such a Manchester-type encodings.

[0062] The abstract of the disclosure is provided to comply with the rules requiring an abstract, which will allow a searcher to quickly ascertain the subject matter of the technical disclosure of any patent issued from this disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 C.F.R. § 1.72(b). Any advantages and benefits described may not apply to all embodiments of the invention. When the word “means” is recited in a claim element, Applicant intends for the claim element to fall under 35 USC § 112, paragraph 6. Often a label of one or more words precedes the word “means”. The word or words preceding the word “means” is a label intended to ease referencing of claims elements and is not intended to convey a structural limitation. Such means-plus-function claims are intended to cover not only the structures described herein for performing the function and their structural equivalents, but also equivalent structures. For example, although a nail and a screw have different structures, they are equivalent structures since they both perform the function of fastening. Claims that do not use the word means are not intended to fall under 35 USC § 112, paragraph 6. Signals are typically electric signals, but may be converted to optical signals such as can be carried over a fiber optic line as the communications medium, or converted to radio waves or other radiation for transmission over an “airwave” medium.

[0063] The foregoing description of the embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.