BEST MODE FOR CARRYING OUT THE INVENTION

[0091] The following explains the best mode for carrying out the present invention with describing some preferable Embodiments and referring to the drawings.

EMBODIMENT 1

[0092] FIG. 1 is a block diagram showing data exchanges between a flash memory card 10 according to Embodiment 1 of the present invention and a host H. The flash memory card 10 is connected with the host H through the following five types of lines. The lines are composed of nine lines in total; four data lines DAT 0 - 3 , a clock line CLK, a power line VDD, two ground lines VSS 1 and VSS 2 , and a command line CMD.

[0093] A host interface 1 is the circuit for performing communications directly with the host H through the above-mentioned nine lines. The host interface 1 receives commands from the host H through the command line CMD and decodes the commands. After that, the host interface performs, for example, the following operations in response to the commands. When a command from the host H is a read command, the host interface 1 decodes the command into the logical address AL of the read target and sends the address to a flash memory controller 3 . When a command from the host H is a write command, the host interface 1 decodes the command into the logical address AL of the write target and sends the address to the flash memory controller 3 . On the other hand, the host interface 1 reads data objects to be written from the data lines DAT 0 - 3 in synchronization with a transfer clock received from the clock line CLK, and stores the data objects in the buffer 2 . When a command from the host H is an erase command, the host interface 1 decodes the command into the logical address AL of the erase target and sends the address to the flash memory controller 3 .

[0094] The buffer 2 is an SRAM preferably, and temporarily stores the data objects Da exchanged between the host interface 1 and the flash memory controller 3 . Thereby, the host interface 1 and the flash memory controller 3 can exchange data objects Da with each other without obstructed by a difference in operating speeds, that is, a difference in frequency between the transfer clock CLK from the host H and the internal clock of the flash memory card 10 . In addition, the buffer 2 provides the host interface 1 and the flash memory controller 3 with respective working memory spaces.

[0095] Flash memories 4 are NAND-type EEPROM (electrically erasable programmable ROM) preferably, and include a page buffer 4 a, a cell array 4 b, an address decoder 4 c, and an erasing circuit 4 d.

[0096] FIG. 2 is a schematic diagram showing the structure of the cell array 4 b. The cell array 4 b is an assembly of a plurality of the physical blocks B 0 , B 1 , B 2 , . . . Each of the physical blocks is the following two-dimensional arrangement of many memory cells: eight memory cells connected in the NAND type compose one line, and 512 lines compose one page. Furthermore, a redundant area composed of 16 lines is added to every one page. The arrangement of one page with the addition of the redundant area composes one unit, and 32 units compose one physical block. For example, the first physical block B 0 includes 32 pages P 0 -P 31 . The redundant areas Pr 0 -Pr 31 of 16 bytes each are added to the respective pages P 0 -P 31 . Similarly, the second physical block B 1 includes 32 pages Q 0 -Q 31 , and the redundant areas Qr 0 -Qr 31 are added to the respective pages Q 0 -Q 31 . Likewise other of the physical blocks B 2 , B 3 , Since one memory cell stores one bit data, in the cell array 4 b, 8 bits=1 byte are stored per one line, 512 bytes per one page, and 512 bytes×32=16 kB per one physical block. Furthermore, in Embodiment 1, the cell array 4 b comprises 210=1024 of the physical blocks, thus comprising the storage capacity of 16 kB×1024=16 MB.

[0097] The flash memory 4 comprises, for example, two page buffers 4 a. Each of the page buffers 4 a can store one-page data. When data is written into the cell array 4 b, data items Da from the flash memory controller 3 , in groups of 2×512 bytes, are temporarily stored in the two page buffers 4 a. Furthermore, the data items are written in parallel from the respective page buffers 4 a onto two separate pages in the cell array 4 b. When data is read from the cell array 4 b, data items are read in parallel from two separate pages inside the cell array 4 b, and temporarily stored in the two respective page buffers 4 a. Furthermore, the data items are transferred in parallel from the two page buffers 4 a to the flash memory controller 3 as a series of data Da.

[0098] Two target pages of writing or reading are selected from separate physical blocks. For example, the two pages hatched in FIG. 2 , that is, the first pages P 0 and Q 0 of the first physical block B 0 and the second physical block B 1 , respectively, are selected. Similarly, from one of the odd-numbered physical blocks and one of the even-numbered physical blocks, the respective pages at corresponding positions are selected. At that time, the address decoder 4 c performs the selection according to the physical address AP received from the flash memory controller 3 . The two-page pair inside the cell array 4 b selected in such a manner is hereafter referred to as one area.

[0099] The erasing circuit 4 d applies a high voltage across the physical block corresponding to the physical address AP received from the flash memory controller 3 , thereby collectively erasing data stored inside the physical block. In order to perform the data erasing separately in each of the physical blocks at that time, the physical blocks inside the cell array 4 b are electrically insulated from each other.

[0100] The flash memory controller 3 performs data input/output control over the flash memory 4 using the components described as follows.

[0101] An address conversion section 3 a receives a logical address AL from the host interface 1 . Furthermore, the section selects the area corresponding to the logical address AL from the inside of the cell array 4 b of the flash memory 4 , and converts the logical address AL into the physical address AP of the area. The address conversion section 3 a assigns generally more than one physical address AP of area to one logical address AL. Furthermore, the section classifies a plurality of the areas corresponding to the same logical address AL into three states, namely, blank, enabled, and disabled states, and selects the physical addresses AP of the areas according to the respective states.

[0102] The blank state represents that data has not yet been written in the area after the erasure of data. On the other hand, the enabled and disabled states are the states of the area in which data is written. The enabled and disabled states represent that the read section 3 b is allowed to read and prohibited from reading data from the area, respectively.

[0103] Information about the state of each area is stored in the redundant area added to each page of the flash memory 4 (such as the redundant area Pr 0 corresponding to the page P 0 ). In particular, the common information about the state of the area is stored in the redundant areas of the pages belonging to the same area.

[0104] The address conversion section 3 , at startup of the flash memory card 10 , checks the states of all the areas inside the cell array 4 b of the flash memory 4 . Furthermore, the section creates, inside the buffer 2 , a table 2 a regarding the state of each of the areas (which is hereafter referred to as a state table). The state table 2 a is, for example, a list of the physical addresses of areas, the logical addresses corresponding to the areas, and the information about the states of the areas.

[0105] When a logical address AL shows a target of reading data, the address conversion section 3 a consults the state table 2 a, thereby selecting an enabled area from among the areas inside the cell array 4 b corresponding to the logical address AL. The read section 3 b sends the physical address AP of the enabled area to the flash memory 4 . The address decoder 4 c decodes the physical address AP entered into the flash memory 4 . Thereby, data items are read in parallel from the respective pages belonging to the area inside the cell array 4 b corresponding to the physical address AP into the two page buffers 4 a. The read section 3 b transfers the data items Da from the page buffers 4 a to the buffer 2 .

[0106] When a logical address AL shows a target of writing data, the address conversion section 3 a consults the state table 2 a, thereby selecting blank areas from the inside of the cell array 4 b. Furthermore, the section assigns the physical addresses AP of the blank areas to the logical address AL of the write target. The write section 3 c transfers the data objects Da to be written, in groups of 2×512 bytes, from the buffer 2 to the page buffers 4 a inside the flash memory 4 . In conjunction with that, the section sends the physical address AP of the blank area selected by the address conversion section 3 a to the flash memory 4 . The address decoder 4 c decodes the physical address AP entered in the flash memory 4 . Thereby, data items are written in parallel from the different page buffers 4 a onto the respective pages belonging to the area inside the cell array 4 b corresponding to the physical address AP. Furthermore, at the end of the data writing, the address conversion section 3 updates the state table 2 a and rewrites the item regarding the state of the write target area from “blank” to “enabled”.

[0107] As described above, the writing and reading of data into and from the flash memory 4 are performed through the two page buffers 4 a on an area-by-area basis, that is, one page each of the two separate physical blocks in parallel. Thus, the flash memory card 10 according to Embodiment 1 shortens the writing and reading durations for the flash memory 4 .

[0108] When a logical address AL shows a target of erasing data, the address conversion section 3 a identifies the physical address AP of the physical block corresponding to the logical address AL. An erase section 3 d sends the physical address AP of the erasing target identified by the address conversion section 3 a to the erasing circuit 4 d inside the flash memory 4 . The erasing circuit 4 d stops the address decoder 4 c, and applies a predetermined high voltage across the physical block corresponding to the received physical address AP, thereby performing the erasing of data for the physical block. Furthermore, at the end of the data erasing, the address conversion section 3 updates the state table 2 a and rewrites “enabled” into the items regarding the states of all the areas inside the physical block of the erasing target.

[0109] At the time of the data writing, the address conversion section 3 a consults the state table 2 a along with the above-described operations, and retrieves an enabled area among the areas of the physical addresses corresponding to the logical address AL of the write target. When the writing requested by the host H is the overwriting of data, generally an enabled area exists in the areas of the physical addresses corresponding to the logical address AL. Then, a page-disabling section 3 e disables the enabled area as described bellow. Furthermore, the address conversion section 3 updates the state table 2 a, and rewrites the item regarding the state of the area from “enabled” to “disabled.” Thereby, the read section 3 b is prohibited from accessing to the area.

[0110] The page-disabling section 3 e rewrites data inside the redundant area corresponding to the enabled page, thereby disabling the page. For example, it is defined that a page is enabled and disabled when the predetermined one bit (flag) inside the redundant area is “1” and “0,” respectively. Since the flag corresponding to the enabled page is “1,” the page-disabling section 3 e changes the flag from “1” to “0,” in other words, writes “0” into the flag inside the redundant area, thereby disabling the page.

[0111] As described above, the flash memory card 10 according to Embodiment 1, when requested the overwriting of data by the host H, writes new data in another area without erasing the original data. Furthermore, the card assigns the physical address of the area in which the new data is written to the logical address of the write target. In addition, the card disables states of the areas at the other physical addresses corresponding to the logical address. Thereby, when receiving from the host a read command aimed at the logical address, the read section 3 b can access only the area storing the latest data items among a plurality of the areas corresponding to the logical address. Thus, the overwriting of data at the same logical address is realized without entailing an erasure of data in the flash memory 4 . Therefore, the overwriting duration shortens by the erasing duration.

[0112] The flash memory card 10 according to Embodiment 1 further comprises a merge control section 3 f inside the flash memory controller 3 . As described above, the overwriting of data produces disabled pages. Accordingly, the rate of the disabled areas to the enabled areas increases when the overwriting of data is repeated. The merge control section 3 f controls the read section 3 b, the write section 3 c, the erase section 3 d, and the page-disabling section 3 e as follows, thereby copying data on the enabled pages inside a predetermined physical block onto the blank pages inside other physical blocks. Furthermore, the merge control section erases the original data in the physical block, thereby increasing the number of the physical blocks including only blank pages (the blank physical blocks). As a result, the rate of the disabled areas to the enabled areas can be reduced.

[0113] FIG. 3 is a flow chart about the operation of the merge control section 3 f.

[0114] The merge control section 3 f starts up at the time of writing of data into the flash memory 4 .

[0115] Step S 1 :

[0116] The merge control section 3 f consults the state table 2 a inside the buffer 2 and counts the number N of the blank physical blocks.

[0117] Step S 2 :

[0118] The number N of the blank physical blocks counted in Step S 1 is compared with each of the first threshold value th 1 and the second threshold value th 2 . Here, the first threshold value th 1 and the second threshold value th 2 are, for example, equal to about 50% and about 20% of the number of all the physical blocks inside the cell array 4 b, respectively. Furthermore, the merge control section 3 f causes the process to branch as follows, depending on the result of comparison: (1) The merge control section 3 f stops when the number N of the blank physical blocks is equal to or more than the first threshold value th 1 (N≧th 1 ). (2) The merge control section 3 f performs the first merge process S 3 when the number N of the blank physical blocks is smaller than the first threshold value th 1 and equal to or more than the second threshold value th 2 (th 2 ≦N<th 1 ). (3) The merge control section 3 f performs the second merge process S 4 when the number N of the blank physical blocks is smaller than the second threshold value th 2 (N<th 2 ).

[0119] Through Step S 1 and Step S 2 , the merge control section 3 f performs the following merge process only when the number N of the blank physical blocks is smaller than the first threshold value th 1 , in other words, only when the remaining area available for the data writing is small. Thus, the flash memory card 10 according to Embodiment 1 limits the extension of the writing duration due to the merge process.

[0120] <The First Merge Process S 3 >

[0121] FIG. 4 is a flow chart about the first merge process S 3 . FIG. 5 is a schematic diagram showing changes in the states of the pages inside the cell array 4 b during the first merge process S 3 . In Embodiment 1, the corresponding pages in one of the odd-numbered physical blocks and one of the even-numbered physical blocks belong to the same area. Furthermore, the data input/output operations are performed area by area in parallel. Accordingly, the changes in states of pages are substantially common between the odd-numbered physical blocks and the even-numbered physical blocks. Therefore, FIG. 5 shows only the odd-numbered physical blocks inside the cell array 4 b.

[0122] FIG. 5 represents the data items stored in the respective areas P 0 , P 1 , P 2 , . . . as the reference symbols D 0 , D 1 , D 2 , . . . written inside the boxes showing the respective areas. In addition, the states of the areas are represented as the numerals 1 and 0 written inside the boxes showing the corresponding redundant areas Pr 0 , Pr 1 , Pr 2 , . . . Here, the numerals 1 and 0 show the enabled and disabled states, respectively. Furthermore, the states of the areas are blank when the boxes showing the areas are blank.

[0123] Substep S 31 :

[0124] As shown in (a) of FIG. 5 , new data items (for example, d 1 , d 2 , and d 3 ) are written into the blank areas. Then, the merge control section 3 f obtains the number k (for example, 3) of the blank areas in which the new data items are written.

[0125] Substep S 32 :

[0126] The merge control section 3 f consults an address table 2 b inside the buffer 2 , and selects the physical block BL as a source of copying in decreasing order of the number of the disabled areas, the physical block including the largest number of the disabled areas first. Here, the address table 2 b is a list of the addresses of the physical blocks and the numbers of the disabled pages belonging to the physical blocks. For example, the top physical block BL is selected as the source physical block in (a) of FIG. 5 .

[0127] Substep S 33 :

[0128] The merge control section 3 f consults the state table 2 a inside the buffer 2 , and selects the same number of the enabled areas of the source physical block BL as the number of the areas obtained in Substep S 31 , that is, k areas in order, the top area P 0 first. For example, the three enabled areas P 0 , P 1 , and P 3 are selected in (a) of FIG. 5 . Here, when the number of the enabled areas inside the source physical block BL is smaller than k, Substep S 32 is performed again, and thereby another physical block is selected as a source physical block and the rest of the enabled areas are selected from the physical block.

[0129] Substep S 34 :

[0130] The merge control section 3 f consults the state table 2 a inside the buffer 2 and selects the same number of blank areas as the number of the areas obtained in Substep S 31 , that is, k areas from a physical block different from the source physical block BL. For example, the three blank areas CP 0 , CP 1 , and CP 3 are selected in (a) of FIG. 5 .

[0131] Substep S 35 :

[0132] The merge control section 3 f reads data items from the enabled areas selected in Substep S 33 using the read section 3 b. The data items read are temporarily stored in the buffer 2 . Furthermore, the merge control section 3 f writes the data items temporarily stored in the buffer 2 into the respective blank areas selected in Substep S 34 using the write section 3 c. Thus, data items on the k enabled areas inside the source physical block BL are copied into the respective blank areas of the other physical blocks. For example, the data items D 0 , D 1 , and D 3 in the three enabled areas P 0 , P 1 , and P 3 inside the source physical block BL are copied into the three blank areas CP 0 , CP 1 , and CP 3 , respectively, in (a) of FIG. 5 .

[0133] Substep S 36 :

[0134] The merge control section 3 f disables the k enabled areas inside the source physical block BL using the page-disabling section 3 e. In (b) of FIG. 5 , for example, data in the redundant areas Pr 0 , Pr 1 , and Pr 3 corresponding to the three enabled areas P 0 , P 1 , and P 3 inside the source physical block BL is changed from “1” to “0.” Furthermore, the merge control section 3 f updates the state table 2 a inside the buffer 2 , and rewrites the items regarding the states of the k enabled areas inside the source physical block BL from “enabled” to “disabled.” In conjunction with that, the merge control section 3 f updates the address table 2 b inside the buffer 2 based on the state table 2 a updated.

[0135] Substep S 37 :

[0136] The merge control section 3 f consults the state table 2 a inside the buffer 2 and selects the physical block including only disabled areas, or alternatively, only a large number of disabled areas and a small number of blank areas, and assigns the physical block as an erasing target physical block BE. In (c) of FIG. 5 , for example, the top physical block BE is selected as an erasing target since the states of all the areas inside the physical block BE are disabled.

[0137] Substep S 38 :

[0138] It is checked whether an erasing target physical block BE can be selected in Substep S 37 . The merge control section 3 f causes the process to branch to Substep S 39 when an erasing target physical block BE exists, and finishes the first merge process S 3 at other times.

[0139] Substep S 39 :

[0140] The merge control section 3 f performs the erasing of data for the erasing target physical block BE using the erase section 3 d. In (d) of FIG. 5 , for example, all the boxes showing the areas inside the erasing target physical block BE are drawn as blank boxes so as to represent that the states of all the areas are changed into blank states. After the end of the data erasing, the merge control section 3 f updates the state table 2 a inside the buffer 2 , and rewrites “enabled” into the items regarding the states of all the areas of the erasing target physical block BE. In conjunction with that, the merge control section 3 f updates the address table 2 b inside the buffer 2 based on the state table 2 a updated. Then, the merge control section 3 f repeats the process from Substep S 37 .

[0141] As described above, the first merge process S 3 is performed at every time of the data writing when the number N of the blank physical blocks is smaller than the first threshold value th 1 . Generally the amounts of the data objects to be written are equal to the storage capacity on the order of the integral multiple of the physical block. On the other hand, in Substep S 33 , the merge control section 3 f selects enabled areas as many as the areas in which new data is written. Accordingly, generally the number of the physical blocks that become erasable through the first merge process S 3 can be adjusted on the order of the number of the blank physical blocks consumed by the writing of new data, especially when data is overwritten into the same logical address. As a result, the flash memory card 10 according to Embodiment 1 can suppress an increase in the rate of the disabled areas to the enabled areas at the time of the repetition of the overwriting of data.

[0142] <The Second Merge Process S 4 >

[0143] FIG. 6 is a flow chart about the second merge process S 4 . FIG. 7 is a schematic diagram showing changes in the states of the pages inside the cell array 4 b during the second merge process S 4 . FIG. 7 shows only the odd-numbered physical blocks inside the cell array 4 b in a manner similar to FIG. 5 . Furthermore, data items stored in the areas and the states of the areas are shown as reference symbols similar to those shown in FIG. 5 .

[0144] Substep S 41 :

[0145] The merge control section 3 f prohibits the write section 3 c from writing new data in contrast to the time of the first merge process S 3 .

[0146] Substep S 42 :

[0147] The merge control section 3 f consults the address table 2 b inside the buffer 2 and selects the source physical block BL in decreasing order of the number of the disabled areas, the physical block including the largest number of the disabled areas first, in a manner similar to Substep S 32 of the first merge process S 3 . In (a) of FIG. 7 , for example, the top physical block BL is selected as the source physical block.

[0148] Substep S 43 :

[0149] The merge control section 3 f consults the state table 2 a inside the buffer 2 and selects all the enabled areas inside the source physical block BL. In (a) of FIG. 7 , for example, all the enabled areas P 0 and P 3 inside the physical block BL are selected.

[0150] Substep S 44 :

[0151] The merge control section 3 f consults the state table 2 a inside the buffer 2 and selects blank areas as many as the enabled areas selected in Substep S 43 from a physical block different from the source physical block BL. In (a) of FIG. 7 , for example, the top two areas CP 0 and CP 1 inside the one Bn of the blank physical blocks are selected.

[0152] Substep S 45 :

[0153] The merge control section 3 f reads data items from the enabled areas selected in Substep S 43 using the read section 3 b. The data items read are temporarily stored in the buffer 2 . Furthermore, the merge control section 3 f writes the data items temporarily stored in the buffer 2 into the respective blank areas selected in Substep S 44 using the write section 3 c. Thus, the data items in all the enabled areas inside the source physical block BL are copied into the respective blank areas of another physical block. In (a) of FIG. 7 , for example, the data items D 0 and D 3 in the enabled areas P 0 and P 3 inside the source physical block BL are copied into the two blank areas CP 0 and CP 1 of the blank physical block Bn, respectively.

[0154] Substep S 46 :

[0155] The merge control section 3 f selects the source physical block BL as an erasing target physical block BE as shown in (b) of FIG. 7 . Furthermore, the section performs the erasing of data for the erasing target physical block BE using the erase section 3 d. In (c) of FIG. 7 , for example, all the boxes showing the areas inside the erasing target physical block BE are drawn as blank boxes so as to represent that the states of all the areas are changed into blank states. After the end of the data erasing, the merge control section 3 f updates the state table 2 a inside the buffer 2 and rewrites “enabled” into the items regarding the states of all the areas inside the erasing target physical block BE. In conjunction with that, the merge control section 3 f updates the address table 2 b inside the buffer 2 based on the state table 2 a updated.

[0156] As described above, the second merge process S 4 is performed when the number N of the blank physical blocks is smaller than the second threshold value th 2 . At that time, the writing of new data is prohibited, and the producing of an increase in the number N of the blank physical blocks through Substeps S 42 -S 46 is placed on a higher priority. Thereby, the rate of the disabled areas to the enabled areas is reduced so that the number N of the blank physical blocks is secured at or beyond the second threshold value th 2 . As a result, the flash memory card 10 according to Embodiment 1 increases the amounts of data that can be stored therein.

[0157] The flash memory 4 comprises the two page buffers 4 a in Embodiment 1. Alternatively, the flash memory may comprise only one page buffer, or three or more of the page buffers.

EMBODIMENT 2

[0158] FIG. 8 is a block diagram showing data exchanges between a flash memory card 10 A according to Embodiment 2 of the present invention and a host H. The flash memory card 10 A according to Embodiment 2 comprises two flash memories in contrast to the counterpart 10 of Embodiment 1 ( FIG. 1 ). In FIG. 8 , components similar to those of Embodiment 1 are marked with the same reference symbols as those of Embodiment 1. Furthermore, the description of Embodiment 1 is cited regarding those similar components.

[0159] A flash memory controller 3 A and two flash memories 4 A and 4 B according to Embodiment 2 are really similar in internal structure to their respective counterparts 3 and 4 of Embodiment 1, and therefore FIG. 1 is cited regarding them.

[0160] The duration of data transfer between the flash memory controller 3 A and the flash memory 4 A or 4 B inside the page buffers 4 a is on the order of several tens of nsec. On the other hand, the duration of writing data from the page buffer 4 a into the cell array 4 b is on the order of several hundreds of nsec. Using the difference between those processing times, the flash memory controller 3 A according to Embodiment 2 performs a writing operation of data into one of the flash memories and a merge process in the other of the flash memories in parallel as described bellow. Thereby, the extension of the writing duration due to the merge process can be reduced compared with that of the flash memory card 10 according to Embodiment 1.

[0161] For example, when writing data into the first flash memory 4 A, a write section 3 c inside the flash memory controller 3 A transfers the data object Da to be written into the first flash memory 4 A area by area, in a manner similar to that of Embodiment 1. The merge control section 3 f inside the flash memory controller 3 A, at every time of the transfer of the one area, starts up and performs Step S 1 and Step S 2 for the second flash memory 4 B in a manner similar to that of Embodiment 1. The merge control section 3 f further performs the first merge process S 3 or the second merge process S 4 according to the result of the comparison in Step S 2 , in a manner similar to that of Embodiment 1.

[0162] <The First Merge Process S 3 >

[0163] In the first merge process S 3 according to Embodiment 2, in contrast to that of Embodiment 1, the merge control section 3 f obtains in Substep S 31 the number of the areas in which new data is written inside the first flash memory 4 A. In Substep S 33 , enabled areas as many as the areas in which new data is written inside the first flash memory 4 A are selected from the source physical block inside the second flash memory 4 B. Thereby, one area of the second flash memory 4 B is copied into another area in parallel with the writing of data in one area into the first flash memory 4 A. Furthermore, the number of the target areas of the first merge process S 3 in the second flash memory 4 B is equal to the number of the write target areas in the first flash memory 4 A. Accordingly, the duration required of the first merge process S 3 in the second flash memory 4 B is nearly equal to the writing duration in the first flash memory 4 A. As a result of the above-described operations, the extension of the writing duration due to the first merge process S 3 can be reduced in Embodiment 2, compared with that in Embodiment 1.

[0164] <The Second Merge Process S 4 >

[0165] In the second merge process S 4 according to Embodiment 2, in contrast to that of Embodiment 1, the merge control section 3 f allows the data writing into the first flash memory 4 A. Thereby, the data writing into the first flash memory 4 A can be performed in parallel with the second merge process S 4 in the second flash memory 4 B. Therefore, the extension of the writing duration due to the second merge process S 4 can be reduced in Embodiment 2, compared with that in Embodiment 1.

EMBODIMENT 3

[0166] FIG. 9 is a block diagram showing data exchanges between a flash memory card 10 B according to Embodiment 3 of the present invention and a host H. The flash memory card 10 B according to Embodiment 3 comprises two flash memories in a manner similar to the counterpart 10 A of Embodiment 2 ( FIG. 8 ). In FIG. 9 , components similar to those of Embodiment 1 are marked with the same reference symbols as those of Embodiment 1. Furthermore, the description of Embodiment 1 is cited regarding those similar components.

[0167] The two flash memories 4 A and 4 B according to Embodiment 3 are really similar in internal structure to their counterpart 4 of Embodiment 1, and therefore FIG. 1 is cited regarding them.

[0168] A flash memory controller 3 B according to Embodiment 3 substantially includes two internal structures each of which is similar to that of its counterpart 3 according to Embodiment 1. Of the internal structures similar to that of the flash memory controller 3 according to Embodiment 1, the one is connected to the first flash memory 4 A, and separately the other is connected to the second flash memories 4 B. Furthermore, the internal structures are separately connected to the buffer 2 B through the separate data buses. Because of such composition, the flash memory card 10 B according to Embodiment 3 can perform the writing operation and the merge process in parallel for the two flash memories 4 A and 4 B in a manner similar to that of Embodiment 2. In contrast to Embodiment 2, in particular, data transmissions between the buffer 2 B and the flash memory controller 3 B and data transmissions between the flash memory controller 3 B and the flash memories 4 A and 4 B are also performed in parallel. Accordingly, the writing duration can further shorten by the data transfer duration compared with that of Embodiment 2.

[0169] As described above, the flash memory system according to the present invention can copy data on the enabled pages inside a predetermined physical block into other physical blocks. Furthermore, at the end of the copying of data on all the enabled pages inside the predetermined physical block, the system can erase collectively data in the physical block. Through such a merge process, the flash memory system according to the present invention can erase data on the disabled pages inside the physical block including enabled pages, in contrast to conventional systems. Accordingly, the flash memory system according to the present invention can reduce the rate of the disabled pages to the enabled pages. As a result, the amount of data that can be stored at the time of the repetition of the overwriting of data is larger than those of the conventional systems.

[0170] The flash memory system according to the present invention may further perform the above-described merge process when new data is written therein and the number of blank physical blocks is smaller than the first threshold value. Thus, the above-described flash memory system can reduce the extension of the writing duration due to the copying of data by the restriction of the execution timing of the merge process.

[0171] The flash memory system according to the present invention may adjust the number of the source pages to be equal to or more than the number of the pages on which new data is written. Thereby, when data is overwritten at the same logical address, the system can adjust the number of the physical blocks erased in the above-described merge process to be on or beyond the order of the number of the blank physical blocks consumed by the writing of new data. As a result, the system can avoid an increase in the rate of the disabled pages to the enabled pages at the time of the repetition of the overwriting of data. Therefore, the system can increase the amounts of data that can be stored.

[0172] The flash memory system according to the present invention may provide the above-described merge process with a higher priority than the writing operation of new data when the number of the blank physical blocks is smaller than the second threshold value. Thereby, the system can reduce the rate of the disabled pages to the enabled pages so as to secure the number of the blank physical blocks on or beyond the order of the second threshold value. As a result, the system can increase the amounts of data that can be stored.

[0173] The second threshold value is smaller than the first threshold value when the above-described flash memory system performs both of the operation in the case of the number of the blank physical blocks equal to or smaller than the first threshold value and the operation in the case of the number equal to or smaller than the second threshold value. Thereby, the merge process does not take precedence over the writing operation of new data until the blank physical blocks are too small in number to allow the writing of new data therein. As a result, the extension of the writing duration due to the merge process can be reduced.

[0174] The flash memory system according to the present invention may comprise a list of the addresses of the physical blocks and the numbers of the disabled pages belonging to the physical blocks. The above-mentioned list is consulted at the time of the selection of the source physical block in the above-described merge process. Thereby, the source physical block is selected easily and quickly in decreasing order of the number of the disabled areas, the physical block including the largest number of the disabled areas first. As a result, the time required to the above-described merge process shortens since the number of the enabled pages targeted for the above-described merge process is minimized.

[0175] The above-described disclosure of the invention in terms of the presently preferred embodiments is not to be interpreted as intended for limiting. Various alterations and modifications will no doubt become apparent to those skilled in the art to which the invention pertains, after having read the disclosure. As a corollary to that, such alterations and modifications apparently fall within the true spirit and scope of the invention. Furthermore, it is to be understood that the appended claims be intended as covering the alterations and modifications.

[0176] Industrial Applicability

[0177] According to the present invention, for flash memories, the per-physical-block rate of the disabled pages to the enabled pages can be maintained low enough. Thereby, a substantial increase in the storage capacity can be achieved for the flash memories. Therefore, the industrial applicability in the present invention is very high.