Ware, Frederick (Los Altos Hills, CA, US)
Best, Scott (Palo Alto, CA, US)
Chang, Timothy (Saratoga, CA, US)
Perego, Richard (San Jose, CA, US)
Tsern, Ely (Los Altos, CA, US)
Mitchell, Jeff (Santa Clara, CA, US)

10/768443

09/23/2004

01/30/2004

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324/763

(IPC1-7): H04L005/16; G01R031/02

VIERRA MAGEN MARCUS HARMON & DENIRO LLP (685 MARKET STREET, SUITE 540, SAN FRANCISCO, CA, 94105, US)

1. A semiconductor device, comprising: a test circuit; a first element; and a second element comprising at least one of a transmitter and a receiver; wherein when the first element is coupled to the test circuit and the second element is coupled to the first element, at least one of the first and second elements is capable of testing another one of the first and second elements using the test circuit; and the first element comprises a transmitter when the second element comprises a receiver and the first element comprises a receiver when the second element comprises a transmitter.

2. The semiconductor device of claim 1, wherein the semiconductor device is configured to operate at high frequencies.

3. The semiconductor device of claim 1, wherein the semiconductor device is configured to operate at a frequency of at least 1 Gigahertz.

4. The semiconductor device of claim 1, wherein the semiconductor device is configured to operate at a frequency of at least 3 Gigahertz.

5. The semiconductor device of claim 1, wherein the test circuit includes a pattern generator and a pattern compare circuitry.

6. The semiconductor device of claim 1, wherein the semiconductor device is configured to be coupled to at least one reference signal that includes a voltage reference signal, V_REF, and wherein the test circuit includes at least one comparator circuit for comparing at least one voltage signal representing received data with the V_REF signal.

7. The semiconductor device of claim 6, wherein the at least one reference signal further includes a time reference signal, T_REF, and the high bandwidth test circuit includes at least one analog sampling circuit controlled by the T_REF signal, wherein the analog sampling circuit receives at least one voltage signal representing received data, such that T_REF determines a time offset between receipt of the at least one voltage signal by the receiver and evaluation of the voltage signal by the receiver.

8. The semiconductor device of claim 7, wherein the T_REF signal is scannable so as to characterize an actual output eye of the transmitter.

9. The semiconductor device of claim 7, wherein the T_REF signal is scannable so as to characterize an actual input eye of the receiver.

10. The semiconductor device of claim 1, wherein the semiconductor device is coupled to an interconnect to receive and transmit a complementary voltage value V_N and a true voltage value V_P, wherein the test circuit further comprises: a test pattern generation circuit that generates test patterns for transmission to a component under test; a test pattern comparison circuit that compares a generated test pattern with a pattern received from a component under test; a first differential comparator that compares V_N with a voltage reference value, V_REF to produce a first result; a second differential comparator that compares V_P with a voltage reference value, V_REF to produce a second result; and a multiplexer that selects one of the first result and the second result to transmit to the comparator for comparison with the test pattern.

11. The semiconductor device of claim 10, wherein the test circuit further comprises an analog sampling circuit that delays the V_P and V_N signals under control of a T_REF signal so as to decouple parameters of the transmitter and the receiver.

12. The semiconductor device of claim 11, wherein the delayed V_P and V_N signals produce a third result, and wherein the multiplexer further selects one of the first result, the second result, and the third result to transmit to the comparator for comparison with the test pattern.

13. The semiconductor device of claim 12, wherein the transmitter is coupled to the receiver via an interconnect, and wherein the transmitter and the receiver are on a semiconductor wafer.

14. The semiconductor device of claim 12, wherein the transmitter is coupled to the receiver via an interconnect, wherein the interconnect is in a system and is used for system communication between the transmitter and the receiver.

15. A semiconductor circuit component coupleable to an external receiver and an external transmitter, the semiconductor component comprising: a first transmitter coupled to a first signal path and configurable to drive a first signal according to predetermined transmitter specification parameters; and a first receiver coupled to a second signal path and configurable to sample a second signal according to predetermined receiver specification parameters, wherein, when the component is configured to operate in a first mode, the first signal path is coupled to the external receiver, and the second signal path is coupled to the external transmitter, and when the component is further configurable to operate in a second mode in which, the first signal path is coupled to the second signal path; the first receiver is operable to evaluate the first signal for compliance with the predetermined transmitter specification parameters; and the first transmitter is operable to evaluate the second signal for compliance with the predetermined receiver specification parameters.

16. The component of claim 15, wherein the component is configured to operate at high frequencies.

17. The component of claim 16, wherein the semiconductor device is configured to operate at a frequency of at least 1 Gigahertz.

18. The component of claim 16, wherein the semiconductor device is configured to operate at a frequency of at least 3 Gigahertz.

19. The component of claim 15, wherein the predetermined transmitter specifications of the first transmitter and the predetermined receiver specification parameters of the first receiver must be met for the first transmitter and the first receiver to be suitable for operation in the first mode, and wherein evaluation comprises determining that the first transmitter and the first receiver operate properly when the respective predetermined specification parameters are met.

20. The component of claim 15, wherein the predetermined transmitter specification parameters of the first transmitter and the predetermined receiver specification parameters of the first receiver must be met for the first transmitter and the first receiver to be suitable for operation in the first mode, and wherein evaluation comprises: determining an amount of margin present between operating characteristics of the first transmitter and the predetermined transmitter specification parameters being evaluated; and determining an amount of margin present between operating characteristics of the first receiver and the predetermined receiver specification parameters being evaluated.

21. The component of claim 15, wherein, in the second mode, the first transmitter and the first receiver are in different interface blocks in the component and are each configurable to be coupled via an external interconnect.

22. The component of claim 15, wherein, in the second mode, the first transmitter and the first receiver are in a same interface block in the component and are coupled via an internal interconnect.

23. The component of claim 15, further comprising a first timing circuit that receives a first external timing signal and produces a first internal timing signal.

24. The component of claim 23, wherein the first internal timing signal is coupled to the first transmitter, and an internal timing event on the first internal timing signal causes the first transmitter to drive a first symbol on the first signal.

25. The component of claim 23, wherein the first internal timing signal is coupled to the first receiver, and an internal timing event on the first internal timing signal causes the first receiver to sample a first symbol on the second signal.

26. The component of claim 23, wherein the first timing circuit aligns an internal timing event on the internal timing signal with an external timing event on the external timing signal.

27. The component of claim 23, wherein the first timing circuit creates at least two internal timing events on the first internal timing signal, that are each associated with an external timing event on the external timing signal.

28. The component of claim 23, wherein the first timing circuit creates an internal timing event on the internal timing signal, wherein the internal timing event has a fixed time offset relative to an external timing event on an associated external timing signal.

29. The component of claim 23, wherein the first timing circuit creates an internal timing event on the internal timing signal, wherein the internal timing event has an adjustable time offset relative to an external timing event on the associated external timing signal.

30. The component of claim 29, wherein the adjustable time offset is specified by a value held in a register in the component.

31. The component of claim 29, wherein evaluation of the respective predetermined specification parameters of the receiver and the transmitter includes accessing a value that determines the adjustable time offset.

32. The component of claim 23, wherein evaluation of the respective predetermined specification parameters of the receiver and the transmitter includes measuring a position of an external timing event on the first external timing signal.

33. The component of claim 15, further comprising: a first timing circuit that receives a first external timing signal and produces a first internal timing signal; and a second timing circuit that receives the second external timing signal and produces a second internal timing signal, such that the first internal timing signal is coupled to the first transmitter, and the second internal timing signal is coupled to the first receiver, so that a first timing event on the first internal timing signal causes the first transmitter to drive a first symbol on the first signal and a second timing event on the second internal timing signal causes the first receiver to sample a second symbol on the second signal.

34. The component of claim 33, wherein evaluation of the specification parameters of the receiver and the transmitter comprises: measuring a position of a first external timing event on the first external timing signal; and measuring a position of a second external timing event on the second external timing signal, wherein the first external timing event is associated with the first internal timing event and the second external timing event is associated with the second internal timing event.

35. The component of claim 34, wherein the first external timing event is aligned with the first internal timing event and the second external timing event is aligned with the second internal timing event.

36. The component of claim 15, further comprising: a first timing circuit that receives a first external timing signal and produces a first internal timing signal; and a second timing circuit that receives the first external timing signal and produces a second internal timing signal, such that the first internal timing signal is coupled to the first transmitter, and the second internal timing signal is coupled to the first receiver, so that a first timing event on the first internal timing signal causes the first transmitter to drive a first symbol on the first signal and a second timing event on the second internal timing signal causes the first receiver to sample a second symbol on the second signal.

37. The component of claim 36, wherein: the first timing circuit creates a first internal timing event on the first internal timing signal; the first internal timing event has a first adjustable time offset relative to a first external timing event on the associated external timing signal; wherein the second timing circuit creates a second internal timing event on the second internal timing signal; and wherein the second internal timing event has a second adjustable time offset relative to a second external timing event on the associated external timing signal.

38. The component of claim 37, wherein the first adjustable time offset is specified by a first value held in a first register in the component and the second adjustable time offset is specified by a second value held in a second register in the component.

39. The component of claim 37, wherein evaluation of the respective predetermined specification parameters of the receiver and the transmitter includes accessing a first value that determines the first adjustable time offset and includes accessing a second value that determines the second adjustable time offset.

40. The component of claim 15, wherein a voltage discriminator circuit is coupled to one of the first signal and the second signal, and measures a voltage level of one of the first signal and the second signal in the course of evaluating the respective predetermined transmitter and receiver specification parameters.

41. The component of claim 40, wherein a voltage reference signal is coupled to the voltage discriminator circuit to provide a voltage comparison standard for measuring a voltage level on one of the first signal and the second signal.

42. The component of claim 41, wherein measuring includes at least one comparison of a voltage level of one of the first signal and the second signal and a voltage reference signal

43. The component of claim 41, wherein the voltage discriminator circuit is a differential comparator with one input coupled to one of the first signal and the second signal and another input coupled to the voltage reference signal.

44. The component of claim 41, wherein the voltage reference signal is configurable to be generated outside the component.

45. The component of claim 41, wherein the voltage reference signal is generated inside the component by a voltage reference generator circuit, and wherein the voltage reference generator circuit is coupled to a register containing a value that adjusts a voltage level of the voltage reference signal.

46. The component of claim 15, wherein the receiver includes a voltage discriminator circuit and measures a voltage level of the second signal in the course of evaluating the respective predetermined transmitter and receiver specification parameters.

47. The component of claim 46, wherein a voltage reference signal is coupled to the voltage discriminator circuit to provide a voltage comparison standard for measuring a voltage level on the second signal.

48. The component of claim 47, wherein measuring includes at least one comparison of a voltage level of the second signal and the voltage reference signal.

49. The component of claim 47, wherein the voltage discriminator circuit is a differential comparator with one input coupled to the second signal and another input coupled to the voltage reference signal.

50. The component of claim 47, wherein the voltage reference signal is configurable to be generated outside the component.

51. The component of claim 47, wherein the voltage reference signal is generated inside the component by a voltage reference generator circuit, wherein the voltage reference generator circuit is coupled to a register containing a value that adjusts a voltage level of the voltage reference signal.

52. The component of claim 15, wherein a timing discriminator circuit couples a third signal to one of the first signal and the second signal, wherein the third signal is further coupled to a third receiver on the component, wherein the third receiver being similar to the first receiver, and wherein the time discriminator circuit is used to evaluate the respective predetermined specification parameters of the first transmitter and of the first receiver.

53. The component of claim 52, wherein a timing reference signal is coupled to the timing discriminator circuit, and wherein the timing reference signal is configurable to be generated outside the component.

54. The component of claim 53, wherein a timing event on the timing reference signal causes the third signal to assume a same value as the one of the first signal and second signal.

55. The component of claim 53, wherein a timing event on the timing reference signal causes the third signal to become independent of the one of the first signal and second signal, and to retain a value as of the timing event.

56. The component of claim 53, wherein the timing discriminator circuit includes an MOS pass transistor coupling the one of the first signal and second signal and the third signal, wherein the timing reference signal is coupled to the gate of the MOS pass transistor, and wherein a capacitor is coupled between the third signal and a fixed voltage reference.

57. The component of claim 53, wherein the timing reference signal is coupled directly from an external source to the timing discriminator circuit with an internal interconnect.

58. The component of claim 52, wherein a timing reference signal is coupled to the timing discriminator circuit and is generated inside the component by a timing reference generator circuit, to which is coupled a register containing a value which adjusts the timing offset of a timing event on the timing reference signal.

59. The component of claim 15, wherein a first timing discriminator circuit couples a third signal to the second signal, and a second timing discriminator circuit couples the third signal to a fourth signal, wherein the fourth signal is coupled to a third receiver on the component, the third receiver being similar to the first receiver, wherein the first and second time discriminator circuits are used to evaluate the respective predetermined specification parameters of the first transmitter and of the first receiver.

60. The component of claim 15, wherein the first receiver consists of a first timing discriminator circuit coupled to one of a voltage discriminator circuit and a second timing discriminator circuit, such that the in the first mode of operation the first timing discriminator couples the second signal to the one of a voltage discriminator circuit and a second timing discriminator circuit, and in the second mode of operation, the first time discriminator circuit is used to evaluate the respective predetermined specification parameters of the first transmitter and of the first receiver.

61. The component of claim 60, wherein a timing reference signal is coupled to the first timing discriminator circuit and is configurable to be generated outside the component, and wherein the timing reference signal is coupled directly from an external source to the timing discriminator circuit with an internal interconnect.

62. The component of claim 15, further comprising a current control circuit coupled to the transmitter, wherein the current control circuit determines a current passing through the first transmitter to determine a voltage level driven on the first signal in the first mode and in the second mode.

63. The component of claim 62, further comprising a current reference signal coupled to the current control circuit to provide a current comparison standard for determining a current passing through the first transmitter.

64. The component of claim 63, wherein the current control circuit and the first transmitter each include a plurality of transistor elements whose conductive strengths form a binary sequence.

65. The component of claim 63, wherein the current reference signal is configurable to be generated outside the component.

66. The component of claim 63, further comprising: a current reference generator circuit that generates the current reference signal inside the component; and a register coupled to the reference generator circuit, wherein the register stores a value that adjusts a value of the current reference signal.

67. The component of claim 63, wherein the current reference signal is varied between at least two values during evaluation of the transmitter and receiver specification parameters in the second mode.

68. The component of claim 15, further comprising: a termination control circuit; a termination element coupled to the termination control circuit and to one of the first signal and the second signal, wherein the termination control circuit determines a value of a termination load present on one of the first signal and the second signal in the second mode, and in the first mode.

69. The component of claim 68, further comprising a termination reference signal coupled to the termination control circuit to provide a termination comparison standard for determining a value of a termination load present on one of the first signal and the second signal.

70. The component of claim 69, wherein the termination control circuit and the termination element each include a plurality of transistor elements whose conductive strengths form a binary sequence.

71. The component of claim 69, wherein the termination reference signal is configurable to be generated outside the component.

72. The component of claim 69, further comprising: a termination reference generator circuit that generates the termination reference signal inside the component; and a register coupled to the termination generator circuit, wherein the register stores a value that adjusts a value of the termination reference signal.

73. The component of claim 69, wherein the termination reference signal is varied between at least two values in the second mode.

74. The component of claim 73, wherein the termination voltage signal is varied between at least two values in the second mode.

75. The component of claim 15, further comprising a termination element coupled to a termination voltage signal, and further coupled to one of the first signal and the second signal, wherein the termination element determines voltage levels present on one of the first signal and the second signal in the second mode and in the first mode.

76. The component of claim 75, wherein the termination voltage signal is configurable to be generated outside the component.

77. The component of claim 75, further comprising: a termination voltage generator circuit that generates the termination voltage signal inside the component; and a register coupled to the termination voltage generator circuit, wherein the register stores a value that adjusts a value of the termination voltage signal.

78. The component of claim 15, further comprising at least one pattern generator circuit, wherein pattern data from the at least one pattern generator circuit is coupled to the first transmitter to be driven as transmitter pattern data on the first signal, and to be sampled by the receiver as received pattern data on the second signal.

79. The component of claim 15, further comprising at least one pattern comparison circuit that compares the received pattern data to the transmitted pattern data.

80. The component of claim 15, wherein at least one of the first signal and the second signal are encoded using two differential voltage values.

81. The component of claim 15, wherein at least one of the first signal and the second signal are encoded using single-ended voltage values.

82. The component of claim 15, wherein at least one of the first signal and the second signal are encoded using single-ended voltage values with reference to an external reference voltage value.

83. The component of claim 15, wherein at least one of the first signal and the second signal are each bidirectional.

84. The component of claim 15, wherein at least one of the first signal and the second signal are each unidirectional.

85. The component of claim 15, wherein the first transmitter includes at least one unipolar driver.

86. The component of claim 15, wherein the first transmitter includes at least one bipolar driver.

87. The component of claim 15, wherein the first transmitter uses an external reference value to generate signal values.

88. The component of claim 15, further comprising at least one calibration circuit, wherein the first transmitter uses an external reference value and the at least one calibration circuit to generate signal values.

89. The component of claim 88, wherein the calibration circuitry is adjustable.

90. The component of claim 89, wherein the calibration circuitry is adjustable using a value in a register of the component.

91. The component of claim 15, wherein at least one of the first signal and the second signal is coupleable to an interconnect that couples the component to one other component.

92. The component of claim 15, wherein at least one of the first signal and the second signal is coupleable to an interconnect that couples the component to at least two other components.

93. The component of claim 15, wherein at least one of the first signal and the second signal use current-mode operation.

94. The component of claim 15, wherein at least one of the first signal and the second signal use voltage-mode operation.

95. The component of claim 15, further comprising at least one slew rate control circuit coupled to control respective slew rates of at least one of the first signal and the second signal.

96. The component of claim 15, wherein at least one of the first signal and the second signal is coupled to respective external termination loads.

97. The component of claim 15, wherein at least one of the first signal and the second signal is coupled to respective internal termination loads.

98. The component of claim 97, wherein at least one of the internal termination loads is calibrated to an external reference value.

99. The component of claim 98, wherein at least one of the internal termination loads is adjustable.

100. The component of claim 99, wherein at least one of the internal termination loads is adjusted using a value in an internal register.

101. An electronic system comprising: at least one semiconductor component configurable to perform testing functions, wherein the at least one semiconductor component has at least two operational modes comprising a normal mode and a test mode, the at least one semiconductor component comprising, a transmitter; a receiver; and a test circuit, wherein in the test mode the transmitter is configurable to test the receiver and the receiver is configured to test the transmitter.

102. The system of claim 101, wherein in at least one semiconductor component is a component configured to operate at high frequencies.

103. The system of claim 102, wherein the semiconductor component is configured to operate at a frequency of at least 1 Gigahertz.

104. The system of claim 102, wherein the semiconductor component is configured to operate at a frequency of at least 3 Gigahertz.

105. The system of claim 101, wherein in the test mode, the transmitter and the receiver are on a same semiconductor component.

106. The system of claim 101, wherein in the test mode, the transmitter and the receiver are on different interfaces of a same semiconductor component.

107. The system of claim 101, wherein in the test mode, the transmitter and the receiver are on different semiconductor components.

108. The system of claim 101, wherein the at least one semiconductor component comprises a memory interface on a memory component and a memory controller interface on a memory controller component, and wherein the memory component and the memory controller component are coupled via an interconnect in the test mode and in the normal mode.

109. The system of claim 108, wherein the interconnect is a high frequency interconnect.

110. The system of claim 108, wherein the interconnect is configured to operate at a frequency of at least 1 Gigahertz.

111. The system of claim 108, wherein the interconnect is configured to operate at a frequency of at least 3 Gigahertz.

112. The system of claim 101, wherein the at least one semiconductor component is coupled to a plurality of reference signals, including a voltage reference signal, V_REF, a receiver clock reference signal, CLK_RREF, a transmitter clock reference signal CLK_TREF, and a current reference signal, I_REF, and wherein the reference signals are scanned in the test mode, wherein scanning comprises sweeping a value of a reference signal to determine an event on another signal.

113. The system of claim 112, wherein a differential comparator receives the V_REF signal and compares the V_REF signal to a signal voltage on the interconnect as the V_REF signal is scanned to produce a test output signal.

114. The system of claim 112, wherein the plurality of reference signals further comprise a time reference signal, T_REF, and wherein the test circuit further comprises an analog sampling circuit controlled by the T_REF signal so as to control sampling times of a signal voltage on the interconnect in the test mode independent of individual interface parameters, wherein the analog sampling circuit produces a time test voltage signal.

115. The system of claim 114, wherein the test circuit further comprises: a test pattern circuit; a register that holds the test output signal and the time test voltage signal; and a selection circuit coupled to the test pattern circuit, that selects a value from the register to be compared to a test pattern.

116. The system of claim 112, wherein the plurality of reference signals further comprise a test current reference signal I_TL-REF that controls a test current generated to allow a pin of one of the at least one semiconductor components to test itself.

117. An electronic system comprising: at least one semiconductor component configurable to perform testing functions, wherein the at least one semiconductor component has at least two operational modes comprising a normal mode and a test mode, the at least one semiconductor component comprising, a transmitter; a receiver; and a test circuit, wherein in the test mode the transmitter is configurable to test the receiver or the receiver is configured to test the transmitter.

118. A method for a semiconductor component to be tested by another semiconductor component, the method comprising: generating a test pattern; storing the test pattern in the semiconductor component; providing a reference signal to the semiconductor component; generating an operational signal by processing a data signal in the semiconductor component; scanning the reference signal; comparing the operational signal to the reference signal, while scanning the reference signal; and comparing a result of the comparison with the test pattern.

119. The method of claim 118, wherein at least one of the semiconductor component and the other semiconductor component is configured for operation at high frequencies.

120. The method of claim 119, wherein at least one of the semiconductor component and the other semiconductor component is configured for operation at a frequency of at least 1 Gigahertz.

121. The method of claim 119, wherein at least one of the semiconductor component and the other semiconductor component is configured for operation at a frequency of at least 3 Gigahertz.

122. The method of claim 118, wherein the method is performed by the semiconductor component on the other semiconductor component, and wherein the semiconductor component and the other semiconductor component are on at least one semiconductor wafer.

123. The method of claim 122, wherein the semiconductor component and the other semiconductor component comprise a transmitter and a receiver, and wherein the plurality of signals further comprises a time reference signal that decouples semiconductor component transmitter timing parameters from semiconductor component receiver timing parameter, the method further comprising scanning the time reference signal to define a output eye region for the transmitter, including: creating a series of timing events, including an active clock edge that causes the transmitter to output data; determining a time after an active clock edge when the output data becomes valid; and determining a time after an active clock edge when the output data becomes invalid.

124. The method of claim 123, further comprising using the time reference signal to control an analog sampler that samples the output data and creates a time offset between when the output data becomes valid and when the output data is sampled as input data by the receiver.

125. The method of claim 124, further comprising: setting the time offset using the time reference signal such that an input eye region of the receiver occurs within the output eye region defined for the transmitter; and scanning a receiver clock signal to determine whether a setup time specification and a hold time specification for the receiver are met.

126. The method of claim 118, wherein the method is performed by the semiconductor component on the other semiconductor component, and wherein the semiconductor component and the other semiconductor component are in at least one component package.

127. The method of claim 126, wherein the method is performed on the high-speed receiver circuit, the method comprising: scanning a voltage reference signal; and comparing the scanned voltage reference signal with a normal operational signal of the receiver to determine a high input voltage and a low input voltage.

128. The method of claim 127, further comprising scanning a transmitter clock reference signal to determine whether a setup time specification and a hold time specification for the transmitter are met.

129. The method of claim 118, wherein the semiconductor component and the other semiconductor component comprises a high frequency transmitter circuit and a high frequency receiver circuit.

130. The method of claim 129, wherein the high frequency transmitter circuit and the high frequency receiver circuit operate at a frequency of at least 1 Gigahertz.

131. The method of claim 129, wherein the high frequency transmitter circuit and the high frequency receiver circuit operate at a frequency of at least 3 Gigahertz.

132. The method of claim 129, wherein the method is performed on the high-speed transmitter circuit, the method further comprising: scanning a voltage reference signal and; comparing the scanned voltage reference signal with a normal operational signal of the transmitter to determine a high output voltage and a low output voltage.

133. The method of claim 132, further comprising scanning a receiver clock reference signal to determine whether a setup time specification and a hold time specification for the receiver are met.

134. A method for using one component to test and characterize another component, comprising: receiving at least one first signal having a first frequency; receiving a plurality of second reference signals having a plurality of second frequencies, wherein at least one of the second frequencies is lower than the first frequency; generating and storing a test pattern; scanning one of the second reference signals; comparing an operational signal to one of the second reference signals, while scanning one of the reference signals, wherein the operational single comprises a data signal processed by a circuit during operation; and comparing a result of the comparison with the test pattern.

135. A semiconductor circuit component comprising: a transmit interface comprising, a first transmitter; and transmitter test circuitry; and a receive interface comprising, a first receiver: and receiver test circuitry, wherein the first transmitter drives a first signal according to predetermined transmitter specifications, the first receiver samples a second signal according to predetermined receiver specifications, and wherein the component is configurable to operate in a test mode in which, the first signal is coupled to the second signal such that the first receiver evaluates transmitter specification parameters of the first transmitter; and the first signal is coupled to the second signal such that the first transmitter evaluates receiver specification parameters of the first receiver.

136. The component of claim 135, wherein the receive interface and the transmit interface are each configured to transfer data at rates equal to or greater than 3 GHz.

137. The component of claim 135, wherein the transmitter test circuitry comprises a first pattern source element, and wherein a first pattern set transmitted from the first pattern source element to the first transmitter, and is driven by the first transmitter onto the first signal during operation in the test mode.

138. The component of claim 137, wherein the transmitter test circuitry further comprises a first pattern storage element coupled to the first pattern source element, wherein the first pattern storage element stores the first pattern set as the first pattern set is generated.

139. The component of claim 137 in which the first pattern set is generated by circuitry in the first pattern source element.

140. The component of claim 137 in which the first pattern set is generated by circuitry external to the component and communicated to the first pattern source element.

141. The component of claim 137 in which the first pattern set is generated when the first pattern source element is controlled by at least one first external sideband signal whose transfer rate is lower than that of the first signal.

142. The component of claim 137, wherein the receiver test circuitry comprises: a delay element coupled to the first pattern source element; and a compare element coupled to the delay element, wherein the first receiver samples a second pattern set on the second signal, the first pattern set is delayed by the first delay element to form a third pattern set, and wherein the compare element is compares the first pattern set to the third pattern set.

143. The component of claim 137, wherein the transmitter test circuitry further comprises a memory array coupled to the first pattern source element, wherein the first pattern set is stored in the memory array.

144. The component of claim 143, wherein at least one pattern set is written from the first pattern source element to the memory array.

145. The component of claim 143, wherein at least one pattern set is read from the memory array to the first transmitter and driven onto the first signal during operation in the test mode.

146. The component of claim 143, wherein the receiver test circuitry further comprises: a delay element coupled to the memory array; and a compare element coupled to the delay element, wherein the first receiver samples a second pattern set on the second signal such that the first pattern set is delayed by the delay element to form a third pattern set, and wherein the compare element compares the first pattern set to the third pattern set.

147. The component of claim 135, further comprising a first pattern source element, wherein the first receiver samples a first pattern set on the second signal, and a second pattern set is provided by the first pattern source element during operation in the test mode.

148. The component of claim 147, wherein the first pattern source element includes a first pattern storage element used to accumulate the first pattern set as the first pattern is generated.

149. The component of claim 147, wherein the first pattern set is generated by circuitry in the pattern source element.

150. The component of claim 147, wherein the first pattern set is generated by circuitry external to the component and is communicated to the pattern source element.

151. The component of claim 147, wherein the first pattern set is generated when the pattern source element is controlled by at least one first external sideband signal whose transfer rate is lower than that of the second signal.

152. The component of claim 147, further comprising a compare element coupled to the first receiver and the first pattern source element, wherein the compare element compares the first pattern set to the second pattern set.

153. The component of claim 147, further comprising a memory array coupled to the first pattern source element, wherein the second pattern set resides in the memory array.

154. The component of claim 153, wherein at least one pattern set is written from the first pattern source element to the memory array.

155. The component of claim 153, wherein at least one pattern set is read from the memory array.

156. The component of claim 153, further comprising a compare element coupled to the first receiver and the memory array, wherein the compare element compares the first pattern set to the second pattern set.

157. An electronic system comprising: a first component comprising a first transmitter configured to drive a first signal onto a first external interconnect according to a set of transmitter specification parameters; and a second component comprising a first receiver configured to sample the first signal from the first external interconnect according a set of receiver specification parameters, wherein, the first component and the second component are configurable to operate in a normal mode in which the first signal is configurable to be driven by the first component and sampled by the first receiver; the first component and the second component are further configurable to operate in a first test mode in which the first receiver evaluates the transmitter specification parameters of the first transmitter; and the first component and the second component are further configurable to operate in a second test mode in which first transmitter evaluates the receiver specification parameters of the first receiver.

158. The system of claim 157, wherein the first component and the second component are each semiconductor components configured to operate at frequencies of 1 GHz or greater.

159. The system of claim 157, wherein the first component and the second component are each semiconductor components configured to operate at frequencies of 3 GHz or greater.

160. The system of claim 157, wherein system evaluation of the first component is performed in the first test mode.

161. The system of claim 157, wherein system evaluation of the second component is performed in the second test mode.

162. The system of claim 157, wherein the first component further comprises a second receiver coupled with a second interconnect to the first transmitter, wherein the first component is further configurable to operate in a third test mode in which the second receiver evaluates the transmitter specification parameters of the first transmitter.

163. The system of claim 162, wherein the second interconnect is an internal interconnect of the first component.

164. The system of claim 162, wherein the second interconnect is an interconnect external to the first component.

165. The system of claim 162, wherein wafer evaluation of the first component is performed in the third test mode.

166. The system of claim 162, wherein package evaluation of the first component is performed in the third test mode.

167. The system of claim 157, wherein the second component further comprises a second transmitter coupled with a second interconnect to the first receiver, wherein the second component is further configurable to operate in a third test mode in which the second transmitter evaluates the receiver specification parameters of the first receiver.

168. The system of claim 167, the second interconnect is an internal interconnect of the second component.

169. The system of claim 167, wherein the second interconnect is external to the second component.

170. The system of claim 167, wherein wafer evaluation of the second component is performed in the third test mode.

171. The system of claim 167, wherein package evaluation of the second component is performed in the third test mode.

172. The system of claim 157, further comprising at least one third component coupled to the external interconnect, wherein the first component is further configurable to operate in a third test mode in which the first transmitter is coupled with a second external interconnect to a second receiver on the third component, so that the second receiver evaluates the transmitter specification parameters of the first transmitter.

173. The system of claim 172, wherein wafer evaluation of the first component is performed in the third test mode.

174. The system of claim 172, wherein package evaluation of the first component is performed in the third test mode.

175. The system of claim 172, wherein the third component is substantially the same as the first component.

176. The system of claim 157, further comprising at least one third component coupled to the external interconnect, wherein the second component is further configurable to operate in a third test mode in which the first receiver is coupled with a second external interconnect to a second transmitter on the third component, so that the second transmitter evaluates the receiver specification parameters of the first receiver.

177. The system of claim 176, wherein wafer evaluation of the second component is performed in the third test mode.

178. The system of claim 176, wherein package evaluation of the second component is performed in the third test mode.

179. The system of claim of claim 176, wherein the third component is substantially similar to the second component.

180. A device, comprising: a test circuit; a first element, coupled to the test circuit, including a transmitter; a second element, coupled to the first element and the test circuit, including a receiver; and means for testing the first element using the second element and the test circuit.

181. A device, comprising: a test circuit; a first element, coupled to the test circuit, including a transmitter; a second element, coupled to the first element and the test circuit, including a receiver; and means for testing the second element using the first element and the test circuit.

PRIORITY CLAIM

[0001] The present application claims priority to U.S. Provisional Patent Application Serial No. 60/450,007, entitled, “METHOD AND APPARATUS FOR TEST AND CHARACTERIZATION OF SEMICONDUCTOR COMPONENTS”, which application was filed on Feb. 26, 2003.

FIELD OF THE INVENTION

[0002] The present invention relates to testing and characterization of electronic circuits implemented in semiconductor components.

BACKGROUND OF INVENTION

[0003] Modern semiconductor circuit components are manufactured by first placing electronic circuit components on semiconductor wafers and then packaging different circuits into circuit component packages. Packages include semiconductor “chips” that are placed in systems with many other chips to create a product such as a personal computer or a network router. At various stages in the manufacturing process, it is important to verify that the components function properly and meet specifications. Testing a component includes, for example, sending a pattern of bits to a component and verifying that the component receives and interprets the pattern correctly. Testing can also include component characterization, which establishes or verifies a set of operating parameters for the component. For example, for a component that performs a binary signaling protocol, it is necessary to guarantee that the component will interpret voltages in certain ranges as ones or zeroes. Typically, components are tested with a specialized piece of equipment called a test system or tester.

[0004] Recent improvements in the ability of components to produce a greater range of signaling bandwidths and to operate at higher frequencies have increased the cost and difficulty of testing and characterizing components. In order to test and characterize components, a test system must operate at a frequency at least as high as the operating frequency of the component under test. The test system requires some tester guard band, which is a margin around the tested values required to guarantee the tested values. In the past, it was relatively easy to produce test systems that were faster than the tested components. That is not the case now, as even mass-produced metal oxide semiconductor (“MOS”) components achieve ever greater speeds. High-speed test systems that are capable of exceeding the speeds of the fastest components today are very expensive. As component designers produce faster and faster component designs, it becomes more problematic for potential manufacturers to produce the designs because of the required investment in faster test systems.

[0005] FIG. 1 is a block diagram of a prior art high-speed interface 100 of a component A. The high-speed interface 100 is coupled to an interconnect 108 , which is an electrical conductor or conductors. The high-speed interface 100 includes a receiver block 104 , a transmitter block 102 , and a termination block 106 . The receiver 104 includes a voltage discriminator element 132 , a register element 130 , and a receive clock aligner element 128 . The voltage discriminator element 132 is a differential comparator that compares the V _P (high logic value) and V _N (low logic value) voltages values on interconnect 108 to determine what symbol is present (e.g., a “1” or a “0”). The register element 130 is a time discriminator that samples the output of the voltage discriminator element 132 on the rising edge of the CLKRA signal (the receive clock signal of component A), stores it, and drives it as the RA signal (receive signal of component A), to be used by other circuits on the component A. The receive clock aligner element 128 creates the CLKRA signal from the CLKRREF (receive clock reference) reference signal. The receive clock aligner element 128 is typically a phase locked loop (“PLL”) or a delay locked loop (“DLL”) circuit.

[0006] The termination block 106 includes two load devices 134 a and 134 b , coupled to interconnect 108 with one terminal and to the V _T supply with the other terminal. A terminal of load device 134 a is coupled to a first signal line, in interconnect 108 , that provides a V _P voltage value and a terminal of load device 134 b is coupled to a second signal line, in interconnect 108 , that provides a V _N voltage value. The termination block 106 further includes a control element 136 , which adjusts the resistive value R _T of the load devices 134 to match an external reference resistance, RREF.

[0007] The transmitter block 102 includes a predriver element 118 , two differential driver elements 120 and 122 , two current source elements 124 and 126 , a current control element 114 , a register element 116 , and a transmit clock aligner element 112 . The register element 116 is a time drive element that samples the TA signal (transmit signal from other circuits on component A) and drives it on the rising edge of the CLKTA signal. The transmit clock aligner element 112 creates the CLKTA signal from the CLKTREF reference signal. The transmit clock aligner element 112 is typically a phase locked loop (“PLL”) or a delay locked loop (“DLL”) circuit. The output of the register element 116 connects to the predriver element 118 , which connects to the differential driver elements 120 and 122 . Each driver element 120 and 122 is an open drain transistor, and is connected in series with one of the current source elements 124 and 126 , respectively. The current control element 114 maintains a sink current of I _OL (output low current) in the current source elements using an external reference value IREF. When the transmitter 102 drives a bit, one of the two driver elements 120 and 122 is on, and the other is off.

[0008] In an alternate embodiment, the two current source elements 124 and 126 could be merged into a single current source element, with one terminal connecting to the low supply voltage (ground) and the other terminal connecting to the source terminals of the two driver elements 120 and 122 . This will be equivalent to the circuit shown in transmitter block 102 since only one of the two driver elements 120 and 122 may be on at any time.

[0009] FIG. 2 shows a prior art test system 202 used to characterize and test the transmitter 102 and the receiver 104 of component A. Typically, component A will be mounted on a load board 222 , which is a printed circuit board. The testing system 202 and the load board 222 approximately duplicate the environment seen by component A during normal operation. The load board 222 has an interconnect 212 that couples the interface 100 of the component A to the high-speed pin electronics 204 of test system 202 . The interconnect 212 has a characteristic impedance ZO which may be the same as, or different from, that of the manufactured system interconnect 108 . The interconnect 108 is terminated on one end by termination 214 in high-speed pin electronics 204 , and on the other end by termination 106 . The high-speed pin electronics 204 include timing circuitry 206 to adjust the drive point and the sample point of signals. The high-speed pin electronics 204 further include voltage/current force/sense circuitry 208 to force and sense voltage values and to force and sense current values. The high-speed pin electronics 204 also include pattern generation circuitry 210 for storing, generating, and comparing test patterns. Typically, the accuracy and resolution of circuitry 206 , circuitry 208 and circuitry 210 are very high in order to minimize the uncertainty due to measurement error. As a result, the cost of pin electronic 204 is also very high. This is particularly true in the case in which the component A has high-speed signals, each requiring its own set of pin electronics. The test system 202 must simultaneously provide a high signaling rate, precise timing control, and precise voltage/current control for each signal to be tested.

[0010] The test system 202 further includes circuitry that generates reference signals 110 used by component A. The reference signals 110 include IREF, RREF, CLKRREF, and CLKTREF. These reference signals are typically shared across the entire component A. These reference signals 110 often do not need the simultaneous combination of high-speed, voltage/current accuracy and timing accuracy. Therefore, the circuitry necessary to produce the reference signals is relatively easier and cheaper to produce compared to the high-speed pin electronics 204 . For example, the RREF signal will typically shift through a small set of discrete values during testing. The IREF signal will typically shift through some range of direct current (“DC”) values during testing. The CLKRREF and CLKTREF signals provide a frequency and phase reference for the component A. The clock frequency will typically shift through a small set of discrete values during testing. The clock phase will typically shift through some range of values during testing. Typically, a component will utilize frequency multiplication, so that the required signaling rate of the CLKRREF and CLKTREF signals is much lower than the signaling rate of the high-speed signals.

[0011] Another disadvantage of prior art test systems, such as the high-speed test system 202 , is that they cannot be used at every stage of the manufacturing process. The result is more defective components being passed to later stages of the manufacturing process. In a typical manufacturing process, there are at least three possible testing stages: 1) component wafer testing; 2) component package testing; and 3) in-system testing. Component wafer testing determines which components are acceptable to be packaged. Component package testing determines which components are acceptable to be used in a system. In-system testing determines which systems work properly. Usually, components are tested twice, once at the wafer level before packaging, and again after packaging. High-speed testing, however, is only performed after packaging when packages can be placed on a load board such as load board 222 . All high-speed testing must be performed with a high-speed test system, such as high-speed test system 202 . Typically a high-speed test system performs the most exhaustive testing during the component package test. It is usually not possible to perform component wafer testing at full speed. The final in-system test can be performed at full speed, but must use nominal parameter values because of the difficulty of probing high-speed interconnects within an operating system.

[0012] There is a need for a method and apparatus for testing and characterizing high-speed components that does not require an expensive high-speed test system. There is also a need for a method and apparatus for providing more uniform testing at each stage of the manufacturing process.

BRIEF DESCRIPTION OF THE DRAWING

[0013] The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which:

[0014] FIG. 1 is a block diagram of a prior art high-speed interface;

[0015] FIG. 2 is a block diagram of a prior art high-speed test system;

[0016] FIG. 3 is a block diagram of an embodiment of a high-speed component interface;

[0017] FIGS. 4 A-B are block diagrams of portions of two components configured to test each other according to one embodiment;

[0018] FIG. 5 is a timing diagram illustrating a transmitter testing operation using the embodiment of FIGS. 4 A-B;

[0019] FIGS. 6 A-B are block diagrams of portions of two components configured to test each other according to one embodiment;

[0020] FIG. 7 is a timing diagram illustrating a receiver testing operation using the embodiment of FIG. 6 ;

[0021] FIGS. 8 A-B are block diagrams of portions of two components configured to test each other with parameters of respective components being uncoupled according to one embodiment;

[0022] FIG. 9 is a timing diagram illustrating a transmitter testing operation using the embodiment of FIG. 8 ;

[0023] FIG. 10 is a timing diagram illustrating a receiver testing operation using the embodiment of FIG. 8 ;

[0024] FIG. 11 is a block diagram of an embodiment with bipolar drivers;

[0025] FIG. 12 is a block diagram of an embodiment with single-ended signals;

[0026] FIG. 13 is a block diagram of an embodiment of I _OL current control;

[0027] FIG. 14 is a block diagram of an embodiment of I _OL current control;

[0028] FIG. 15 is a block diagram of an embodiment of V _OL voltage control;

[0029] FIG. 16 is a block diagram of an embodiment of R _T termination load control;

[0030] FIG. 17 is a block diagram of an embodiment of I _OL current control;

[0031] FIG. 18 is a block diagram of an embodiment of clock aligner circuit;

[0032] FIG. 19 is a block diagram of an embodiment of clock aligner circuit;

[0033] FIG. 20 is a block diagram of an embodiment of a transmit clock aligner circuit;

[0034] FIG. 21 is a block diagram of an embodiment of a high-speed interface with a slew rate control circuit;

[0035] FIG. 22 is a block diagram of an embodiment of a high-speed interface with a test current source;

[0036] FIG. 23A is a block diagram of an embodiment of a clock aligner circuit used for frequency multiplication;

[0037] FIG. 23B is a timing diagram that shows the clock signals from the embodiment of FIG. 23A for both a transmitter circuit and a receiver;

[0038] FIG. 24 is a block diagram of an embodiment of a high-speed interface with clock, current, and termination value adjustment circuitry FIG. 25 is a block diagram of an embodiment of a clock aligner circuit with a PLL and a DLL;

[0039] FIG. 26 is a block diagram of an embodiment of adjustable termination circuit;

[0040] FIG. 27 is a block diagram of an embodiment of adjustable current circuit;

[0041] FIG. 28 is a block diagram of an embodiment of a high-speed interface with a single external clock reference;

[0042] FIG. 29 is a block diagram of an embodiment with two high-speed interfaces communicating using unidirectional signaling;

[0043] FIGS. 30 A-B are block diagrams of an embodiment of a high-speed interface with an analog sampling circuit in a transmitter;

[0044] FIG. 31 is a block diagram of an embodiment of a coupled transmitter and receiver illustrating timing relationships;

[0045] FIG. 32 is a block diagram of an embodiment of a transmitter and receiver uncoupled by an analog sampling circuit, illustrating timing relationships; and

[0046] FIG. 33 is a block diagram of an embodiment of a transmitter and receiver uncoupled by two analog sampling circuits, illustrating timing relationships.

[0047] FIG. 34 is a block diagram of a transmit interface with pattern storage and a receive interface with pattern storage according to one embodiment;

[0048] FIG. 35A is a block diagram of a transmit interface, a receive interface, and interconnects according to one embodiment;

[0049] FIG. 35B is a block diagram of a transmit interface, a receive interface, and interconnects according to one embodiment;

[0050] FIG. 35C is a block diagram of a transmit interface, a receive interface, and an interconnect according to one embodiment;

[0051] FIG. 36 is a flow diagram of an embodiment of a pattern generation, storage and comparison process;

[0052] FIG. 37 is a block diagram of a transmit interface, a receive interface, and shared pattern generation and storage elements, according to one embodiment;

[0053] FIG. 38 is a block diagram of a transmit interface, a receive interface, and shared pattern generation and storage elements, according to one embodiment;

[0054] FIG. 39 is a flow diagram of an embodiment of a pattern generation, storage and comparison process;

[0055] FIG. 40 is a block diagram of a transmit interface, a receive interface, and dedicated pattern generation and storage elements, according to one embodiment;

[0056] FIGS. 41 A-C are flow diagrams of an embodiment of a pattern generation, storage and comparison process;

[0057] FIG. 42 is a block diagram of a transmit interface, a receive interface, and dedicated pattern generation and storage elements, according to one embodiment;

[0058] FIGS. 43 A-C are flow diagrams of an embodiment of a pattern generation, storage and comparison process;

[0059] FIG. 44 is a block diagram of a transmit interface, a receive interface, and dedicated pattern generation and storage elements, according to one embodiment;

[0060] FIGS. 45 A-D are flow diagrams of an embodiment of a pattern generation, storage and comparison process;

[0061] FIG. 46 is a block diagram of a transmit interface, a receive interface, and dedicated pattern generation and storage elements, according to one embodiment; and

[0062] FIGS. 47 A-C are flow diagrams of an embodiment of a pattern generation, storage and comparison process.

DETAILED DESCRIPTION

[0063] A method and apparatus is described for testing and characterizing semiconductor circuit components. A substantial part of the testing and characterization is performed by one component on itself or on another component. For example, a test system is not required to generate high accuracy and high-resolution signals for the test and characterization process. In one embodiment, a high-speed component interface includes additional circuitry to perform testing of the high-speed component. For example, the additional circuitry includes pattern generation, pattern memory, and comparison circuitry. A Rambus® XIO interface cell includes pattern storage and comparison logic. Also, a Rambus® ASIC cell (“RRAC”) interface includes pattern generation logic and pattern comparison logic. Various embodiments of component interface circuitry perform all normal testing and characterization on the interface itself, or on a similar interface, reducing the performance requirements of an external test system significantly. For example, an interface capable of very high data transfer rates, such as 3 GHz or greater normally requires a testing system with pin electronics capable of the same transfer rate. With the embodiments described, the external test system data transfer rates may be reduced by a factor of four or eight to 800 MHz or 400 MHz. This significantly reduces component testing costs. It also increases the number of test systems that are available for testing, since the highest speed testers have only limited availability. The embodiments also permit the same high-speed testing and characterization to be performed at each stage in the manufacturing process: at the wafer stage, at the package stage, and at the system stage. This further reduces manufacturing costs because components with out-of-specification interface parameters will be rejected at the earliest possible stage of manufacture.

[0064] The interface embodiment described may reside on one or multiple components. A component may test itself using test circuitry to be described below. Components may also test each other using test circuitry in their respective interfaces. Respective interfaces may be coupled through an interconnect for the specific purpose of testing one another. Alternatively, interfaces that are coupled to each other within a system for normal system operation, such as a memory component and a memory controller component, can test each other within the system through their usual system interconnect.

[0065] FIG. 3 is a block diagram of an embodiment of a high-speed component interface 300 . The high-speed interface 300 is part of a component A and includes circuitry that facilitates communication with the “outside world” external to the component A via high-speed digital signaling. In one embodiment, a system including the component A is built with discrete integrated circuit components. In one embodiment, the digital signal travels between the interface 300 and another interface external to the interface 300 using the interconnect 308 . In one embodiment, the digital signaling is differential signaling as known in the art, and the interconnect 308 is two conductive media. In other embodiments, other known signaling schemes, such as single-ended signaling, are used.

[0066] Information in the signal is carried as voltage values on the interconnect 308 . The voltage values are restricted to two voltage ranges, because there are two possible symbols (bits with logic values of “1” or “0”) in this example. A voltage value within a first voltage range on interconnect 308 represents a bit having a logical 1 value or high value; while, a different voltage value within a second voltage range represents a bit having a logical 0 value or low value. A bit is driven for a specific length of time called a bit interval. The characteristic impedance of each interconnect 308 is Z _O . In order to maximize the signaling rate of the system, a termination element, such as the termination elements 334 a and 334 b of termination block 306 , are present at each end of interconnect 308 . The resistive value R _T of the termination elements 334 a and 334 b is approximately the same as the real part of the characteristic impedance Z _O of the interconnect 308 . One end of each termination element 334 a and 334 b connects to an interconnect 308 , and the other connects to a power supply that sources a termination voltage of V _T volts.

[0067] The interface 300 includes a transmitter 302 and a receiver 304 . The high-speed signal is bidirectional. That is, information may travel from component A to another component B or from another component B to component A. In this example, the bit intervals of the component A transmitter may not overlap the bit intervals of the component B transmitter (including the effects of the propagation delay of signal wavefronts traveling on the interconnect 308 ). The transmitter 302 uses an internal timing signal, CLK _TA , to frame its bit interval. An event on the timing signal determines when a new bit is to be driven.

[0068] Alternate embodiments might permit the bit intervals of the component A transmitter to overlap the bit intervals of the component B transmitter. This is called simultaneous bidirectional signaling. The testing features that have been added to interface 300 could also be added to an interface that permitted simultaneous bidirectional signaling.

[0069] The transmitter 302 further includes a predriver element 318 , two differential driver elements 320 and 322 , two current source elements 324 and 326 , a current control element 314 , a register element 316 , and a transmit clock aligner element 312 . In one embodiment, the register element 316 is a register cell that samples the T _A signal (transmit signal from other circuits on component A) and drives it on the rising edge of the CLK _TA signal. The transmit clock aligner element 312 creates the CLK _TA signal from the CLK _TREF reference signal. In various embodiments, the transmit clock aligner element 312 is a phase lock loop (“PLL”) or a delay lock loop (“DLL”) circuit. The output of the register element 316 connects to the predriver element 318 , which connects to the differential driver elements 320 and 322 . Each driver element 320 and 322 is an open drain transistor, and is connected in series with one of the current source elements 324 and 326 , respectively. The current control element 314 maintains a sink current Of I _OL (output low current) in the current source elements using an external reference value I _REF .

[0070] In an alternate embodiment, the two current source elements 324 and 326 could be merged into a single current source element, with one terminal connecting to the low supply voltage (ground) and the other terminal connecting to the source terminals of the two driver elements 320 and 322 . This will be equivalent to the circuit shown in transmitter 302 since only one of the two driver elements 320 and 322 may be on at any time.

[0071] When the transmitter 302 drives a bit, one of the two driver elements 320 and 322 is on, and the other is off. The output voltage of the driver element that is off will remain high at the termination value, and the output voltage of the driver element that is on will assume a lower voltage. As a result, high output voltage V _OH (high logic value) and low output voltage V _OL (low logic value) on interconnect 308 are:

V _OH =V _T Equation 1

V _OL =V _T −I _OL *R _T /2 Equation 2

[0072] There is a “R _T /2” factor in Equation 2 reflects the fact that the interconnect 308 is terminated at both ends in a termination load of R _T which is presumed to match Z _o , the characteristic impedance of interconnect 308 . The specification for the transmitter circuit requires that the V _P and V _N voltage values remain above V _OL,MAX or below V _OH,MIN for a time t _Q,MAX after the rising edge of CLK _TREF until a time t _V,MIN after the next rising edge of CLK _TREF . The width of the (t _Q,MAX −t _V,MIN ) window depends upon three factors in this example. The first factor is the width of the (t _Q-T,MAX -t _V-T,MIN ) window of the TA register relative to the CLK _TA rising edge. The second factor is the range of propagation delay (t _PROP-T,MAX −t _PROP-T,MIN ) through the predriver element 318 and driver elements 320 and 322 . The third factor is the range of timing skew (t _SKEW-T,MAX −t _SKEW-T,MIN ) between the CLK _TREF and CLK _TA signals from the transmit clock aligner element 312 . The following equation can be written:

( t _Q,MAX −t _V,MIN )=( t _Q-T,MAX −t _V-T,MIN )+( t _PROP-T,MAX −t _PROP-T,MIN )+( t _SKEW-T,MAX −t _SKEW-T,MIN ) Equation 3

[0073] Of the three factors, the width of the (t _Q-T,MAX −t _V-T,MIN ) window of the TA register relative to the CLK _TA rising edge will usually be the smallest, and the range of timing skew (t _SKEW-T,MAX −t _SKEW-T,MIN ) between the CLK _TREF and CLK _TA signals will usually be the largest. The three factors have a timing range because of variations of manufacturing process (between different components) and variations in temperature and supply voltages during system operation.

[0074] The transmitter 302 elements described so far are similar to known transmitter elements. The transmitter 302 further includes a multiplexer 327 . The multiplexer 327 selects data from one of two sources to be transmitted via the T _A signal. Specifically, multiplexer 327 selects data from other circuits to be transmitted in normal operation. Alternatively, the multiplexer 327 selects a test pattern set from a test circuit 340 , as described in more detail below.

[0075] The receiver 304 includes a voltage discriminator element 332 , a register element 330 , and a receive clock aligner element 328 . In one embodiment, the voltage discriminator element 332 is a differential comparator that compares the voltage values on the V _P (positive voltage) and V _N (negative voltage) interconnects to determine what symbol is present (e.g., a “1” or a “0”). The register element 330 is a time discriminator element that samples the output of the voltage discriminator element 332 on the rising edge of the CLK _RA signal (the receive clock signal of component A), stores it, and drives it as the R _A signal (receive signal of component A), to be used by other circuits on the component A. The receive clock aligner element 328 creates the CLK _RA signal from the CLK _RREF (receive clock reference) reference signal. In various embodiments, the receive clock aligner element 328 is a phase lock loop (“PLL”) or a delay lock loop (“DLL”) circuit.

[0076] Typical specification for the receiver 304 requires that the V _P and V _N voltage values remain above V _IL,MAX or below V _IH,MIN for a time t _S,MIN (minimum setup time) before and a time t _H,MIN (minimum hold time) after the rising edge of CLK _RREF . The width of the (t _S,MIN +t _H,MIN ) window depends upon three factors in this example. The first factor is the width of the (t _S-R,MIN +t _H-R,MIN ) window of the R _A signal from register element 330 relative to the CLK _RA rising edge. The second factor is the range of propagation delay (t _PROP-R,MAX −t _PROP-R,MIN ) through the voltage discriminator 332 . The third factor is the range of timing skew (t _SKEW-R,MAX −t _SKEW-R,MIN ) between the CLK _RREF and CLK _RA signals from the receive clock aligner element 328 . The following equation can be written:

( t _S,MIN +t _H,MIN )=( t _S-R,MIN +t _H-R,MIN )+( t _PROP-R,MAX −t _PROP-R,MIN )+( t _SKEW-R,MAX −t _SKEW-R,MIN ) Equation 4

[0077] Of the three factors, the width of the (t _S-R,MIN +t _H-R,MIN ) window of the R _A register relative to the CLK _RA rising edge will usually be the smallest, and the range of timing skew (t _SKEW-R,MAX −t _SKEW-R,MIN ) between the CLK _RREF and CLK _RA signals will usually be the largest. The three factors have a timing range because of variations of manufacturing process (between different components) and variations in temperature and supply voltages (during system operation). The receiver 304 uses an internal timing signal, CLK _RA , to sample a bit during its bit interval. An event on the timing signal determines when a new bit is to be sampled and held.

[0078] The receiver 304 further includes a test circuit 340 and a test circuit 342 . In one embodiment, the test circuit 340 consists of pattern memory and pattern generation circuitry 346 that creates a stream of bits, or pattern set, that may be steered to the transmitter 302 and driven onto the interconnect 308 . Alternatively, the stream of bits may be compared in the compare circuit 348 to a second stream of bits which the receiver 304 has sampled from the interconnect 308 , and the compare results (pass or fail) indicated. The test circuit 340 is controlled by other circuitry (not shown), or by other signals received by component A (not shown), or both. Typically, these other signals will utilize a low bandwidth interface, which will not present the testing and characterization issues that exist in prior testing systems. This other circuitry or other signals control the operation of the test circuit 340 . For example, the other circuitry or signals dictates when the pattern set starts and ends, which pattern set is to be used, whether the transmitter 302 or receiver 304 is being used, and whether some of the pattern comparisons are to be ignored, or masked.

[0079] Alternatively, the compare circuit 348 could include delay circuitry that permits the stream of bits from the pattern memory and pattern generation circuitry 346 to be aligned to the bit stream from receiver 304 . This would permit a single bit stream from the pattern memory and pattern generation circuitry 346 to be steered to the transmitter 302 , driven to the receiver 304 in the same interface 300 , and compared to the delayed version of the original bit stream.

[0080] The receiver 304 further includes a test circuit 342 . The test circuit 342 includes an analog sampling circuit 356 , a series of differential comparator elements 354 , a series of register elements 352 , and a multiplexer 350 . The analog sampling circuit 356 includes two NMOS transistors 360 a and 360 b , and two capacitors 358 a and 358 b . As will be described in more detail below, the analog sampling circuit 356 samples by utilizing a T _REF 362 signal that is used in embodiments for facilitating testing and characterization of one component by another and of one component by itself by decoupling respective transmitter and receiver parameters.

[0081] The differential comparator element 354 a receives the outputs of analog sampling circuit 356 . The analog sampling circuit 356 includes NMOS transistors 360 a and 360 b and capacitors 358 a and 358 b to sample voltage values V _P and V _N . The analog sampling circuit 356 and its function will be described in more detail below. The differential comparator element 354 b receives V _N and V _REF . The differential comparator element 354 c receives V _P and V _REF . The register element 352 a receives the output of the differential comparator element 354 a . The output of the register element 352 a is the signal R _TT , or receiver time test signal which has the same digital value as the received RA signal but is time-sampled by the analog sampling circuit 356 instead of being time-sampled by register element 330 . The register element 352 b receives the output of the differential comparator element 354 b . The differential comparator elements 354 b and 354 c compare the respective V _P and V _N voltage values to a reference voltage signal V _REF . The results of the two comparisons are received by the respective register elements 352 b and 352 c on the rising edge of CLK _RA to produce the R _TN (receiver test negative signal) and R _TP (receiver test positive signal) signals. Note that the R _TN signal is inverted relative to the R _TP signal because the V _P and V _N voltage values are complementary.

[0082] Multiplexer 350 receive the outputs of all of the register elements 352 . The multiplexer 350 selects one of the outputs of the register elements 352 or the received signal R _A to transmit to the compare circuit 348 of the test circuit 340 for comparison with a test pattern. Signal R _A is also continually sent to other circuits as in normal operation.

[0083] The compon