DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention. For instance, the present invention has application in connection with non-volatile read-only memory erasable by ultraviolet light and electrically programmable (EPROM) and also electrically erasable and programmable read-only memory (EEPROM) chips. In addition, the difference amplifier circuits for sensing the difference between the target memory cell and the reference memory cell may be implemented using various forms of active or passive circuits, and the respective circuits providing the input and output signals may be implemented in a number of modified forms. The preferred circuits depicted in FIG. 4 show an exemplary arrangement and use a high-speed sensing means in accordance with the present invention, but it should be recognized that other circuits may be implemented within the scope of the present invention without loss of generality.

[0024] FIG. 2 depicts a typical differential amplifier circuit that may be used with the present invention. The difference amplifier has a first input line, a second input line, and an output line. A sensing reference signal from a reference memory cell is compared to a source signal from one of the memory array column lines, and the binary state of the source memory cell is the output of the amplifier. The source and n-well of p-channel metal-oxide semiconductor field-effect transistors (MOSFETs) P 21 and P 22 are coupled to a predetermined voltage Vcc, with the gates of P 21 and P 22 coupled to the drain of P 22 and the drain of n-channel MOSFET N 22 and the gate of n-channel MOSFET N 24 . The drain of P 21 couples to the drain of n-channel MOSFET N 21 and the gate of n-channel MOSFET N 25 . The first input line is coupled to the gate of N 21 , and the second input line is coupled to the gate of N 22 . The sources of N 21 and N 22 are connected to the drain of n-channel MOSFET N 23 , which has its source coupled to predetermined voltage Vss and its gate coupled to predetermined voltage Vbias and the gate of n-channel MOSFET N 26 . N 26 has its source coupled to Vss, with its drain coupled to the sources of N 24 and N 25 . The source and n-well of p-channel MOSFETs P 23 and P 24 are coupled to a predetermined voltage Vcc, with the gates of P 23 and P 24 coupled to the drain of P 23 and the drain of N 24 . The drain of P 24 is coupled to the drain of N 25 and the output line.

[0025] The difference amplifier separates further the relatively low voltage swing between a binary high state and a binary low state that may be stored in a memory device. The reference memory device will supply at the negative (−) input of the differential amplifier a predetermined sensing-reference voltage upon Vbias going high. The selected memory device within the memory array will supply at the positive input a voltage either slightly lower or slightly higher than the reference voltage, depending on whether the device represents a binary low or binary high state, respectively.

[0026] If the memory device represents a binary low state, the voltage it supplies to the positive input of the differential amplifier will be slightly less than the voltage supplied by the reference device to the negative input. The difference between the voltage supplied by the device and the voltage supplied by reference device will be slightly less than zero. The output of the differential amplifier will therefore be low, because the voltage across the positive and negative terminals is not a positive voltage.

[0027] If the memory device represents a binary high state, the voltage it supplies to the positive input of the differential arnplifier will be slightly greater than the voltage supplied by the reference device to the negative input. The difference between the voltage supplied by the device and the voltage supplied by the reference device will be slightly higher than zero. The output of the differential amplifier will therefore be high, because the voltage across the positive and negative terminals is positive.

[0028] FIG. 3 illustrates a new and novel read-biasing and amplifying circuit compatible with the present invention. The read-biasing and amplifying circuit has an input line Din and an output line Dout. P-channel MOSFETs P 31 , P 32 , and P 33 each have their source and n-well coupled to the predetermined voltage Vcc. The gates of P 31 and P 32 couple to each other and the predetermined voltage Vss, and the drains of P 32 and P 33 couple to each other and the gate of P 33 and Dout. The source of n-channel MOSFET N 31 couples to the predetermined voltage Vss, and the drain of N 31 couples to the gate of n-channel MOSFET N 32 and the drain of P 31 . The gate of the N 31 couples to Din and the source of N 32 . The drain of the N 32 couples to the drains of P 32 and P 33 and the gate of P 33 and Dout.

[0029] The read-biasing and amplifying circuit used is a new and novel approach. The quick-charging transistor for biasing the bit line for sensing is the p-channel transistor, P 33 . This device operates in the saturated region of operation for quick charging of the bit line and is “off” during sensing. During sensing, transistor P 32 , which is in the linear region of operation, provides current and acts as the load for the memory cell being sensed. Transistors N 31 , N 32 and P 31 form a feedback biasing circuit which limits the bit line voltage during sensing. Limiting the bit line voltage during read operations is required by the floating-gate memory cells to prevent read disturbs. This circuit is an improvement over prior art because the feedback biasing circuit consists of only three transistors, rather than five or more as in prior art, and therefore is faster. Having a fast feedback path is also important in preventing overshoot of the bit line during charging because overshoot can cause additional delays during sensing. Furthermore, the quick-charging device not only charges the bit line node but also provides quick charging of the read-biasing and amplifying circuit's output node, Dout. This again results in a speed improvement over the prior art. Also, with the sensing load operating in the linear, or resistive, region of operation rather than in saturation mode, the voltage differential to the differential amplifier is more linear with memory cell currents. This results in a more equal voltage difference for the same amount of current difference between the reference current and the memory cell stored “one” and “zero” states.

[0030] Within the preferred embodiment of the invention, the new and novel biasing circuit acts to quickly pull up the input line to the bias potential needed during the sensing of the data stored on a selected memory device, and to prevent overshoot on this line that would otherwise result from such a fast pull up. The input line Din initially discharges to ground. Afterwards, with transistor P 32 serving as a load to the memory device coupled to the input line, transistor P 33 acts as a quick-charging device to quickly pull the input line up to the read-bias potential used in reading the selected memory device. The feedback circuit comprised of transistors N 31 , P 31 , and N 32 prevent the input line from overshooting the read-bias potential on the memory device coupled to the line.

[0031] For example, if the selected memory device coupled to the line input Din has no charge on its gate (corresponding to a logic zero), the device will conduct. Transistor P 33 will quickly raise the potential at the line until transistor N 31 turns on, which in conjunction with transistors P 31 and N 32 will ensure that the potential at the input line does not rise above Vss plus the threshold voltage of transistor N 31 . By preventing the input line from rising above this potential, the feedback circuit limits the maximum voltage in the bit lines at the memory cells. Dout will stabilize at a predetermined voltage less than the reference voltage, and will output to the differential amplifier a potential representing binary low.

[0032] If on the other hand the selected memory device coupled to the line input Din has a negative charge on its gate (corresponding to a logic one), the device will either be off or will only slightly conduct, at a lesser current level than the reference device. Transistor P 33 will quickly pull up the potential at the line until transistor N 31 turns on, which in conjunction with transistors P 31 and N 32 will ensure that the potential at the input line does not rise above Vss plus the threshold voltage of transistor N 31 . Again, by preventing the input line from rising above this potential, the feedback circuit limits the maximum voltage on the bit lines of the memory cells. Dout will stabilize at a predetermine voltage greater than the reference voltage, and will output to the differential amplifier a potential representing binary high.

[0033] FIG. 5 shows an alternative embodiment with an enable control, {overscore (E)}. This sensing circuit operates similar to the preferred embodiment, except that the gate of P 31 couples to an enable line, {overscore (E)}, and an additional n-channel MOSFET transistor N 33 has its drain coupled to the gate of N 32 , its source coupled to Vss, and its gate also coupled to the enable line. Upon {overscore (E)} going low, transistor P 31 turns on and N 33 turns off, which enables the feedback circuit to turn on when Din is coupled to a selected memory device. When {overscore (E)} goes high, a sensing operation cannot occur. Transistor N 33 turns on and P 31 turns off, which in turn prevents transistor N 32 from turning on. Since transistor N 32 connects the quick-charging transistor P 33 to the input line Din, if N 32 does not turn on, then Dout will not reflect the potential at Din. Therefore, essential to the correct operation of the alternative embodiment is for {overscore (E)} to go low when a sensing operation is to occur.

[0034] FIG. 7 shows yet another alternative embodiment with an enable control, {overscore (E)}. This alternative embodiment is identical to that depicted in FIG. 5 , except that an n-channel MOSFET N 50 supplants the p-channel transistor P 33 in FIG. 5 as the quick-charging device. The drain and gate of transistor N 50 couple to the predetermined voltage Vcc, while transistor N 50 's source couples to output line Dout. Other than this modification, the alternative embodiment of FIG. 7 operates identically to the embodiment portrayed in FIG. 5 . Because n-channel transistors have a higher transconductance than p-channel transistors, employing an n-channel transistor as the quick-charging device results in less capacitive loading on the device itself (viz., less self-loading) than if using a p-channel transistor. The ensuing advantage is that the read-biasing and amplifying circuit operates more quickly than if the quick-charging device were a p-channel transistor.

[0035] In addition to the read-biasing and amplifying circuit, the invention consists of the sensing arrangement described in FIG. 4 . A sensing reference is provided by a p-channel MOSFET P 41 with the source and n-well coupled to the predetermined voltage Vcc, and the gate and drain coupled to the second input line of the difference amplifier. A first read-biasing and amplifying circuit has its output line coupled to the gate and drain of the P 41 and the second input line of the difference amplifier and a sense reference. N-channel MOSFETs N 50 and N 51 are coupled in series connection, with the gates of N 50 and N 51 being connected to the predetermined voltage Vcc, the drain of the N 51 coupled to the source of the N 50 , and the drain of the N 50 coupled to the input line of the first read-biasing circuit. A reference floating-gate memory device has the source coupled to a predetermined reference source, the gate coupled to a reference bias voltage Vrefbias and the drain coupled to the source of transistor N 51 .

[0036] The sensing reference is not a reference column in the array, but rather is a single cell. It is biased with a voltage, Vrefbias, which controls the reference current to which the memory cells are compared. A single reference can be used by one or by multiple differential sense amps. In a typical implementation, a plurality of sense amplifiers can share a single reference. Since this results in more loading on the sense reference line, an additional quick-charging transistor, P 41 , may be added to the sense reference signal.

[0037] In this sensing circuit, PCL, a clock pulsed high, pulls the bit lines low prior to sensing, as shown in FIG. 6 . For improved performance, the bit lines are not disconnected from the read-biasing and amplifying circuit. This improves performance because the bit lines do not have any additional delay or loading from an isolation device gated by PCL. This does have the disadvantage of drawing current through the read-biasing and amplifying circuit during the time of pulling the bit lines low. However, this current can be controlled by proper sizing of the quick-charging devices. This arrangement has an additional speed advantage resulting from not using the memory cells to discharge the bit lines from the programmed cell read-bias level to the erased cell read-bias level. The additional speed advantage is achieved by bringing the addressed word line high while PCL is discharging the bit lines. Once PCL has gone low, the read-biasing and amplifying circuit will quickly pull the selected bit lines to the read-bias levels. If the memory cell being read is an erased cell, then it will be conducting current and the bit line will not be pulled as high as if the cell is programmed. A programmed cell is either conducting no current or significantly less current than the erased cell. The high-speed sensing comes from the combination of the bit lines being pre-charged low, while the word line being accessed, and the strong pull up and biasing speed of the read-biasing and amplifying circuit.

[0038] In other words, the new and novel approach of the invention lies in quickly discharging the bit line to a potential close to ground, and then quickly charging the line back up to the read-bias levels without discharging the line with the selected memory devices. In the preferred embodiment, the bit line Din discharges to ground upon the clock pulse PCL going high. After the bit line goes low, and upon the clock pulse PCL going low, the sensing amplifier quickly pulls the potential of the line to the read-bias potential of the selected memory device. The feedback circuit of the sensing amplifier limits overshoot considerably. If the selected memory device carries no charge on its floating gate (viz., it is an “erased” cell), overshoot never exceeds the predetermined reference voltage. Furthermore, if the selected memory devices carries a negative charge on its floating gate (viz., a “programmed” cell), overshoot is essentially negligible. FIG. 6 also shows how Dout and Din indicate either a low or high binary state vis-a-vis the sense-reference potential. Din and Dout are relatively lower than their respective reference potentials when indicating a binary low stored on a memory device, and are relatively higher when indicating a binary high.

[0039] FIG. 8 is a block diagram of an exemplary computer 45 that may incorporate the present invention. The computer 45 includes a microprocessor 46 and corresponding clock 48 . The microprocessor 46 contains the central processing unit (CPU) and associated control circuitry. The microprocessor 46 is connected to a motherboard 49 . An I/O interface module 47 is connected to the motherboard 49 and interfaces the microprocessor 46 with peripheral devices such as a monitor and printer. The motherboard 49 also contains a plurality of memory modules for storing data, such as single in-line memory modules (SIMMs) 50 A- 50 N. The motherboard 49 is typically implement with a printed circuit board, and the SIMMs 50 A- 50 N are typically implemented with integrated circuit chips which “plug into” the motherboard 49 . A non-volatile memory is usually used on the motherboard 49 , SIMMs 50 A- 50 N, or through the I/O interface module 47 .

[0040] The foregoing description, which has been disclosed by way of the above examples and discussion, addresses preferred embodiments of the present invention encompassing the principles of the present invention. The embodiments may be changed, modified, or implemented using various circuit types and arrangements. For example, the difference amplifier circuit for sensing the difference between the target memory cell and the reference memory cell may be implemented using various forms of active or passive circuits, and the respective circuits providing the input and output signals may be implemented in a number of modified forms. Those skilled in the art will readily recognize that these and various other modifications and changes may be made to the present invention without strictly following the exemplary embodiments and applications illustrated and described herein, without departing from the true spirit and scope of the present invention which is set forth in the following claims.