Title:
Printed wiring board and its manufacturing method
Document Type and Number:
Kind Code:
A1

Abstract:
The present invention has for its object to provide a process for manufacturing multilayer printed circuit boards which is capable of simultaneous via hole filling and formation of conductor circuit and via holes of good crystallinity and uniform deposition can be constructed on a substrate and high-density wiring and highly reliable conductor connections can be realized without annealing.

The present invention is related to a process for manufacturing multilayer printed circuit boards which comprises disposing an interlayer resin insulating layer on a substrate formed with a conductor circuit, creating openings for formation of via holes in said interlayer resin insulating layer, forming an electroless plated metal layer on said interlayer resin insulating layer, disposing a resist thereon, performing electroplating, stripping the resist off and etching the electroless plated metal layer to provide a conductor circuit and via holes, wherein the electroplating is performed intermittently using said electroless plated metal layer as cathode and a plating metal as anode at a constant voltage between said anode and said cathode.


Representative Image:
Inventors:
En, Honchin (Ibi-gun, JP)
Nakai, Tohru (Ibi-gun, JP)
Oki, Takeo (Tsushima-shi, JP)
Hirose, Naohiro (Ibi-gun, JP)
Noda, Kouta (Ibi-gun, JP)
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Sponsored by:
Flash of Genius
Application Number:
10/751428
Publication Date:
07/15/2004
Filing Date:
01/06/2004
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Assignee:
IBIDEN CO., LTD.
Primary Class:
International Classes:
(IPC1-7): H05K001/00
Attorney, Agent or Firm:
Sughrue Mion, Pllc (2100 PENNSYLVANIA AVENUE, N.W., WASHINGTON, DC, 20037, US)
Claims:
1. An electroplating process comprising electroplating an electrically conductive substrate wherein the electroplating is performed intermittently using said substrate surface as cathode and a plating metal as anode at a constant voltage between said anode and said cathode.

2. The electroplating process according to claim 1 wherein said intermittent electroplating is performed by repeating application of a voltage between a cathode and an anode and interruption of said application alternately with a voltage time/interruption time ratio of 0.01 to 100, a voltage time of not longer than 10 seconds and an interruption time of not less than 1×10−12 seconds.

3. A process for producing a circuit board comprising a substrate and, as formed thereon, a conductor circuit by electroplating which is performed intermittently using the electrically conductive conductor circuit-forming surface as cathode and a plating metal as anode at a constant voltage between said anode and said cathode.

4. The process for producing a circuit board according to claim 3 wherein said intermittent electroplating is performed by repeating application of a voltage between a cathode and an anode and interruption of said application alternately with a voltage time/interruption time ratio of 0.01 to 100, a voltage time of not longer than 10 seconds and an interruption time of not less than 1×10−12 seconds.

5. A process for manufacturing a printed circuit board which comprises disposing a resist on an electrically conductive layer formed on a substrate, performing electroplating, stripping the resist off and etching said electrically conductive layer to provide a conductor circuit, wherein the electroplating is performed intermittently using said electrically conductive layer as cathode and a plating metal as cathode at a constant voltage between said anode and said cathode.

6. A process for manufacturing a printed circuit board which comprises disposing an interlayer resin insulating layer on a substrate formed with a conductor circuit, creating openings for formation of via holes in said interlayer resin insulating layer, forming an electroless plated metal layer on said interlayer resin insulating layer, disposing a resist thereon, performing electroplating, stripping the resist off and etching the electroless plated metal layer to provide a conductor circuit and via holes, wherein the electroplating is performed intermittently using said electroless plated metal layer as cathode and a plating metal as anode at a constant voltage between said anode and said cathode.

7. The process for manufacturing a printed circuit board according to claim 6 wherein said interlayer resin insulation layer has a metal layer on its surface.

8. The process for manufacturing a printed circuit board according to claim 5, 6 or 7 wherein said intermittent electroplating is performed by repeating application of a voltage and interruption of application alternately with a voltage time/interruption time ratio of 0.01 to 100, a voltage time of not longer than 10 seconds and an interruption time of not less than 1×10−12 seconds.

9. A circuit board comprising a substrate and, as built thereon, a circuit comprised of a copper film, wherein said copper film has properties that (a) its crystallinity is such that the X-ray diffractiion half-width of the (331) plane of copper is less than 0.3 deg and (b) the variation in thickness ((maximum thickness-minimum thickness) /average thickness) of said copper film as measured over the whole surface of said substrate is not greater than 0.4.

10. The circuit board according to claim 9 wherein said copper film has an elongation of not less than 7%.

11. A printed circuit board comprising a substrate and, as built thereon, a circuit comprised of a plated copper film, wherein said plated copper film has properties that (a) its crystallinity is such that the X-ray diffraction half-width of (331) plane of copper is less than 0.3 deg and (b) the variation in thickness ((maximum thickness-minimum thickness)/average thickness) of said plated copper layer as measured over the whole surface of said substrate is not greater than 0.4.

12. A printed circuit board comprising a substrate formed with a conductor circuit, an interlayer resin insulating layer built thereon and a conductor circuit comprised of a copper film as built on said interlayer resin insulating layer, said interlayer resin insulating layer having vial holes by which said conductor circuits are interconnected, wherein said copper film has properties that (a) its crystallinity is such that the X-ray diffraction half-width of (331) plane of copper is less than 0.3 deg and (b) the variation in thickness ((maximum thickness-minimum thickness)/average thickness) of said copper film as measured over the whole surface of said substrate is not greater than 0.4.

13. The printed circuit board according to claim 11 or 12 wherein said copper film has an elongation of not less than 7%.

14. An electroless plating solution which comprises an aqueous solution containing 0.025 to 0.25 mol/L of a basic compound, 0.03 to 0.15 mol/L of a reducing agent, 0.02 to 0.06 mol/L of copper ion and 0.05 to 0.3 mol/L of tartaric acid or a salt thereof.

15. An electroless plating solution which comprises an aqueous solution containing a basic compound, a reducing agent, copper ion, tartaric acid or a salt thereof and at least one metal ion species selected from the group consisting of nickel ion, cobalt ion and iron ion.

16. The electroless plating solution according to claim 14 or 15 wherein said electroless plating solution has a specific gravity of 1.02 to 1.10.

17. The electroless plating solution according to any of claims 14 to 16, the temperature of which is 25 to 40° C.

18. The electroless plating solution according to any of claims 14 to 17 wherein the copper deposition rate of said electroless plating solution is 1 to 2 μm/hour.

19. An electroless plating process which comprises immersing a substrate in the electroless plating solution according to any of claims 14 to 17 and performing electroless copper plating at a deposition rate set to 1 to 2 μm/hour.

20. The electroless plating process according to claim 19 wherein said substrate has a roughened surface.

21. A process for manufacturing a printed circuit board which comprises immersing a resin insulating substrate board in the electroless plating solution according to any of claims 14 to 17 and performing electroless copper plating at a deposition rate set to 1 to 2 μm/hour to provide a conductor circuit.

22. A printed circuit board comprising a resin insulating substrate board formed with a roughened surface and, as built thereon, a conductor circuit comprising at least an electroless plated film, wherein said electroless plated film has a stress of 0 to +10 kg/mm2.

23. A printed circuit board comprising a resin insulating substrate board formed with a roughened surface and, as built thereon, a conductor circuit comprising at least an electroless plated film, wherein said electroless plated film is complementary to said roughened surface with the electroless plated film in convex areas of the roughened surface being relatively greater in thickness than said film in concave areas of said roughened surface.

24. A printed circuit board comprising a substrate board formed with a lower-layer conductor circuit and, as built thereon, an upper-layer conductor circuit through the intermediary of an interlayer resin insulating layer, with said upper-layer conductor circuit and said lower-layer conductor circuit being interconnected by via holes, wherein said upper-layer conductor circuit comprises at least an electroless plated film, said interlayer resin insulating layer is provided with a roughened surface, said electroless plated film is complementary to said roughened surface, and bottoms of said via holes are also provided with an electroless plated film having a thickness equal to 50 to 100% of the thickness of the electroless plated film on said interlayer resin insulating layer.

25. A printed circuit board comprising a resin insulating substrate board and, as built thereon, a conductor circuit comprising at least an electroless plated film, wherein said electroless plated film comprises copper and at least one metal species selected from the group consisting of nickel, iron and cobalt.

26. The printed circuit board according to claim 25 wherein the proportion of said at least one metal species selected from the group consisting of nickel, iron and cobalt is 0.1 to 0.5 weight %.

27. A process for manufacturing a multilayer printed circuit board which comprises at least the following steps (1) to (5). (1) a step for thinning the copper foil of a copper-clad laminate by etching (2) a step for piercing through holes in said copper-clad laminate (3) a step for depositing a plated metal film on said copper-clad laminate to construct plated-through holes within said through holes (4) a step for pattern-etching the copper foil and plated metal film on said copper-clad laminate to construct a conductor circuit (5) a step for serially building up an interlayer resin insulating layer and a conductor layer alternately over said conductor circuit.

28. A process for manufacturing a multilayer printed circuit board which comprises at least the following steps (1) to (7): (1) a step for thinning the copper foil of a copper-clad laminate by etching (2) a step for piercing through holes in said copper-clad laminate (3) a step for forming a conductor film on said copper-clad laminate (4) a step of disposing a resist on the area free from conductor circuits and plated-through holes (5) a step for providing a plated metal film in the resist-free area to construct a conductor circuit and plated-through holes (6) a step for stripping off said resist and etching the conductor film and copper foil underneath the resist (7) a step for serially building up an interlayer resin insulating layer and a conductor layer alternately over said conductor circuit.

29. The process for manufacturing a multilayer printed circuit board according to claim 27 or 28 wherein a laser is used for piercing the through holes in said copper-clad laminate.

30. The process for manufacturing a multilayer printed circuit board according to claim 27 or 28 wherein a drill is used for piercing the through holes in said copper-clad laminate.

31. The process for manufacturing a multilayer printed circuit board according to any of claims 27 to 30, wherein, in the step for thinning the copper foil of said copper-clad laminate by etching, the thickness of the copper foil is reduced to 1 to 10 μm.

32. (Amended) A multilayer printed circuit board comprising a core board having a conductor circuit and, as built over said conductor circuit, a buildup wiring layers obtainable by building up an interlayer resin insulating layer and a conductor layer alternately with the conductor layers being interconnected by via holes, wherein said core board comprises a copper-clad laminate, the conductor circuit on said core board comprises the copper foil of said copper-clad laminate and a plated metal layer, and the thickness of the conductor circuit on said core board is not greater by more than 10 μm than the thickness of the conductor layer on said interlayer resin insulating layer.

33. (Cancelled)

34. A process for manufacturing a multilayer printed circuit board which comprises thinning the copper foil of a copper-clad laminate by etching, pattern-etching the copper foil of said copper-clad laminate to construct a conductor circuit and building up serially an interlayer resin insulating layer and a conductor layer alternately over said conductor circuit wherein the thickness of the conductor circuit on said core board is controlled so as to be not greater by more than 10 μm than the thickness of the conductor layer on said interlayer resin insulating layer.

35. A process for manufacturing a multilayer printed circuit board which comprises constructing an interlayer insulating layer on a substrate formed with a lower-layer conductor circuit, piercing openings in said interlayer insulating layer, imparting electrical conductivity to the surface of said interlayer insulating layer and the inner walls of said openings, performing electroplating to fill up said openings and thereby provide via holes and, at the same time, construct an upper-layer conductor circuit, wherein said electroplating is performed using an aqueous solution containing a metal ion and 0.1 to 1.5 mmol/L of at least one additive selected from the group consisting of a thiourea, a cyanide and a polyalkylene oxide as a plating solution.

36. The process for manufacturing a multilayer printed circuit board according to claim 35 wherein the aspect ratio of said openings for via holes, i.e. depth of opening/diameter of opening, is 1/3 to 1/1.

37. A multilayer printed circuit board comprising a core board and, as constructed on both sides thereof, a buildup wiring layers obtainable by building up an interlayer resin insulating layer and a conductor layer alternately with said conductor layers being interconnected by via holes, wherein said via holes are formed in the manner of plugging the through holes in plated-through holes in said core board.

38. The multilayer printed circuit board according to claim 37 wherein the through holes in said plated-through holes have a diameter of not more than 200 μm.

39. A process for manufacturing a multilayer printed circuit board which comprises at least the following steps (1) to (4): (1) a step for piercing through holes not larger than 200 μm in diameter in a core board by laser (2) a step for plating said through holes therein to construct plated-through holes (3) a step for constructing an interlayer resin insulating layer provided with openings communicating with said plated-through holes on the core board (4) a step for plating the openings in said interlayer resin insulating layer to construct via holes in the manner of plugging the through holes in said plated-through holes.

40. A multilayer printed circuit board comprising a core board and, as constructed on both sides thereof, a buildup wiring layers obtainable by building up an interlayer resin insulating layer and a conductor layer alternately with via holes interconnecting conductor layers, wherein the via holes in a lower layer are disposed immediately over the plated-through holes in said core board and via holes in an upper layer are disposed immediately over said via holes in the lower layer.

41. A multilayer printed circuit board comprising a core board and, as constructed on both sides thereof, a buildup wiring layers obtainable by building up an interlayer resin insulating layer and a conductor layer alternately with via holes interconnecting conductor layers, wherein said plated-through holes of core board are filled with a filler, with the surfaces of said filler which are exposed from said plated-through holes being covered with a conductor layer provided with lower-layer via holes and upper-layer via holes being disposed immediately over said lower-layer via holes.

42. A multilayer printed circuit board comprising a core board and, as constructed on both sides thereof, a buildup wiring layers obtainable by building up an interlayer resin insulating layer and a conductor layer alternately with via holes interconnecting conductor layers, wherein via holes in a lower layer are disposed to plug the through holes of plated-through holes in said core board, with via holes in an upper layer being disposed immediately over said via holes in the lower layer.

43. The multilayer printed circuit board according to any of claims 40 to 42 which comprises bumps formed immediately above said plated-through holes.

44. The multilayer printed circuit board according to any of claims 40 to 43 wherein said lower-layer via holes are filled with metal.

45. The multilayer printed circuit board according to any of claims 40 to 42 wherein valleys of said lower-layer via holes are filled with a conductive paste.

46. The multilayer printed circuit board according to any of claims 40 to 42 wherein valleys of said lower-layer via holes are filled with a resin.

Description:

TECHNICAL FIELD

[0001] The present invention relates to a printed circuit board and to a method for production thereof. The invention further relates to plating methods and plating solutions which can be applied to the above production of printed circuit boards. BACKGROUND ART

[0002] With the mounting need for higher functionality and further miniaturization of electronic equipment, advances in integration technology of LSI and in size reduction of components, and changes in the mounting mode, the demand for high-density wiring is getting greater in the field of printed circuit boards and, as a consequence, development of the so-called multilayer circuit boards comprising 3 or more conductor layers has been broadly undertaken.

[0003] In view of the demand for higher wiring density in multilayer circuit boards, the so-called buildup multilayer circuit board is attracting attention. The buildup multilayer circuit board is manufactured by the technology disclosed in Japanese Kokai Publication Hei-4-55555, for instance. Thus, a core substrate board formed with a lower-layer conductor circuit is coated with an electroless plating adhesive comprising a photosensitive resin and, after the coat is dried, exposure to light and development are carried out to provide an interlayer resin insulating layer having openings for via holes. Then, the surface of this interlayer resin insulating layer is roughened with an oxidizing agent or the like and a thin electroless plated copper layer is formed on said interlayer resin insulating layer. Then, a plating resist is disposed thereon and a thick electroplated copper layer is constructed. The plating resist is then stripped off and the thin electroless plated copper layer is etched off to provide a conductor circuit pattern including via holes. This procedure is repeated a plurality of times to provide a multilayer printed circuit board.

[0004] When, in the above process for fabricating a printed circuit board, the direct-current plating (DC plating) method, which is one of the conventional electroplating techniques, is used to provide said electroplated copper layer on a substrate surface, the current generally tends to be concentrated in the marginal area of the substrate surface as compared with the central area so that, as illustrated in FIG. 6 , the thickness t 12 of the copper layer in the marginal area of the substrate surface tends to become greater than the thickness t 11 in the central area, thus causing a regional variation in thickness of the electroplated copper layer.

[0005] Since, in actual production runs, said substrate surface is the surface of a substrate board (work size substrate) having a large area corresponding to a large number of printed circuit boards integrated (specifically, the average one has an area of 255 to 510 mm square and there is even one having an area of about 1020 mm square at a maximum), the above tendency is particularly pronounced.

[0006] In the manufacture of printed circuit boards, when the electroplated copper layer constituting a conductor circuit is not uniform in thickness, the insulation interval t 14 between conductor layers in the marginal region of the substrate board is relatively smaller than the insulation interval t 13 between conductor layers in the central region of the substrate board as shown in FIG. 7 , so that the thickness of the insulating layer 1101 b between conductor layers must be increased in order to insure a sufficient insulation in all regions of the printed circuit board but this is a hindrance to the implementation of high-density wiring.

[0007] In addition, when the copper layer is formed by direct current plating, the crystallinity of the plated copper is low because of the use of an organic additive for improved throwing power. Moreover, the residual stress in the plated copper layer is fairly large so that the layer tends to develop cracks and other flaws and show low elongation and high tensile strength characteristics. Therefore, an annealing step for reducing the residual stress has been essential to the manufacture of printed circuit boards.

[0008] As a technology for insuring the uniformity of thickness of the plated copper layer, it has been proposed to form a thick plated copper layer by electroless plating alone without electroplating. However, the thick plated copper layer formed by electroless plating is poor in ductility because of the unavoidable contamination of the layer with many impurities inclusive of the additives used. Therefore, when a thick plated copper layer is formed by electroless plating, the reliability for the wiring and connection is insufficient and in order to attain a sufficient degree of reliability, an annealing step is indispensable in this case, too.

[0009] To overcome the above problem, a technology for constructing a thick plated copper layer by a constant-current pulse electrolytic technique has been proposed.

[0010] The constant-current pulse electroplating process is characterized in that the plating current is controlled at a constant level and the representative waveform involved is a square wave.

[0011] This technology may be further divided into the process (PC plating process; FIG. 8 ) in which the current is controlled by means of the square pulse wave available by repetition of the alternating supply (ON) and interruption (OFF) of the cathode current and the pulse-reverse electroplating method (PR plating method; FIG. 9 ) in which the current is controlled with a periodically reversed wave available by repetition of the alternating supply of cathode current and supply of anode current. As compared with the direct current electroplating process, the non-steady diffusion layer can be reduced in thickness in either process, with the result that a smooth plated metal layer can be constructed and further that since plating can be effected at a high pulse current density (high overvoltage), the evolution of crystal seeds is promoted to yield finer crystal grains, thus enabling formation of a plated metal layer of high crystallinity. As an example of the PR electroplating method, the process disclosed by Fujinami et al. (Surface Technology, “Formation of Via Filling by PR Electrolysis”, 48 [6], 1997, p.86-87).

[0012] However, when the plated copper layer is formed by PC process, the uniformity of layer thickness is superior to that obtainable by direct current plating process but is not as good as the objective level ( FIG. 4 ).

[0013] On the other hand, the plated copper layer formed by PR process is improved in the uniformity of thickness as compared with the layer obtainable by PC process but is not as high as desired yet and, moreover, plating by PR process requires an expensive current source.

[0014] The current mainstream of electroless plating in the manufacture of printed circuit boards uses EDTA as a complexing agent, and examples of formation of copper circuits with such electroless plating solutions can be found in the Best Mode sections of Japanese Kokai Publication Sho-63-158156 and Japanese Kokai Publication Hei-2-188992 (corresponding to U.S. Pat. No. 5,055,321 and U.S. Pat. No. 5,519,177).

[0015] However, with a plating solution containing EDTA as a complexing agent, a compressive stress (an expanding force) is generated in the plating metal layer to cause peeling of the plated copper film from the resin insulating layer.

[0016] Furthermore, there is also found the problem not to deposit within fine via holes not over 80 μm in diameter.

[0017] Moreover, in the conventional processes for manufacture of printed circuit boards, it was impossible to construct fine-definition line conductor circuits on core boards. Thus, the prior art method for forming a conductor circuit on the core substrate board for a printed circuit board is now described with reference to FIG. 27 . As the core substrate board, a copper-clad laminate 3330 A comprising a resin substrate 3330 and, as clad to both sides thereof, a copper foil 3331 ( FIG. 27 (A)) is used. First, through holes 3332 are drilled in this core board ( FIG. 27 (B)). Then, a plating metal is uniformly deposited ( 3333 ) to form plated-through holes 3336 in said holes 3332 ( FIG. 27 (C)) . Then, the copper foil 3331 formed with the plated metal layer 3333 is subjected to pattern-etching to provide a conductor circuit 3334 ( FIG. 27 (D)) . After an interlayer resin insulating layer 3350 is formed over said conductor circuit 3134 , plating is performed to provide a conductor circuit 3358 ( FIG. 27 (E)).

[0018] In the above process according to the conventional technology, the thickness of copper foil 3331 is at least 18 μm and the thickness of the plated metal layer formed thereon is 15 μm. Since the combined thickness is as large as 33 μm, etching produces undercuts on the lateral sides of the conductor 3334 as shown in FIG. 27 (D) and since the circuit layer then is liable to peel off, it has been impossible to construct a fine-line conductor circuit.

[0019] Furthermore, the conductor circuit 3358 on the interlayer resin insulating layer 3350 , shown in FIG. 27 (E), has been formed in a thickness of about 15 μm. In contrast, the conductor circuit 3334 on the core board 3330 has a thickness of 33 μm. This means that a large impedance difference is inevitable between the conductor circuit 3358 on the interlayer resin insulating layer 3350 and the conductor circuit 3334 on the core board and because of difficulties in impedance alignment, the high-frequency characteristic of the circuit board cannot be improved.

[0020] Moreover, in the above process for fabricating a printed circuit board, when the substrate surface is copper-plated by direct-current (DC) electroplating which is general electroplating technique, the plating metal is deposited in the same thickness over the via hole openings and the conductor circuit-forming area.

[0021] This results in formation of depressions in the areas of the interlayer resin insulating layer which correspond to the via holes. Another problem is that the structure called “stacked via”, namely formation of a via hole over a via hole, cannot be constructed.

[0022] In addition, for the following reasons, the conventional printed circuit board has the drawback that its size and thickness are increased beyond what are required. Thus, as shown in FIG. 38 (A), the printed circuit board 5210 for use as a package board for mounting the IC chip 5290 is fabricated by building up interlayer resin insulating layers 5250 , 5350 and conductor layers 5258 , 5358 in an alternating manner on a core board 5230 formed with plated-through holes 5236 and disposing bumps 5276 U for connection to the IC chip 5290 on the top surface and bumps 5276 D for connection to a mother board on the bottom side. The electrical connection between the top and bottom conductor layers is afforded by via holes 5260 , 5360 . While the via holes 5260 are adjacent to the IC chip 5290 of the core board 5230 , the via holes 5360 adjacent to the mother board. These via holes are connected to each other through the corresponding plated-through holes 5236 . Thus, on the face side of the core board 5230 of this printed circuit board 5210 , as shown in FIG. 38 (B) which is a sectional view taken along the line B-B of FIG. 38 (A), the land 5236 a of the plated-through hole 5236 is provided with an inner layer pad 5236 b for via-hole connection to the upper layer, while the via hole 5260 is connected to this inner layer pad 5236 b.

[0023] However, with the prior art land configuration illustrated in FIG. 38 (B), the interval between plated-through holes must be large enough to insure a mutual insulation of inner layer pads 5236 b , thus restricting the number of plated-through holes that can be constructed in the core board.

[0024] On the other hand, the package board is formed with a larger number of bumps on the face side than on the reverse side. This is because the wirings from the plurality of bumps on the surface are consolidated and connected to the bumps on the reverse side. For example, the power lines required to be of low resistance compared with signal lines, which number 20, for instance, on the face side (IC chip side) are consolidated into a single line on the reverse side (on mother board side).

[0025] Here, it is preferable that the buildup circuit layer formed on the face side of a core board and the buildup circuit layer on the reverse side may be consolidated at the same pace for the purpose of equalizing the number of upper buildup circuit layers to the number of lower buildup circuit layers, that is to say for minimizing the number of layers. However, as mentioned above, there is a physical restriction to the number of plated-through holes which can be formed in a multilayer core board. Therefore, in the prior art package board, the wirings are consolidated to some extent in the buildup circuit layer on the face side and then connected to the buildup circuit layer on the reverse side through the plated-through holes in the multilayer core board. Since the wiring density has thus been decreased in the buildup circuit layer on the reverse side, it is intrinsically unnecessary to provide the same number of layers on the reverse side as in the buildup circuit layers on the face side. However, the same number of layers has heretofore been used because if there is a difference in the number of layers between the face and reverse sides, warping due to asymmetry would be inevitable. Thus, because of said restriction to the number of plated-through holes which can be provided in the multilayer core board, it is not only necessary to increase the number of layers for the buildup wiring layer on the face side but also necessary to form the buildup circuit layer on the reverse side using the same increased number of layers on the face side.

[0026] Thus, in the prior art multilayered buildup circuit board (package board), the number of built-up layers is increased so that the reliability of connection between the upper and lower layers is low. Moreover, the cost of the package board is increased and the size, thickness and weight of the package board are unnecessarily increased.

[0027] Furthermore, even when the buildup multilayer circuit board is provided only on one side of a core board, provision must be made for a freedom in wiring design for the side opposite to the side formed with the buildup layer.

[0028] Moreover, since the connection between plated-through hole 5236 and via hole 5260 is afforded through an inner layer pad 5236 b as described above, the wiring length within the printed circuit board is increased to sacrifice the signal transmission speed, thus making it difficult to meet the demand for speed-up of IC chips.

SUMMARY OF THE INVENTION

[0029] Developed in the above state of the art, the present invention has for its object to provide an electroplating process which, by utilizing a constant-voltage pulse process is capable of providing with low equipment cost, an electroplated metal of good crystallinity and uniform deposition on substrate.

[0030] It is another object of the present invention to provide an electroless plating solution contributory to reduced plating stresses and consequent protection of the plated metal film against peeling from the inner insulating layer and capable of forming a plated metal film even in fine via holes and an electroless plating process using said plating solution.

[0031] It is still another object of the present invention to provide a process for manufacturing a multilayer printed circuit board having an improved high-frequency characteristic.

[0032] The present invention has for its additional object to provide a process for manufacturing multilayer printed circuit boards which is capable of simultaneous via hole filling and formation of conductor circuit by electroplating without using an expensive equipment.

[0033] It is a further object of the present invention to provide a multilayer printed circuit board contributory to reduction in the number of layers of the buildup structure and a multilayer printed circuit board contributory to reduction in the internal wiring length.

[0034] It is a still further object of the present invention to provide a multilayer buildup circuit board contributory to reduction in the internal wiring length.

[0035] The first invention among inventions belonging to the first group is concerned with an electroplating process comprising electroplating an electrically conductive substrate wherein the electroplating is performed intermittently using said substrate surface as cathode and a plating metal film as anode at constant voltage between said anode and said cathode.

[0036] The second invention among said inventions belonging to the first group is concerned with a process for producing a circuit board comprising a substrate and, as formed thereon, a conductor circuit by electroplating wherein the electroplating is performed intermittently using the electrically conductive conductor circuit-forming surface as cathode and a plating metal as anode at a constant voltage between said anode and said cathode.

[0037] The third invention among said inventions belonging to the first group is concerned with a process for manufacturing a printed circuit board which comprises disposing a resist on electrically conductive layer formed on a substrate, performing electroplating, stripping the resist off and etching said electrically conductive layer to provide a conductor circuit, wherein the electroplating is performed intermittently using said electrically conductive layer as cathode and a plating metal as cathode at a constant voltage between said anode and said cathode.

[0038] The fourth invention among said inventions belonging to the first group is concerned with a process for manufacturing a printed circuit board which comprises disposing an interlayer resin insulating layer on a substrate formed with a conductor circuit, creating openings for formation of via holes in said interlayer resin insulating layer, forming an electroless plated metal layer on said interlayer resin insulating layer, disposing a resist thereon, performing electroplating, stripping the resist off and etching the electroless plated metal layer to provide a conductor circuit and via holes, wherein the electroplating is performed intermittently using said electroless plated metal layer as cathode and a plating metal as anode at a constant voltage between said anode and said cathode.

[0039] The fifth invention among said inventions belonging to the first group is concerned with a circuit board comprising a substrate and, as built thereon, a circuit comprised of a copper film which has properties that (a) its crystallinity is such that the X-ray diffraction half-width of the (331) plane of copper is less than 0.3 deg and (b) the variation in thickness ((maximum thickness-minimum thickness)/average thickness)) of the electroplated copper layer (electroplated metal layer) as measured over the whole surface of said substrate is not greater than 0.4.

[0040] The sixth invention among said inventions belonging to the first group is concerned with a printed circuit board comprising a substrate and, as built thereon, a circuit comprised of a plated copper film wherein said plated copper film has properties that (a) its crystallinity is such that the X-ray diffraction half-width of (331) plane of copper is less than 0.3 deg and (b) the variation in thickness ((maximum thickness-minimum thickness)/average thickness) of said plated copper layer as measured over the whole surface of said substrate is not greater than 0.4.

[0041] The seventh invention among said inventions belonging to the first group is concerned with a printed circuit board comprising a substrate formed with a conductor circuit, an interlayer resin insulating layer built thereon and a conductor circuit comprised of a copper film as built on said interlayer resin insulating layer, said interlayer resin insulating layer having vial holes by which said conductor circuits are interconnected, wherein said copper film has properties that (a) its crystallinity is such that the X-ray diffraction half-width of (331) plane of copper is less than 0.3 deg and (b) the variation in thickness ((maximum thickness-minimum thickness)/average thickness) of said plated copper layer as measured over the whole surface of said substrate is not greater than 0.4.

[0042] As a prior art technology for constructing a conductor circuit by a pulse electroplating method, there is known the PR electrolytic process mentioned hereinbefore but this prior art technology is a plating method using a constant current and not a constant-voltage pulse electroplating process wherein the voltage is controlled.

[0043] The first invention among inventions belonging to a second group is concerned with an electroless plating solution comprising an aqueous solution containing 0.025 to 0.25 mol/L of a basic compound, 0.03 to 0.15 mol/L of a reducing agent, 0.02 to 0.06 mol/L of copper ion and 0.05 to 0.30 mol/L of tartaric acid or a salt thereof.

[0044] The second invention among said inventions belonging to the second group is concerned with an electroless plating solution comprising an aqueous solution containing a basic compound, a reducing agent, copper ion, tartaric acid or a salt thereof and at least one ion species selected from the group consisting of nickel ion, cobalt ion and iron ion.

[0045] The third invention among said inventions belonging to the second group is concerned with an electroless plating process which comprises immersing a substrate in the electroless plating solution according to either said first invention or said second invention and performing electroless copper plating at a deposition rate set to 1 to 2 μm/hour.

[0046] The fourth invention among said inventions belonging to the second group is concerned with a process for manufacturing a printed circuit board which comprises immersing a resin insulating substrate board in the electroless plating solution according to either said first invention or said second invention and performing electroless copper plating at a deposition rate set to 1 to 2 μm/hour to provide a conductor circuit.

[0047] The fifth invention among said inventions belonging to the second group is concerned with a printed circuit board comprising a resin insulating substrate board formed with a roughened surface and, as built thereon, a conductor circuit comprising at least an electroless plated film wherein that said electroless plated film has a stress of 0 to +10 kg/mm 2 .

[0048] The sixth invention among said inventions belonging to the second group is concerned with a printed circuit board comprising a resin insulating substrate board formed with a roughened surface and, as built thereon, a conductor circuit comprising at least an electroless plated film wherein said electroless plated film is complementary to said roughened surface and convex areas of the roughened surface is relatively greater in thickness than said film in concave areas of said roughened surface.

[0049] The seventh invention among said inventions belonging to the second group is concerned with a printed circuit board comprising a substrate board formed with a lower-layer conductor circuit and, as built thereon, an upper-layer conductor circuit through the intermediary of an interlayer resin insulating layer, with said upper-layer conductor circuit and said lower-layer conductor circuit being interconnected by via holes,

[0050] wherein said upper-layer conductor circuit comprises at least an electroless plated film, said interlayer resin insulating layer is provided with a roughened surface, said electroless plated film is complementary to said roughened surface, and bottoms of said via holes are also provided with an electroless plated film having a thickness equal to 50 to 100% of the thickness of the electroless plated film on said interlayer resin insulating layer.

[0051] The eighth invention among said inventions belonging to the second group is concerned with a printed circuit board comprising a resin insulating substrate board and, as built thereon, a conductor circuit comprising at least an electroless plated film, wherein said electroless plated film comprises copper and at least one metal species selected from the group consisting of nickel, iron and cobalt.

[0052] The first invention among inventions belonging to a third group is concerned with a process for manufacturing a multilayer printed circuit board comprising at least the following steps (1) to (5).

[0053] (1) a step for thinning the copper foil of a copper-clad laminate by etching

[0054] (2) a step for piercing through holes in said copper-clad laminate

[0055] (3) a step for depositing a plated metal film on said copper-clad laminate to construct plated-through holes within said through holes

[0056] (4) a step for pattern-etching the copper foil and plated metal film on said copper-clad laminate to construct a conductor circuit

[0057] (5) a step for serially building up an interlayer resin insulating layer and a conductor layer alternately over said conductor circuit.

[0058] The second invention among said inventions belonging to the third group is concerned with a process for manufacturing a multilayer printed circuit board comprising at least the following steps (1) to (7):

[0059] (1) a step for thinning the copper foil of a copper-clad laminate by etching

[0060] (2) a step for piercing through holes in said copper-clad laminate

[0061] (3) a step for forming a conductor film on said copper-clad laminate

[0062] (4) a step of disposing a resist on areas free from conductor circuits and plated-through holes

[0063] (5) a step for providing a plated metal film in the resist-free area to construct a conductor circuit and plated-through holes

[0064] (6) a step for stripping off said resist and etching the conductor film and copper foil under the resist

[0065] (7) a step for serially building up an interlayer resin insulating layer and a conductor layer alternately over said conductor circuit.

[0066] The third invention among inventions belonging to the third group is concerned with a multilayer printed circuit board which comprises a core board having a conductor circuit and, as built over said conductor circuit, a buildup wiring layers comprising obtainable by building up an interlayer resin insulating layer and a conductor layer alternately with the conductor layers being interconnected by via holes, wherein the thickness of the conductor circuit on said core board is not greater by more than 10 μm than the thickness of the conductor layer on said interlayer resin insulating layer.

[0067] The fourth invention among said inventions belonging to the third group is concerned with a process for manufacturing a multilayer printed circuit board which comprises thinning the copper foil of a copper-clad laminate by etching, pattern- etching the copper foil of said copper-clad laminate to construct a conductor circuit and building up serially an interlayer resin insulating layer and a conductor layer alternately over said conductor circuit wherein the thickness of the conductor circuit on said core board is controlled so as to be not greater by more than 10 μm than the thickness of the conductor layer on said interlayer resin insulating layer.

[0068] The invention belonging to a fourth group is concerned with a process for manufacturing a multilayer printed circuit board which comprises constructing an interlayer insulating layer on a substrate formed with a lower-layer conductor circuit, piercing openings in said interlayer insulating layer, imparting electrical conductivity to the surface of said interlayer insulating layer and the inner walls of said openings, performing electroplating to fill up said openings and thereby provide via holes and, at the same time, construct an upper-layer conductor circuit, wherein said electroplating is performed using an aqueous solution containing a metal ion and 0.1 to 1.5 mmol/L of at least one additive selected from the group consisting of thioureas, cyanides and polyalkylene oxides as a plating solution.

[0069] The first invention belonging to a fifth group is concerned with a multilayer printed circuit board comprising a core board having plated-through holes and, as constructed on both sides thereof, a buildup wiring layers obtainable by building up an interlayer resin insulating layer and a conductor layer alternately with said conductor layers being interconnected by via holes, wherein said via holes are formed in the manner of plugging the holes in plated-through holes in said core board.

[0070] The second invention belonging to the fifth group is concerned with a process for manufacturing a multilayer printed circuit board comprising at least the following steps (1) to (4):

[0071] (1) a step for piercing through holes not larger than 200 μm in diameter in a core board by laser

[0072] (2) a step for plating said through holes to construct plated-through holes therein

[0073] (3) a step for constructing an interlayer resin insulating layer provided with openings communicating with said plated-through holes on the core board

[0074] (4) a step for plating the openings in said interlayer resin insulating layer to construct via holes in the manner of plugging the holes in said plated-through holes.

[0075] The first invention among inventions belonging to a sixth group is concerned with a multilayer printed circuit board comprising a core board and, as constructed on both sides thereof, a buildup wiring layers obtainable by building up an interlayer resin insulating layer and a conductor layer alternately with via holes interconnecting conductor layers, wherein the via holes in a lower layer are disposed immediately over the plated-through holes formed in said core board and via holes in an upper layer are disposed immediately over said via holes in the lower layer.

[0076] The second invention among said inventions belonging to the sixth group is concerned with a multilayer printed circuit board comprising a core board having plated-through holes and, as constructed on both sides thereof, a buildup wiring layers obtainable by building up an interlayer resin insulating layer and a conductor layer alternately with via holes interconnecting conductor layers, wherein said plated-through holes of core board are filled with a filler, with the surfaces of said filler which are exposed from said plated-through holes being covered with a conductor layer provided with lower-layer via holes, with upper-layer via holes being disposed immediately over said lower-layer via holes.

[0077] The third invention among said inventions belonging to the sixth group is concerned with a multilayer printed circuit board comprising a core board and, as constructed on both sides thereof, a buildup wiring layers obtainable by building up an interlayer resin insulating layer and a conductor layer alternately with via holes interconnecting conductor layers wherein the via holes in a lower layer are disposed to plug the holes in plated-through holes of said core board, with via holes in an upper layer being disposed immediately over said via holes in the lower layer.

BRIEF DESCRIPTION OF THE DRAWINGS

[0078] FIGS. 1 ( a ) to ( g ) are diagrams illustrating the conductor circuit-fabricating step in the processes for manufacture of printed circuit boards which belong to a first group of the present invention.

[0079] FIGS. 2 ( a ) to ( e ) are diagrams illustrating the printed circuit board-fabricating step in the processes for manufacture of printed circuit boards which belong to the first group of the present invention.

[0080] FIGS. 3 ( a ) to ( b ) are diagrams showing exemplary current and voltage waveforms for the constant-voltage pulse plating process.

[0081] FIG. 4 is a diagram showing the results of evaluation of the deposition uniformity of the electroplated copper layers constructed by four kinds of electroplating techniques, namely the direct-current plating technique, PC plating technique, PR plating technique and constant-voltage pulse plating technique.

[0082] FIG. 5 is a diagram showing the result of X-ray diffraction analysis of the electroplated copper layer formed by the constant-voltage pulse plating technique.

[0083] FIG. 6 is a schematic diagram illustrating the electroplated copper layer formed on an insulating board by the conventional direct-current electrolytic technique.

[0084] FIG. 7 is a schematic diagram illustrating the disadvantage encountered in laminating the printed circuit board prepared by the technique according to FIG. 6 .

[0085] FIGS. 8 ( a ) to ( b ) are diagrams showing exemplary current and voltage waveforms for the PC plating technique.

[0086] FIGS. 9 ( a ) to ( b ) are diagrams showing exemplary current and voltage waveforms for the PR plating technique.

[0087] FIGS. 10 ( a ) to ( b ) are views illustrating the production flow for the manufacture of a CMOS IC.

[0088] FIGS. 11 ( a ) to ( d ) are sectional views showing a part of the process for manufacture of printed circuit boards according to a second group of the present invention.

[0089] FIGS. 12 ( a ) to ( d ) are sectional views showing a part of the process for manufacture of printed circuit boards according to the second group of the present invention.

[0090] FIGS. 13 ( a ) to ( d ) are sectional views showing a part of the process for manufacture of printed circuit boards according to the second group of the present invention.

[0091] FIGS. 14 ( a ) to ( c ) are sectional views showing a part of the process for manufacture of printed circuit boards according to the second group of the present invention.

[0092] FIGS. 15 ( a ) to ( c ) are sectional views showing a part of the process for manufacture of printed circuit boards according to the second group of the present invention.

[0093] FIG. 16 is a partially exaggerated schematic sectional view showing the thickness profile of the electroless plated metal layer formed by the process according to the second group of the present invention.

[0094] FIGS. 17 (A) to (E) are sectional views showing a part of the process for manufacture of multilayer printed circuit boards according to the third group of the present invention.

[0095] FIGS. 18 (F) to (I) are sectional views showing a part of the process for manufacture of multilayer printed circuit boards according to the third group of the present invention.

[0096] FIGS. 19 (J) to (M) are sectional views showing a part of the process for manufacture of multilayer printed circuit boards according to the third group of the present invention.

[0097] FIGS. 20 (N) to (P) are sectional views showing a part of the process for manufacture of multilayer printed circuit boards according to the third group of the present invention.

[0098] FIGS. 21 (Q) to (S) are sectional views showing a part of the process for manufacture of multilayer printed circuit boards according to the third group of the present invention.

[0099] FIGS. 22 (T) to (U) are sectional views showing a part of the process for manufacture of multilayer printed circuit boards according to the third group of the present invention.

[0100] FIGS. 23 is a cross-section view showing a multi-layer printed circuit board according to this invention.

[0101] FIGS. 24 (A) to (F) are sectional views showing a part of the process for manufacture of multilayer printed circuit boards according to the third group of the present invention.

[0102] FIGS. 25 (A) to (E) are sectional views showing a part of the process for manufacture of multilayer printed circuit boards according to the third group of the present invention.

[0103] FIGS. 26 (A) to (E) are sectional views showing a part of the process for manufacture of multilayer printed circuit boards according to the third group of the present invention.

[0104] FIGS. 27 (A) to (E) are cross-section views showing a part of the conventional process for manufacture of multilayer printed circuit boards.

[0105] FIGS. 28 ( a ) to ( d ) are sectional views showing a part of the process for manufacture of multilayer printed circuit boards according to the fourth group of the present invention.

[0106] FIGS. 29 ( a ) to ( d ) are sectional views showing a part of the process for manufacture of multilayer printed circuit boards according to the fourth group of the present invention.

[0107] FIGS. 30 ( a ) to ( d ) are sectional views showing a part of the process for manufacture of multilayer printed circuit boards according to the fourth group of the present invention..

[0108] FIGS. 31 ( a ) to ( c ) are sectional views showing a part of the process for manufacture of multilayer printed circuit boards according to the fourth group of the present invention.

[0109] FIGS. 32 (A) to (E) are cross-section views illustrating a part of the production process for multilayer printed circuit boards according to a fifth group of the present invention.

[0110] FIGS. 33 (F) to (I) are cross-section view showing a part of the production process for the multilayer printed circuit board according to a fifth group of the present invention.

[0111] FIGS. 34 (J) to (M) are cross-section view showing a part of the production process for the multilayer printed circuit board according to the fifth group of the present invention.

[0112] FIGS. 35 (N) to (Q) are cross-section views showing a part of the production process for the multi-layer printed circuit board in accordance with the fifth group of the present invention.

[0113] FIGS. 36 (R) is a cross-section view of the multi-layer printed circuit board according to the fifth group of the present invention and FIG. 36 (S) is a sectional view taken along the line S-S of FIG. 36 (R).

[0114] FIG. 37 is a cross-section view of the multi-layer printed circuit board according to the fifth group of the present invention.

[0115] FIG. 38 (A) is a cross-section view of the conventional multi-layer printed circuit board and FIG. 38 (B) is a sectional view taken along the line B-B of FIG. 38 (A).

[0116] FIGS. 39 (A) to (E) are cross-section views illustrating a part of the production process for multilayer printed circuit boards according to the sixth group of the present invention.

[0117] FIGS. 40 (F) to (J) are cross-section view showing a part of the production process for the multilayer printed circuit board according to the sixth group of the present invention.

[0118] FIGS. 41 (K) to (O) are cross-section view showing a part of the production process for the multilayer printed circuit board according to the sixth group of the present invention.

[0119] FIGS. 42 (P) to (T) are cross-section views showing a part of the production process for the multi-layer printed circuit board according to the sixth group of the present invention.

[0120] FIGS. 43 (U) to (X) are cross-section views showing a part of the production process for the multi-layer printed circuit board according to the sixth group of the present invention.

[0121] FIG. 44 is a cross-section view showing a multi-layer printed circuit board according to the sixth group of the present invention.

[0122] FIG. 45 is a cross-section view showing a multi-layer printed circuit board according to the sixth group of the present invention.

[0123] FIG. 46 is a cross-section view showing a multi-layer printed circuit board according to the sixth group of the present invention.

[0124] FIG. 47 (A) illustrates a structure of the multi-layer printed circuit board according to the sixth group of the present invention and FIG. 47 (B) illustrates a structure of the multi-layer printed circuit board according to the sixth group of the present invention.

[0125] FIG. 48 (B) illustrates an example of a structure of the multi-layer printed circuit board according to the sixth group of the present invention.

[0126] FIG. 49 is a cross-section view showing a multi-layer printed circuit board according to the sixth group of the present invention.

[0127] FIG. 50 is a cross-section view showing a multi-layer printed circuit board according to the sixth group of the present invention.

DETAILED DISCRIPTION OF THE INVENTION

[0128] The present invention is now described in detail. Unless otherwise indicated, the thickness of any copper foil, conductor layer or conductor circuit as mentioned in this specification is the mean of thicknesses measured on a light or electron microphotograph of its cross-section.

[0129] The first invention among the inventions belonging to the first group is concerned with an electroplating process for electroplating a conductive substrate surface wherein said electroplating is performed intermittently using said substrate surface as cathode and a plating metal as anode at a constant voltage between said anode and said cathode.

[0130] The intermittent electroplating in the above electroplating process is carried out by repeating application of a voltage between the cathode and anode and interruption thereof in an alternating pattern, and preferably the voltage time/interruption time ratio is 0.01 to 100, the voltage time is not longer than 10 seconds and the interruption time is not shorter than 1×10 −2 seconds.

[0131] The second invention among the inventions belonging to the first group is concerned with a process for producing a circuit board which comprises forming a conductor circuit on a substrate board by electroplating,

[0132] wherein said electroplating is performed intermittently using the conductive surface on which a conductor circuit is to be formed as cathode and a plating metal as anode at a constant voltage between said anode and said cathode.

[0133] In the above process for producing a circuit board, said intermittent electroplating is carried out by repeating application of a voltage between the cathode and anode and interruption thereof in an alternating pattern, and preferably the voltage time/interruption time ratio is 0.01 to 100, the voltage time is not longer than 10 seconds and the interruption time is not shorter than 1×10 −2 seconds.

[0134] It should be understood that the above circuit comprises electrodes and mounting pads in addition to a conductor circuit pattern.

[0135] The third invention among the inventions belonging to the first group is concerned with a process for producing a printed circuit board which comprises disposing a resist on a conductive layer on a substrate board, performing electroplating, stripping the resist off, and etching said conductive layer to provide a conductor circuit,

[0136] wherein said electroplating is performed intermittently using said conductive layer as cathode and a plating metal as anode at a constant voltage between said anode and said cathode.

[0137] The fourth invention among the inventions belonging to the first group is concerned with a process for producing a printed circuit board which comprises constructing an interlayer resin insulating layer on a conductor circuit-forming substrate board, forming openings for via holes in said interlayer resin insulating layer, forming an electroless plated metal layer over said interlayer resin insulating layer, disposing a resist thereon, performing electroplating, stripping the resist off and etching the electroless plated metal layer to form a conductor circuit pattern and via holes, wherein said electroplating is performed intermittently using said electroless plated metal layer as cathode and a plating metal as anode at a constant voltage between said anode and said cathode.

[0138] In the above process for producing a printed circuit board, a metal layer may have been formed on the surface of the interlayer resin insulating layer.

[0139] The intermittent electroplating in the above third and fourth inventions comprises application of a voltage between the cathode and anode and interruption thereof in an alternating pattern, and preferably the voltage time/interruption time ratio is 0.01 to 100, the voltage time is not longer than 10 seconds and the interruption time is not shorter than 1×10 −2 seconds.

[0140] The fifth invention among the inventions belonging to the first group is concerned with a circuit board having a copper film circuit on a substrate board, wherein said copper film has properties ( a ) its crystallinity is such that the half-width of X-ray diffraction of the (331) plane of copper is less than 0.3 deg. and (b) the variation in thickness of said copper film (electroplated copper layer) measured over the whole surface of said substrate, i.e. ((maximum thickness-minimum thickness)/average thickness), is not greater than 0.4.

[0141] In the circuit board mentioned above, the percent elongation of said copper film as a characteristic parameter is preferably not less than 7%.

[0142] The sixth invention among the inventions belonging to the first group is concerned with a printed circuit board comprising a copper film circuit on a substrate board, wherein said copper film has properties that (a) its crystallinity is such that the half-width of X-ray diffraction of the (331) plane of copper is less than 0.3 deg. and (b) the variation in thickness of plated metal layer measured over the whole surface of said substrate, i.e. ((maximum thickness-minimum thickness)/average thickness), is not greater than 0.4.

[0143] The seventh invention among the inventions belonging to the first group is concerned with a printed circuit board comprising an interlayer resin insulating layer on a substrate board for the formation of a conductor circuit and, as disposed on top of said interlayer resin insulating layer, a copper-film conductor circuit, with via holes provided in said interlayer resin insulating layer interconnecting said conductor circuits,

[0144] wherein said copper film has properties that (a) its crystallinity is such that the half-width of X-ray diffraction of the (331) plane of copper is less than 0.3 deg. and (b) the variation in thickness of said copper film (electroplated copper layer) measured over the whole surface of said substrate, i.e. ((maximum thickness-minimum thickness)/average thickness), is not greater than 0.4.

[0145] The copper film in the above sixth and seventh inventions is preferably further has its percent elongation of not less than 7%.

[0146] The inventions of the first group relate broadly to a technology for fabricating conductor circuits for semiconductor devices and printed circuit boards and an electroplating technology such that intermittent electroplating is performed in a plating metal ion-containing plating solution using the substrate surface as cathode and the plating metal as anode with the voltage between said anode and cathode being kept constant.

[0147] The intermittent electroplating described above insures a uniform plating thickness. The reason seems to be that while the plating metal deposit is preferentially dissolved by the spike current flowing momentarily toward the anode in the marginal area of the substrate board surface and around the openings for via holes where the amount of deposition of the plating metal tends to be larger, the plating metal is precipitated by the spike current flowing momentarily toward the cathode in the central area of the substrate surface and the interior parts of the via holes where the amount of plating metal deposition tends to be smaller as in the remainder of the region, with the result that a highly uniform thickness of electrodeposition is insured.

[0148] Furthermore, intermittent electroplating results in an increased crystallinity of the plated metal film. The reason is suspected to be that as the application of a voltage is interrupted, the metal ions in the neighborhood of the interface of the substrate diffuse to maintain a constant concentration at all times so that no defect occurs in the crystal lattice of the precipitated metal layer, thus contributing to a higher degree of crystallinity.

[0149] By the constant-voltage pulse plating technique in the inventions of the first group, which insures a uniform plate thickness, the thickness of the conductor circuits for circuit boards such as semiconductor devices and printed circuit boards can be rendered uniform. Therefore, not only is impedance alignment facilitated but, because the thickness of the interlayer resin insulating layer is uniform, an improved interlayer insulation is materialized. Furthermore, because of high crystallinity and high elongation characteristics, the residual stress in the plated metal layer is low so that even fine line-definition patterns can be protected against peeling. Therefore, the connection reliability of circuits is improved.

[0150] The above intermittent electroplating process comprises application of a voltage between the cathode and anode and interruption thereof in an alternating pattern, and preferably the voltage time/interruption time ratio is 0.01 to 100, the voltage time is not longer than 10 seconds and the interruption time is not shorter than 1×10 −12 seconds. If the voltage time exceeds 10 seconds, the film thickness will become uneven as it is the case with the conventional direct-current electroplating, and when the interruption time is less than 1×10 −12 seconds, the diffusion of metal ions will be insufficient to detract from crystallinity. The optimum voltage time/interruption time ratio is 0.1 to 1.0.

[0151] The electroplating mentioned above is preferably copper plating, nickel plating, cobalt plating, tin plating or gold plating.

[0152] The copper plating solution is preferably an aqueous solution of sulfuric acid and copper sulfate. The nickel plating solution may for example be an aqueous solution of nickel sulfate, nickel chloride, and boric acid. The cobalt plating solution may be an aqueous solution of cobalt chloride, basic cobalt carbonate and phosphorus acid. The tin plating solution may be an aqueous solution of stannous chloride. For gold plating, an aqueous solution of gold chloride, potassium cyanide and gold metal can be used.

[0153] Since the electroplating bath need not be supplemented with a brightener and other additives, the crystallinity of the plated metal deposit is remarkably high.

[0154] As the plating metal which serves as the anode, the metal in the form of a ball or a rod, for instance, can be used.

[0155] The technology of manufacturing circuit boards in accordance with the inventions belonging to the first group in now described.

[0156] The substrate board which can be used includes metal, semiconductor, resin and ceramic substrates, among others.

[0157] First, the surface of the substrate board is made electrically conductive so that it may be successfully electroplated. The technique for imparting electrical conductivity to a resin substrate or a ceramic substrate comprises forming metal layer by using an electroless plated deposit layer or a sputter-metalized layer. As an alternative, the technique of incorporating a colloidal or powdery metal in the matrix resin can be used.

[0158] On the substrate rendered electrically conductive on the surface, a resist is disposed where necessary. The plating metal adheres to the conductive surface not covered with resist but exposed.

[0159] This substrate is immersed in the electroplating solution and subjected to intermittent electroplating using the substrate as cathode and the plating metal as anode.

[0160] Referring to the inventions of the first group, the production process relevant to cases in which the circuit board is a printed circuit board is now described.

[0161] The substrate which can be used includes insulating substrates such as a resin substrate and a ceramic substrate.

[0162] The resin substrate mentioned above includes an insulating board prepared by laminating prepregs each comprising a fibrous matrix impregnated with a thermosetting resin, a thermoplastic resin or a thermosetting resin-thermoplastic resin complex or a copper-clad laminate board prepared by laying up such prepregs and copper foils and hot-pressing them.

[0163] As the fibrous matrix mentioned above, glass cloth, aramid cloth, etc. can be used.

[0164] An electroless plating catalyst such as a Pd catalyst is applied to the surface of said insulating substrate board to form an electroless plated layer. When a copper-clad laminate board is used, the copper foil as such can be utilized as cathode.

[0165] A plating resist is then disposed thereon. The plating resist can be formed by a process which comprises pasting a photosensitive dry film followed by exposure and development or a process which comprises coating the substrate board with a liquid resist followed by exposure and development.

[0166] The conductor circuit is formed by intermittent electroplating using the conductive layer not covered with resist but exposed, e.g. electroless plated metal layer as cathode and the plating metal as anode.

[0167] Then, the plating resist is stripped off and the conductive layer, e.g. electroless plated metal layer, is etched off with an etching solution to complete the conductor circuit.

[0168] As the etching solution mentioned above, an aqueous system of sulfuric acid-hydrogen peroxide, ferric chloride, cupric chloride or ammonium persulfate, for instance, can be used.

[0169] The following procedure is followed for the production of a multilayer printed circuit board.

[0170] A conductor circuit-forming substrate board is first provided with an interlayer resin insulating layer, which is then formed with openings for via holes. The openings are provided by exposure, development or irradiation with laser light.

[0171] For the interlayer resin insulating layer mentioned above, a thermosetting resin, a thermoplastic resin, a partially photosensitized thermosetting resin, or a complex resin comprising thereof can be used.

[0172] The above interlayer resin insulating layer can be formed by coating with an uncured resin or an uncured resin film by pressure bonding under heating. As an alternative, an uncured resin film carrying a metal layer, e.g. copper foil, on one side can be bonded. When such a resin film is used, the areas of the metal layer which correspond to via holes are etched off, followed by irradiation with a laser beam to provide necessary openings.

[0173] The above resin film formed with a metal layer may for example be a copper foil having resin film.

[0174] As the interlayer resin insulating layer mentioned above, the layer formed of an adhesive for electroless plating use can be used. The optimum adhesive for electroplating use is a dispersion of a cured acid- or oxidizing agent-soluble heat-resistant resin powder in a substantially acid- or oxidizing agent-insoluble uncured heat-resistant resin. This is because upon treatment with an acid or an oxidizing agent, the heat-resistant resin particles are dissolved and removed so that a roughened surface comprising narrow-necked bottle-like anchors can be provided.

[0175] Referring to said adhesive for electroless plating use, the cured heat-resistant resin powder mentioned above, in particular, is preferably {circle over (1)} a heat-resistant resin powder having an average particle diameter of not more than 10 μm, {circle over (2)} a block powder available on aggregation of heat-resistant resin particles having an average particle diameter of not more than 2 μm, {circle over (3)} a mixture of a heat-resistant resin powder having an average particle diameter of 2 to 10 μm and a heat-resistant resin powder having an average particle diameter of not more than 2 μm, {circle over (4)} a pseudo-particle comprising a heat-resistant resin powder having an average particle diameter of 2 to 10 μm and at least one of a heat-resistant resin powder and an inorganic powder each having an average particle diameter of not more than 2 μm as adhered to the surface of the first-mentioned resin powder, {circle over (5)} a mixture of a heat-resistant resin powder having an average particle diameter of 0.1 to 0.8 μm and a heat-resistant resin powder having an average particle diameter of over 0.8 μm to less than 2 μm, or {circle over (6)} a heat-resistant resin powder having an average particle diameter of 0.1 to 1.0 μm is preferred. With any of those materials, the more sophisticated anchors can be provided.

[0176] The depth of the roughened surface structure is preferably Rmax=0.01 to 20 μm. This is preferred for insuring a sufficient degree of adhesion. Particularly in the semi-additive process, the depth of 0.1 to 5 μm is preferred, for the electroless plated metal layer can then be removed without detracting from adhesion.

[0177] The substantially acid- or oxidizing agent-insoluble heat-resistant resin mentioned above is preferably a “complex resin comprising a thermosetting resin and a thermoplastic resin” or a “complex resin comprising a photosensitive resin and a thermoplastic resin”. This is because while the former is highly heat-resistant, the latter is capable of forming openings for via holes by a photolithographic technique.

[0178] The thermosetting resin which can be used as above includes epoxy resin, phenolic resin and polyimide resin. For imparting photosensitivity, the thermosetting groups are acrylated with methacrylic acid or acrylic acid. The optimum resin is an acrylated epoxy resin.

[0179] As the above-mentioned epoxy resin, there can be used novolac epoxy resins such as phenol novolac resin and cresol novolac resin and dicyclopentadiene-modified alicyclic epoxy resin.

[0180] As the thermoplastic resin, there can be used polyethersulfone (PES), polysulfone (PSF), polyphenylenesulfone (PPS), polyphenylene sulfide (PPES), polyphenyl ether (PPE), polyetherimide (PI) and fluororesin.

[0181] The blending ratio of the thermosetting resin (photosensitive resin) to the thermoplastic resin, i.e. thermosetting (photosensitive) resin/thermoplastic resin, is. preferably 95/5 to 50/50. This range contributes to a high level of toughness without compromise in heat resistance.

[0182] The blending weight ratio of said heat-resistant resin powder is preferably 5 to 50 weight % based on the solid matter of the heat-resistant resin matrix. The more preferable ratio is 10 to 40 weight %.

[0183] The heat-resistant resin powder is preferably an amino resin (melamine resin, urea resin, guanamine resin) or an epoxy resin, for instance.

[0184] Further, an electroless plated metal layer is formed over said interlayer resin insulating layer (on the copper foil when a resin-containing copper foil is used) inclusive of surface of openings and after placement of a resist, electroplating is performed to provide a conductor circuit and via holes.

[0185] The electroplating is performed intermittently using said electroless plated metal layer as cathode and the plating metal as anode with the voltage between the anode and cathode being kept constant.

[0186] Then, the resist is stripped off and the electroless plated metal layer is etched off.

[0187] The circuit board and printed circuit board formed by the electroplating process according to the first group of the present inventions, in which the conductor wiring or conductor circuit is made of copper, should satisfy the following conditions (a) and (b).

[0188] Thus, (a) as to crystallinity, the half-width of X-diffraction of the (331) plane of copper is not greater than 0.3 deg, and (b) the variation in plating thickness of the copper layer (electrolated copper layer) as measured all over the surface of said substrate board ((maximum thickness-minimum thickness)/average thickness) is not greater than 0.4.

[0189] When the half-width of X-ray diffraction of the (331) plane of copper is 0.3 deg. or larger, the residual stress will be increased and, in the case of a delicate pattern, there will be a risk for peeling. If the variation ((maximum thickness-minimum thickness)/average thickness) is greater than 0.4, impedance alignment may hardly be obtained.

[0190] The reason for selection of the (331) plane of copper is that this is the plane revealing the most striking change in crystallinity in X-ray diffraction analysis.

[0191] The percent elongation mentioned above for the copper layer is preferably not less than 7%. If the elongation is less than 7%, cracks are liable to develop on cold thermal shock.

[0192] In the inventions of the first group, the purity of copper deposited is as high as 99.8% or more. Therefore, the inherent ductility of copper is fully expressed to provide a high elongation rate.

[0193] The circuit board mentioned above includes printed circuit boards, IC chips and semiconductor devices such as LSI.

[0194] The first invention among inventions belonging to a second group is concerned with an electroless plating solution comprising an aqueous solution containing 0.025 to 0.25 mol/L of a basic compound, 0.03 to 0.15 mol/L of a reducing agent, 0.02 to 0.06 mol/L of copper ion and 0.05 to 0.30 mol/L of tartaric acid or a salt thereof.

[0195] The second invention among inventions of the second group is concerned with an electroless plating solution comprising an alkaline compound, a reducing agent, copper ion, tartaric acid or a salt thereof and at least one metal ion species selected from the group consisting of nickel ion, cobalt ion and iron ion.

[0196] The preferred specific gravity of the electroless plating solutions according to the above first and second inventions is 1.02 to 1.10.

[0197] Furthermore, the preferred temperature of those electroless plating solutions is 25 to 40° C. In addition, the copper deposition rate of those electroless plating solutions is preferably 1 to 2 μm/hour.

[0198] The third invention among inventions of the second group is concerned with an electroless plating process which comprises immersing a substrate in the electroless plating solution of said first or second invention and performing electroless copper plating with the deposition rate set to 1 to 2 μm/hour.

[0199] In the above electroless plating process, said substrate is preferably provided with a roughened surface in advance.

[0200] The fourth invention among inventions of the second group is concerned with a process for manufacturing a printed circuit board comprising immersing a resin insulating substrate board in the electroless plating solution of said first or second invention and performing electroless copper plating with the deposition rate set to 1 to 2 μm/hour to provide a conductor circuit.

[0201] The fifth invention among inventions of the second group is concerned with a printed circuit board comprising a resin insulating substrate board having a roughened surface and, as electroless plated layer thereon, a conductor circuit, wherein said electroless plated layer has a stress value of 0 to +10 kg/mm 2 .

[0202] The sixth invention among inventions of the second group is concerned with a printed circuit board comprising a resin insulating substrate board having a roughened surface and, as an electroless plated layer thereon, a conductor circuit, wherein said electroless plated layer is complementary to said roughened surface and relatively increased in thickness in convex areas of the roughened surface as compared with concave areas of said surface.

[0203] The concave and convex areas mentioned above mean the concave and convex parts of the primary anchor and do not refer to the secondary anchor formed on the convex part thereof or the like (ref. FIG. 16 ).

[0204] The seventh invention among inventions of the second group is concerned with a printed circuit board which comprises a substrate board formed with a lower conductor circuit, an interlayer resin insulating layer thereon and an upper conductor circuit as built up with said lower conductor circuit connected to said upper conductor circuit through via holes, wherein said upper-layer conductor circuit comprises at least an electroless plated metal film, said interlayer resin insulating layer has a roughened surface, said electroless plated metal film is complementary to said roughened surface throughout and the bottom parts of said via holes are also provided with a electroless plated layer in a thickness equal to 50 to 100% of the electroless plated layer formed on said interlayer resin insulating layer.

[0205] The eighth invention among inventions of the second group is concerned with a printed circuit board comprising a resin insulating substrate board and as built thereon a conductor circuit comprising at least an electroless plated metal layer, wherein said electroless plated metal layer comprises copper and at least one metal selected from the group consisting of nickel, iron and cobalt.

[0206] In the printed circuit board according to the above eighth invention of the second group, the preferred content of said at least one metal selected from nickel, iron and cobalt is 0.1 to 0.5 weight %.

[0207] The electroless plating solution according to the first invention among inventions of the second group comprises an aqueous solution containing 0.025 to 0.25 mol/L of a basic compound, 0.03 to 0.15 mol/L of a reducing agent, 0.02 to 0.06 mol/L of copper ion and 0.05 to 0.3 mol/L of tartaric acid or a salt thereof.

[0208] The electroless plating solution according to the second invention among inventions of the second group comprises an aqueous solution containing a basic compound, a reducing agent, copper ion, tartaric acid or a salt thereof and at least one ion species selected from the group consisting of nickel ion, cobalt ion and iron ion.

[0209] Since those electroless plating solutions contain tartaric acid or its salt, the amount of hydrogen uptake in the plating metal deposit is so small that a tensile stress is generated in the plated metal layer. Since its absolute value is small compared with the conventional case (when EDTA is used as a complexing agent) but appropriate, the plated metal layer adheres intimately to the substrate and hardly peels off from the substrate.

[0210] Furthermore, by controlling the proportion of said basic compound within the range of 0.025 to 0.25 mol/L and that of said reducing agent within the range of 0.03 to 0.15 mol/L, the deposition rate of the plating solution can be reduced to 1 to 2 μm/hr. Therefore, when a plating metal is deposited in the openings for via holes, the copper ions are allowed to diffuse far enough down the openings for via holes so that a sufficiently thick plated metal film can be formed even within fine via holes.

[0211] Since the electroless plating solution according to the above second invention of the second group contains at least one metal ion species selected from the group consisting of nickel ion, cobalt ion and iron ion in addition to tartaric acid or a salt thereof, the evolution of hydrogen is suppressed with the result that an appropriate tensile stress is generated in the plated metal layer to insure a good adhesion to the substrate and, hence, exfoliation of the plated metal from the substrate is hard to take place.

[0212] The specific gravity of those electroless plating solutions is preferably adjusted to 1.02 to 1.10. This is because a plating metal can then be precipitated in the fine openings for via holes.

[0213] The preferred temperature of those electroless plating solutions is 25 to 40° C. If the temperature is excessively high, the deposition will be accelerated so much that the plating metal can hardly be deposited within fine openings for via holes. If the temprature is less than 25° C., it takes so much time to deposit the plated metal layer, therefor the temperature is not practical.

[0214] Furthermore, the above electroless plating solutions preferably contain 0.01 to 0.05 weight % of nickel ion, iron ion and/or cobalt ion.

[0215] By setting the concentration of nickel and/or other ion within the above range, the concentration of said at least one metal ion species selected from the group consisting of nickel, iron and cobalt ions can be controlled within the range of 0.1 to 0.5 weight % to thereby provide a plated metal film which is hard enough and shows good adhesion to the resin insulating layer.

[0216] Referring to the electroless plating solution according to the first invention among said inventions of the second group, said basic compound may for example be sodium hydroxide, potassium hydroxide or ammonia.

[0217] The reducing agent mentioned above includes formaldehyde, sodium hypophosphite, NaBH 4 and hydrazine.

[0218] The compound mentioned above as a copper ion includes copper sulfate and copper chloride.

[0219] The above-mentioned salt of tartaric acid includes the corresponding sodium salt and potassium salt and any of those salts may be the salt derived by substituting only one of the available two carboxyl groups with the above-mentioned particular metal or the salt derived by substituting both the carboxyl groups with the above-mentioned metal.

[0220] Referring to the electroless plating solution according to the above second invention of the second group, the compound for providing said nickel ion includes nickel chloride and nickel sulfate; the compound for providing said cobalt ion includes cobalt chloride; and the compound providing for said iron ion includes iron chloride.

[0221] The third invention of the second group is concerned with an electroless plating process which comprises immersing a substrate in said electroless plating solution and performing copper electroless plating at the deposition rate set to 1 to 2 μm/hr as mentioned above.

[0222] The fourth invention of the second group is concerned with a process for manufacturing a printed circuit board which comprises immersing a resin insulating substrate board in said electroless plating solution and performing copper electroless plating by the above-mentioned electroless copper plating process to provide a conductor circuit.

[0223] The resin insulating substrate board mentioned above means not only a resin insulating substrate board not formed with a conductor circuit but a resin insulating substrate board formed with a conductor circuit and, in superimposition, further with an interlayer resin insulating layer having openings for via holes.

[0224] In the above electroless plating process or in the above process for manufacturing a printed circuit board, the surface of resin insulating layer constituting said substrate and the resin insulating substrate is preferably a roughened surface.

[0225] The roughened surface mentioned above comprises concave areas and convex areas and the plating metal is deposited tracing those concave and convex areas but the thickness of the deposit is larger in the convex areas of the roughened surface than in the concave areas thereof and this thickness profile offers the following advantages.

[0226] Thus, in the process generally called the semi-additive process which comprises disposing a plating resist on an electroless plated metal layer, performing electroplating to form a thick plated metal film, stripping off said plating resist and etching the electroless plated metal layer beneath the plating resist, the etching operation is easier when the thichness of the electroless plated metal film is relatively thin in the concave areas as compared with the convex areas and the whole plated metal deposit can be easily removed by this etching without leaving unetched areas, with the result that the insulation reliability of the resulting circuit is very satisfactory.

[0227] The printed circuit board fabricated by the process for manufacturing a printed circuit board according to the fourth invention of the second group has the following characteristics.

[0228] Thus, the printed circuit board according to the fifth invention of the second group comprises a resin insulating substrate board having a roughened surface and as built thereon a conductor circuit comprising at least an electroless plated metal film,

[0229] wherein said electroless plated metal film has a stress value of 0 to +10 kg/mm 2 .

[0230] The sign of the above stress value is positive, i.e. +, which means that a tensile stress has been generated in the above-mentioned plated metal film. This stress can be measured with a spiral stress meter (manufactured by Yamamoto Plating Co., Ltd.).

[0231] Moreover, within the above stress range, the plated metal film does not undergo blistering or peeling so that the connection reliability of the conductor circuits is high.

[0232] The printed circuit board according to the sixth invention of the second group is a printed circuit board comprising a resin insulating substrate board formed with a roughened surface and as built thereon a conductor circuit comprising at least an electroless plated metal film, wherein said electroless plated metal film is complementary to said roughened surface and the thickness of said electroless plated metal film is relatively thick in the convex areas of the roughened surface compared with the concave areas thereof (that is to say, the electroless plated metal film in the concave areas is relatively thin as compared with the convex areas thereof).

[0233] Therefore, when a conductor circuit is to be formed by the semi-additive process mentioned above, the electroless plated metal film in the concave areas of said roughened surface, which is thinner than that in the convex areas, can be more readily and completely stripped off, with the result that the problem of unetched residues is obviated in the etching step and a high inter-conductor insulation dependability is assured.

[0234] The printed circuit board according to the seventh invention of the second group is concerned with a circuit board which comprises a substrate board carrying a lower conductor circuit built thereon, an interlayer resin insulating layer and an upper conductor circuit as built up with said lower conductor circuit and upper conductor circuit being interconnected by via holes,

[0235] wherein said upper conductor circuit comprises at least electroless plated metal film, said interlayer resin insulating layer has a roughened surface, said electroless plated metal film is complementary to said roughened surface, and bottoms of said via holes also carry the electroless plated metal film in a thickness equal to 50 to 100% of the thickness of the electroless plated metal film on said interlayer resin insulating layer.

[0236] The above printed circuit board is fabricated using the above-described electroless plating solution and, therefore, via holes can be provided because, even when the openings for via holes are as fine as 80 μm or less in diameter, a sufficiently thick plated metal film can be formed on the hole bottoms.

[0237] The printed circuit board according to the eighth invention of the second group comprises a resin insulating substrate board and, as built thereon, a conductor circuit comprising at least an electroless plated metal film, wherein said electroless plated metal film comprises copper and at least one metal species selected from the group consisting of nickel, iron and cobalt.

[0238] Here, addition of a salt of such a metal ion inhibits the uptake of hydrogen into the plated metal to reduce the compressive stress of plating so that the resulting film may have an improved adhesion to the resin insulating layer. Furthermore, those metals form alloys with copper to increase the hardness of the plated metal film, thus contributing further to the adhesion to the resin insulating layer.

[0239] An electrodeposition layer which is high in hardness and adhesion to the resin insulating layer can be obtained when the content of said at least one metal species selected from among nickel, iron and cobalt is within the range of 0.1 to 0.5 weight %.

[0240] The technology for manufacture of printed circuit boards according to the inventions of the second group is now described, taking the semi-additive process as an example.

[0241] (1) First, a substrate board carrying an inner-layer copper pattern (lower conductor circuit) on the surface of a core board is constructed.

[0242] Formation of the conductor circuit on the core board can be achieved typically by a process which comprises etching a copper-clad laminate board according to a predetermined pattern, a process which comprises depositing an electroless plating adhesive layer on a glass-epoxy substrate board, polyimide substrate board, ceramic substrate board or metal substrate board, roughening the adhesive layer to impart a roughened surface and performing electroless plating, or a process which comprises performing electroless plating all over said roughened surface, disposing a plating resist, performing electroplating over the areas other than the plating resist areas, stripping off the plating resist and performing etching to provide a conductor circuit comprising the electroplated metal film and the electroless plated metal film (semi-additive process).

[0243] In addition, the surface of the conductor circuit of the above circuit board may be formed with a roughened surface or a roughened layer.

[0244] The roughened surface or roughened layer mentioned above is preferably formed by any of sanding, etching, blackening-reduction, and plating techniques.

[0245] Blackening-reduction, among the above techniques, is preferably carried out by a method using a blackening bath (oxidizing bath) comprising an aqueous solution of NaOH (20 g/l), NaClO 2 (50 g/l) and Na 3 PO 4 (15.0 g/l) and a reducing bath comprising an aqueous solution of NaOH (2.7 g/l) and NaBH 4 (1.0 g/l).

[0246] The preferred procedure for forming a roughened layer by a plating technique comprises performing electroless plating using an electroless plating solution (pH=9) containing copper sulfate (1 to 40 g/l), nickel sulfate (0.1 to 6.0 g/l), citric acid (10 to 20 g/l), sodium hypophosphite (10 to 100 g/l), boric acid (10 to 40 g/l) and a surfactant (Surfinol 465, Nisshin Chemical Industries, Ltd.) (0.01 to 10 g/l) to provide a roughened layer composed of Cu—Ni—P alloy.

[0247] The crystal of the plated metal deposit formed within the above range has an acicular structure which has an excellent anchor effect. This electroless plating bath may contain a complexing agent and various additives in addition to the above compounds.

[0248] The method for providing a roughened layer by etching includes a process which comprises permitting an etching solution containing a cupric complex compound and an organic acid to act upon the surface of the conductor circuit in the presence of oxygen to thereby roughen said surface.

[0249] In this case, etching proceeds according to the chemical reactions represented by the following expression (1) and expression (2).

[0250] 1 embedded image

[0251] (wherein A represents a complexing agent (which functions as a chelating agent) and n represents a coordination number).

[0252] The cupric complex mentioned above is preferably a cupric azole complex. This cupric azole acts as an oxidizing agent which oxidizes metallic copper or the like. The azole may for example be a diazole, a triazole or a tetrazole. Particularly preferred species are imidazole, 2-methylimidazole, 2-ethylimidazole, 2-ethyl-4-methylimidazole, 2-phenylimidazole, 2-undecylimidazole, etc. The cupric azole complex content of said etching solution is preferably 1 to 15 weight %. Within this range, the complex is good in solubility and stability and capable of dissolving even a noble metal, such as Pd, which constitutes the catalyst nucleus.

[0253] To insure dissolution of copper oxide, an organic acid is used in association with the cupric azole complex. The organic acid includes formic acid, acetic acid, propionic acid, butyric acid, valeric acid, caproic acid, acrylic acid, crotonic acid, oxalic acid, malonic acid, succinic acid, glutaric acid, maleic acid, benzoic acid, glycolic acid, lactic acid, malic acid and sulfamic acid. Those acids may be used each independently or in a combination of two or more species.

[0254] The preferred organic acid content of the etching solution is 0.1 to 30 weight %. In this range, the solubility of oxidized copper and the solution stability can be sufficiently insured. As expressed by the above expression (2), the cuprous complex generated is dissolved under the influence of the acid and binds oxygen to form the cupric complex, thus contributing to the oxidation of copper again.

[0255] To assist in the dissolution of copper and the oxidizing action of the azole compound, the etching solution mentioned above may be supplemented with a halide ion, e.g. fluoride ion, chloride ionorbromide ion. The halide ion may also be supplied by adding hydrochloric acid, sodium chloride or the like. The halide ion content of the etching solution is preferably 0.01 to 20 weight %. In this range, a good adhesion can be insured between the roughened surface and the interlayer resin insulating layer.

[0256] In preparing the etching solution, said cupric azole complex and organic acid (where necessary, one having a halide ion is used) are dissolved in water. As said etching solution, a commercial etching solution, for example “Meck Etch Bond”, trade mark, manufactured by Meck Co., Ltd., can be used. The etching amount, when the above etching solution is used, is preferably 0.1 to 10 μm, the optimum range being 1 to 5 μm. If the etching amount exceeds 10 μm, a connection defect occurs between the roughened surface and the via hole conductor. On the other hand, if the etching amount is less than 0.1 μm, the adhesion to the interlayer resin insulating layer to be built thereon will not be sufficiently high.

[0257] The roughened layer or roughened surface may be covered with a layer made of a metal having an ionization tendency greater than copper but not greater than titanium or a noble metal layer (hereinafter referred to as the metal layer). The metal mentioned above includes titanium, aluminum, zinc, iron, indium, thallium, cobalt, nickel, tin, lead and bismuth. The noble metal includes gold, silver, platinum and palladium. Those metal species may be used either independently or in a combination of two or more species to form a plurality of layers.

[0258] Such a metal layer covers the roughened layer and roughens the interlayer resin insulating layer to prevent local electrode reactions and thereby protect the conductor circuit against dissolution. The preferred thickness of such a metal layer is 0.1 to 2 μm.

[0259] Among the metals used to constitute said metal layer, tin is preferred. This is because tin may form a thinner layer on lectroless substituted plated layer faithfully tracing the roughened layer.

[0260] To form a metal layer composed of tin, substitution plating is carried out using a tin borofluoride-thiourea containing solution or a tin chloride-thiourea containing solution. In this case, an Sn layer about 0.1 to 2 μm thick is formed by the Cu—Sn substitution reaction. To form a metal layer composed of a noble metal, sputtering or vapor deposition can be used, for instance.

[0261] The core substrate board may be equipped with plated-through holes so that the wiring layer on the face side and the reverse side may be electrically connected through said plated-through holes.

[0262] Moreover, between the plated-through holes and conduc