BACKGROUND OF THE INVENTION

[0001] The present invention relates to a method for driving a plasma display panel (PDP) and a PDP device. More particularly, the present invention relates to a driving method that improves the display contrast of a PDP.

[0002] FIG. 1 is a diagram showing a basic configuration of a PDP device.

[0003] A plasma display panel (PDP) 1 is a device in which a discharge space sandwiched by two glass substrates filled up with a mixture of neon gas, xenon gas, etc., a discharge is occurred by applying a voltage greater than a discharge start voltage between electrodes formed on the substrate, and phosphors formed on the substrate are excited so that they emit light due to ultraviolet rays generated by the discharge. Although various configurations have been proposed for a PDP, an AC type/three-electrode surface discharge type panel, which is currently most widely used, is described as an example.

[0004] In the plasma display panel (PDP) 1 , a plurality of X electrodes (sustain electrode) 2 and a plurality of Y electrodes (scan electrode) 3 are arranged adjacently by turn and a plurality of address electrodes (third electrodes) 4 are arranged in the direction perpendicular to that in which the X electrodes and the Y electrodes extend. Between a pair of X electrode and Y electrode, that is, between X 1 and Y 1 , between X 2 and Y 2 , . . . , a display line is formed and a display cell 5 is formed at the crossing of each display line and the address electrode 4 . The X electrodes and the Y electrodes are referred to as the display electrodes.

[0005] The X electrodes are commonly connected to an X drive circuit 7 and the same drive signal is applied all to them. The X drive circuit 7 is provided with a sustain pulse circuit 8 that generates a sustain pulse, and a reset/address voltage generation circuit 9 that generates a voltage used during the reset and address operations, both of which will be described later. The Y electrodes are connected individually to a scan circuit 11 provided within a Y drive circuit 10 , and a scan pulse is applied sequentially to them during an address period which will be described later. The Y drive circuit 10 is further provided with a sustain pulse circuit 12 that generates a sustain pulse, and a reset/address voltage generation circuit 13 that generates a reset/address voltage. The address electrodes are connected to an address driver 6 and an address signal to select a cell to be lit or not to be lit is applied to them during the address operation in synchronization with the scan pulse.

[0006] As a discharge in a PDP takes only two values, that is, ON and OFF, gradation is displayed by varying the number of times of light emission. Therefore, one display field that corresponds to a display of a screen is divided into a plurality of subfields. Each subfield is composed of a reset period, an address period and a sustain discharge period (sustain period). During the reset period, the reset operation is performed so that all of the display cells are put into a uniform state in which, for example, wall charges are erased, or wall charges are formed uniformly, regardless of the lit or unlit state of the cells in the previous subfield. During the address period, a selective discharge (address discharge) is caused to occur so that the ON (lit) or OFF (unlit) state of a display cell is determined according to display data and the wall charges in a cell to be lit are put into a state different from that of a cell not to be lit. During the sustain period, a discharge is caused to occur repeatedly in a display cell selected during the address period and light is emitted. If the number of sustain discharge pulses, that is, the period of the sustain discharge pulse, is constant, the length of the sustain discharge period differs from subfield to subfield, therefore gradation can be displayed by setting the ratio of times of light emission in each subfield to, for example, 1:2:4:8: . . . , and combining subfields that are to emit light according to the gradation of each display cell.

[0007] FIG. 3 is a diagram that shows typical examples of drive waveforms in each subfield of a conventional PDP device. As shown schematically, during the reset period, in a state in which 0V is being applied to an address electrode A, an inclined wave-shaped pulse m, the voltage of which varies gradually from 0V to Vs+Vw, is applied to the Y electrode, and an inclined wave-shaped pulse, the voltage of which gradually varies from 0V to −Vs, is applied to the X electrode. Due to this, a discharge is caused to occur in all of the cells regardless of the wall charges accumulated in the display cell, and negative wall charges are accumulated on the Y electrode and the positive charges, on the X electrode. This is called the all-cell write discharge (reset discharge). Subsequently to this, an inclined wave-shaped charge control pulse n, the voltage of which drops gradually from Vs, is applied to the Y electrode and a voltage Vs is applied to the X electrode, therefore, the wall charges accumulated in the Y electrode and X electrode by the write discharge decrease almost to zero. Although a description is given below using an example of an inclined wave-shaped pulse, the voltage of which varies linearly, it is possible for there to be a case where the voltage does not vary linearly.

[0008] During the address period, the voltage Vx is applied to the X electrode and, in a state in which 0V is being applied to the Y electrode, a scan pulse having a voltage −Vs−Vy is applied sequentially to the Y electrode and an address voltage Va is applied to the address electrode A in a cell to be lit in synchronization with the application of the scan pulse. The voltage 0V is applied to the address electrode in a cell not to be lit. An address discharge is caused to occur in a cell to be lit to which the scan pulse and the address voltage have been applied, and positive wall charges are accumulated in the Y electrode and negative charges are accumulated in the X electrode. In this case, the quantities of these wall charges in the Y electrode and X electrode are sufficient to cause a sustain discharge to occur when a sustain discharge pulse is applied. As an address discharge is not caused to occur in a cell not to be lit, the quantities of wall charges in the Y electrode and X electrode are made to remain almost zero.

[0009] During the sustain discharge period, in a state in which 0V is being applied to the address electrode, the voltage Vs and the voltage −Vs are applied alternately to the X electrode and Y electrode as a sustain pulse. The voltage of the sustain pulse to be applied to the Y electrode for the first time is set to Vs+Vu. In a cell to be lit, the voltage due to wall charges is added to the voltage of the sustain pulse, the discharge start voltage is exceeded and a sustain discharge is caused to occur, and the charges move and a quantity of charges necessary for the next sustain discharge are accumulated in the Y electrode and X electrode. In other words, when the address period is completed, positive wall charges are accumulated in the Y electrode and negative wall charges are accumulated in the X electrode, that is, a voltage, the high potential side of which is the Y electrode, is applied between the Y electrode and the X electrode. Therefore, if the voltage Vs+Vu is applied to the Y electrode as a sustain pulse and −Vs is applied to the X electrode at the inception of the sustain period, the voltage due to the above-mentioned wall charges is added so that the discharge start voltage is exceeded, and a sustain discharge is caused to occur. When a sustain discharge is caused to occur, the positive charges move from the Y electrode to the X electrode and accumulate therein, the negative charges move from the X electrode to the Y electrode and accumulate therein, and the sustain discharge is terminated because a voltage, the high potential side of which is the X electrode, is produced by the movement of charges. Then, if −Vs is applied to the Y electrode as a sustain pulse and the voltage Vs is applied to the X electrode, a sustain discharge is caused to occur because the voltage due to the wall charges, the high potential side of which is the x electrode, is added. This cycle is repeated during the sustain period. As no charge is accumulated in a cell not to be lit, no discharge is caused to occur even though a sustain pulse is applied to either electrode.

[0010] Each subfield has a structure as described above, but the length of the sustain period, that is, the number of sustain pulses, differs according to the weights of luminance in each subfield. A desired gradation can be displayed by combining subfields to be lit from among ten subfields.

[0011] FIG. 4 is a diagram that shows an example of gradation display in a conventional PDP device. In this example, one display field is composed of ten subfields SF1-SF10 and each subfield has a luminance ratio as shown schematically. At the head of the one display field, SF1 with the lowest luminance ratio is arranged and following this, the subfields each having each luminance ratio shown schematically are arranged in order. When each gradation level is displayed, subfields to be lit are combined as shown schematically. Although only the gradation levels 0 to 35 are shown here, it is possible to display up to 124 gradation levels in this example. Moreover, in this example, by providing subfields having the same luminance ratio in twos for the four kinds of luminance ratios, it is possible for there to be multiple combinations for the display of the same gradation level. Due to this, a color false contour can be reduced.

[0012] A description has been given of the conventionally typical PDP device as above, but it is possible for there to be various methods for the PDP device. For example, Japanese Unexamined Patent Publication (Kokai) No. 9-160525 has disclosed a PDP device in which the number of display lines is doubled while the number of sustain electrodes remains the same as conventionally, by utilizing all the gaps between neighboring sustain electrodes as a display cell. Although it is possible to apply the present invention to any PDP device as long as it displays gradation using the subfield method, no further description is given here.

[0013] In an AC type PDP device, the quantity or the state of accumulated wall charges in a cell after the sustain period differs between a cell to be lit and one not to be lit. Therefore, there is a problem that the address discharge in the subsequent subfield becomes unstable and it is difficult to ensure a sufficient operation margin. In an AC type PDP device, therefore, the all-cell write discharge (reset discharge) is caused to occur during the reset period in each subfield as described above, and the wall charges in each cell are brought into a uniform state. However, as the all-cell write discharge is caused to occur in all of the cells, even a cell not to be lit is made to light and as a result, a problem occurs that the background luminance becomes high and the contrast ratio is lowered significantly.

[0014] Therefore, there have been proposed various driving methods for improving the contrast ratio.

[0015] Japanese Unexamined Patent Publication (Kokai) No. 2000-75835 has disclosed a driving method for improving the contrast ratio in which the intensity of discharge during the reset period is reduced by using a pulse to be applied to the Y electrode during the reset period, which is wave-shaped and the voltage of which varies gradually.

[0016] Japanese Unexamined Patent Publication (Kokai) No. 5-313598 has disclosed a driving method in which the all-cell write discharge is caused to occur only in the subfield at the head in a display field and the all-cell write discharge is not caused to occur in other subfields. Due to this, the contrast ratio is improved because the number of times the all-cell write discharge is caused to occur is reduced.

[0017] Japanese Unexamined Patent Publication (Kokai) No. 3-219286 has disclosed a driving method in which a preliminary discharge subfield is provided and a preliminary discharge is caused to occur in all of the cells.

[0018] Japanese Unexamined Patent Publication (Kokai) No. 2002-72961 has disclosed a driving method in which a subfield for resetting is provided at the head in a display subfield and a reset discharge is caused to occur in the subfield for resetting for a cell that is to emit light.

[0019] The most effective driving method for improving the contrast ratio among the prior arts is that which has been disclosed in Japanese Unexamined Patent Publication (Kokai) No. 2000-75835, in which a reset discharge (all-cell write discharge) is caused to occur only in the subfield at the head and it is not caused to occur in other subfields. However, this driving method has the following problems.

[0020] (1) When the all-cell write discharge is caused to occur only in the subfield at the head, it is necessary to raise the write voltage to greater than that used in a case where a reset discharge is caused to occur in all of the subfields because the time interval from this discharge until the address discharge is lengthened in subsequent subfields, therefore, the cost of a drive circuit is raised, the amount of increment in the background luminance due to one reset discharge becomes large, and the contrast ratio is not reduced sufficiently.

[0021] (2) In the second and subsequent subfields, wall charges formed by the sustain discharge are formed in a cell that has been lit in the previous subfield but, in an unlit cell, only wall charges formed by the reset discharge in the subfield at the head are formed and, therefore, the states of wall charges are different. Due to this, if an address discharge is caused to occur in these states, a problem occurs that the address discharge becomes unstable in some cells and it is difficult to ensure the operation margin.

[0022] (3) Although an address discharge is caused to occur in each subfield by utilizing the wall charges formed by the reset discharge caused to occur in the subfield at the head, the priming effect diminishes in a cell where an unlit subfield follows another because the time interval, from the formation of the wall charges in the subfield at the head until they are utilized, is lengthened. Therefore, in a cell that is lit for the first time in a subfield near the end, a problem occurs that it is unlikely that the address discharge is caused to occur normally. Moreover, it is necessary to raise the address voltage in order to solve this problem, and as a result, the cost of the drive circuit is increased.

[0023] (4) A sustain discharge exerts influence also on the surrounding unlit cells through the discharge diffusion. Therefore, it is difficult to maintain the wall charges in the unlit cells formed by the reset discharge in the subfield at the head, and the next reset discharge is affected. Therefore, it is necessary to widen the reverse slit by increase the distance between neighboring cells or to design so that a partition (rib) is provided between cells, but this will degrade the display luminance of the panel. Moreover, it is impossible to widen the reverse slit in the case of the ALIS method disclosed in the above-mentioned Japanese Unexamined Paten Publication (Kokai) No. 9-160525, in which all of the spaces between sustain electrodes are used as a cell.

[0024] Because of the above-mentioned problems, it is, therefore, difficult to apply the driving method, in which a reset discharge is caused to occur only in the subfield at the head, to a high-resolution PDP device in which the reverse slit cannot be widened. Moreover, a PDP device having a box rib structure is free from the above-mentioned problems (3) and (4), but it is necessary to raise the write voltage because cells are enclosed by ribs and completely separate from each other, therefore, the cost of the drive circuit is increased.

SUMMARY OF THE INVENTION

[0025] The object of the present invention is to realize a driving method able to realize a high-contrast PDP device that is free from the above-mentioned problems.

[0026] In order to realize the above-mentioned object, the method for driving a plasma display panel according to the present invention is characterized in that cells to be lit are separated from cells not to be lit in a display field and all of the cells to be lit are lit in a predetermined subfield arranged at a position near the head in the display field. The gradation level is set with the light emission in the predetermined subfield being taken into consideration.

[0027] FIG. 5 is a diagram that illustrates the principle of the present invention. It is assumed that subfields SF1, SF2, SF3, SF4, . . . , are arranged in this order in a display field. Conventionally, each subfield is combined to display a predetermined gradation level, and in some cases, a cell that is not lit in the subfield SF1 at the head is lit in a subsequent subfield. Contrary to this, in the configuration according to the present invention, whenever there is a subfield to be lit in a display field, it is always lit in the subfield SF1 at the head. A reset discharge is caused to occur only in a predetermined subfield and not in other subfields, but it is possible for there to be a modification such as that a reset discharge is caused to occur in a subfield with a large luminance ratio, as will be described later. Due to this, the contrast ratio can be improved similar to the conventional case where a reset discharge is caused to occur only in the subfield at the head and the following advantages can be expected.

[0028] (1) As the wall charges formed by a sustain discharge are more stable than those formed by a reset discharge (write discharge), the above-mentioned problems relating to the prior art do not occur. For example, when a cell is lit in a subfield after the predetermined subfield, a high write voltage (reset voltage) is not required because a cell in which an address discharge is caused to occur uses the wall charges formed by a sustain discharge.

[0029] In the conventional case shown in FIG. 5 , for example, the cell in the fourth row and second column is lit in SF4 for the first time. Therefore, the wall charges formed by the reset discharge in SF1 are used. Contrary to this, in the present invention, the cell in the fourth row and second column has been lit in SF1 and when it is lit in SF4, the wall charges formed by the sustain discharge are used.

[0030] (2) Because the lit cells are completely separated from the unlit cells in a display field, it is possible to bring wall charges into a desired state, individually, by a proper process and to ensure an operation margin for a stable operation.

[0031] (3) Both the priming effects of the write discharge (reset discharge) and the sustain discharge can be used.

[0032] As described above, the method for driving a plasma display panel according to the present invention can improve the contrast ratio as the conventional driving method can do and at the same time, it can solve the problems relating to the prior art.

[0033] A fixed subfield is, for example, a subfield with the lowest luminance ratio, and in this case, the predetermined subfield is arranged at the head. It is also possible to arrange a subfield with the lowest luminance ratio at the head and a subfield with the second lowest luminance ratio at the second position, and use the second subfield as a fixed subfield, and thus there can be various modifications.

[0034] It is desirable to provide, in addition to a predetermined subfield, a subfield having the same luminance ratio as the predetermined subfield in a display field. Due to this, if, for example, the subfield with the lowest luminance ratio is the predetermined subfield, it is possible to display any gradation level by combining the subfields which light the predetermined subfield.

[0035] In the predetermined subfield, it is desirable to provide a reset period, during which the all-cell write discharge is caused to occur, before an address period. It is also desirable to provide a reset period, during which the all-cell write discharge is caused to occur, before an address period, not only in the predetermined subfield but also in a subfield with a heavy weight of luminance. Moreover, when the predetermined subfield is arranged at the second position, it is desirable to provide a reset period in the subfield at the head with the lowest luminance ratio. It is not necessary to provide a reset period in other subfields. During the reset period, the all-cell write discharge can be caused to occur twice or more successively.

[0036] It is desirable to cause a subfield reset discharge to occur to erase the residual charges in a lit cell in a subfield immediately before a subfield having a reset period.

[0037] In the predetermined subfield, it is desirable to widen the width of the address pulse in the address period so that the width is wider than that of the address pulse in other subfields, to raise the voltage of the address pulse so that the voltage is greater than that of the address pulse in other subfields, or to raise the voltage of the scan pulse so that the voltage is greater than that of the scan pulse in other subfields.

[0038] Moreover, in the predetermined subfield, it is desirable to perform a process to suppress the discharge in an unlit cell between the address period and the sustain period. This process is, for example, a process in which an address pulse is applied to the address electrode and at the same time, an inclined wave-shaped pulse is applied to the scan electrode. In this case, the final potential of the inclined wave-shaped pulse is set so as to be lower than the finally reached potential of an inclined wave-shaped charge control pulse during the reset period.