Title:

Semiconductor multi-package module having inverted bump chip carrier second package

Document Type and Number:

United States Patent Application 20040119152

Kind Code:

Abstract:

A semiconductor multi-package module has stacked lower and upper packages, each of which includes a die attached to a substrate, in which the second package is inverted, in which the upper and lower substrates are interconnected by wire bonding, and in which the inverted second package comprises a bump chip carrier package. Also, a method for making a semiconductor multi-package module, by providing a lower molded package including a lower substrate and a die, affixing an upper bump chip carrier package including an upper substrate in inverted orientation onto the upper surface of the lower package, and forming z-interconnects between the upper and lower substrates.

Inventors:

Karnezos, Marcos (Palo Alto, CA, US)
Carson, Flynn (Redwood City, CA, US)

Plaque It!

What is claimed is:

1. A multi-package module comprising stacked lower and upper packages, each said package including a die attached to a substrate, wherein the second package is inverted, wherein the upper and lower substrates are interconnected by wire bonding, and wherein the inverted second package comprises a bump chip carrier package.

2. The multi-package module of claim 1 wherein the lower package comprises a ball grid array package.

3. The multi-package module of claim 1 wherein the lower package comprises a die-down flip chip package.

4. The multi-package module of claim 1 wherein the lower package comprises a die-up flip chip package.

5. The multi-package module of claim 1 wherein the upper package includes an additional die stacked on the bump chip carrier package.

6. The multi-package module of claim 1 wherein the upper package comprises a stacked die package.

7. The multi-package module of claim 5 wherein adjacent stacked die in the stacked die package are separated by a spacer.

8. The multi-package module of claim 1, further comprising a heat spreader over the second package.

9. A method for making a multi-package module, comprising providing a stacked die first package, providing a bump chip carrier second package, inverting the second package and stacking the second package over the first package, and forming electrical interconnects between the first package and the second package by wire bonding.

10. The method of claim 9 wherein providing a stacked die first package comprises testing stacked die packages for a performance and reliability requirement, and identifying a package that meets the requirement as a said first package.

11. The method of claim 9 wherein providing a second package comprises testing packages for a performance and reliability requirement, and identifying a package that meets the requirement as a said second package.

12. The method of claim 9, further comprising providing a heat spreader.

13. The method of claim 9, further comprising attaching second-level interconnect balls onto the first package substrate.

14. The method of claim 9, further comprising encapsulating the stacked packages on the module in a molding compound.

15. A mobile device comprising the multi-package module of claim 1.

16. A computer comprising the multi-package module of claim 1.

Description:

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Provisional Application No. 60/417,277, filed Oct. 8, 2002, titled “Semiconductor multi-package module having inverted second package”, which is hereby incorporated herein by reference. This application also claims the benefit of U.S. Provisional Application No. 60/460,541, filed 4 Apr. 2003, and of U.S. application Ser. No. 10/618,933, filed 14 Jul. 2003, both titled “Semiconductor multipackage module including processor and memory package assemblies”, which are hereby incorporated herein by reference.

[0002] This application is related to U.S. application Ser. No. ______ (Atty Docket No. CPAC 1029-2), titled “Semiconductor stacked multi-package module having inverted second package”; U.S. application Ser. No. ______ (Atty Docket No. CPAC 1029-3), titled “Semiconductor multi-package module having inverted land grid array (LGA) package stacked over ball grid array (BGA) package”; U.S. application Ser. No. ______ (Atty Docket No. CPAC 1029-4), titled “Semiconductor stacked multi-package module having inverted second package and electrically shielded first package”; U.S. application Ser. No. ______ (Atty Docket No. CPAC 1029-5), titled “Semiconductor multi-package module having inverted second package stacked over die-down flip-chip ball grid array (BGA) package”; U.S. application Ser. No. ______ (Atty Docket No. CPAC 1029-6), titled “Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA) package”; U.S. application Ser. No. ______ (Atty Docket No. CPAC 1029-7), titled “Semiconductor multi-package module having inverted second package and including additional die or stacked package on second package”; all filed 8 Oct. 2003, and each of which is hereby incorporated by reference.

BACKGROUND

[0003] This invention relates to semiconductor packaging.

[0004] Portable electronic products such as mobile phones, mobile computing, and various consumer products require higher semiconductor functionality and performance in a limited footprint and minimal thickness and weight at the lowest cost. This has driven the industry to increase integration on the individual semiconductor chips.

[0005] More recently the industry has begun implementing integration on the “z-axis,” that is, by stacking chips, and stacks of up to five chips in one package have been used. This provides a dense chip structure having the footprint of a one-chip package, in the range of 5×5 mm to 40×40 mm, and obtaining thicknesses that have been continuously decreasing from 2.3 mm to 0.5 mm. The cost of a stacked die package is only incrementally higher than the cost of a single die package and the assembly yields are high enough to assure a competitive final cost as compared to packaging the die in individual packages.

[0006] The primary practical limitation to the number of chips that can be stacked in a stacked die package is the low final test yield of the stacked-die package. It is inevitable that some of the die in the package will be defective to some extent, and therefore the final package test yield will be the product of the individual die test yields, each of which is always less than 100%. This can be particularly a problem even if only two die are stacked in a package but one of them has low yield because of design complexity or technology.

[0007] Another limitation is the low power dissipation of the package. The heat is transmitted from one die to the other and there is no significant dissipation path other than through the solder ball to the motherboard.

[0008] A further limitation is electromagnetic interference between the stacked die, particularly between RF and digital die, because there is no electrical shielding of either die.

[0009] Another approach to integrating on the “z-axis” is to stack die packages to form a multi-package module. Stacked packages can provide numerous advantages as compared to stacked-die packages.

[0010] For instance, each package with its die can be electrically tested, and rejected unless it shows satisfactory performance, before the packages are stacked. As a result the final stacked multi-package module yields are maximized.

[0011] More efficient cooling can be provided in stacked packages, by inserting a heat spreader between the packages in the stack as well as at the top of the module.

[0012] Package stacking allows electromagnetic shielding of the RF die and avoids interference with other die in the module.

[0013] Each die or more than one die can be packaged in a respective package in the stack using the most efficient first level interconnect technology for the chip type and configuration, such as wire bonding or flip chip, to maximize performance and minimize cost.

[0014] The z-interconnect between packages in a stacked multi-package module is a critical technology from the standpoint of manufacturability, design flexibility and cost. Z-interconnects that have been proposed include peripheral solder ball connection, and flexible substrate folded over the top of the bottom package. The use of peripheral solder balls for z-interconnects in stacked multi-package modules limits the number of connections that can be made and limits design flexibility, and results in a thicker and higher cost package. Although the use of a flexible folding substrate provides in principle for design flexibility, there is no established manufacturing infrastructure for the folding process. Moreover, the use of a flexible folding substrate requires a two metal layer flex substrate, and these are expensive. Furthermore the folded flexible substrate approach is restricted to low pincount applications because of limits in routing the circuitry in two metal layer substrates.

[0015] The various z-interconnect structures are described in further detail with reference to FIGS. 1A, 1B and 2-4.

[0016] FIG. 1A is a diagrammatic sketch in a sectional view illustrating the structure of a standard Ball Grid Array (“BGA”) package, well established in the industry, that can be used as a bottom package in a stacked multi-package module (“MPM”). The BGA, shown generally at 10, includes a die 14 attached onto a substrate 12 having at least one metal layer. Any of various substrate types may be used, including for example: a laminate with 2-6 metal layers, or a build up substrate with 4-8 metal layers, or a flexible polyimide tape with 1-2 metal layers, or a ceramic multilayer substrate. The substrate 12 shown by way of example in FIG. 1A has two metal layers 121, 123, each patterned to provide appropriate circuitry and connected by way of vias 122. The die is conventionally attached to a surface of the substrate using an adhesive, typically referred to as the die attach epoxy, shown at 13 in FIG. 1A and, in the configuration in FIG. 1A, the surface of the substrate onto which the die is attached may be referred to as the “upper” surface, and the metal layer on that surface may be referred to as the “upper” metal layer, although the die attach surface need not have any particular orientation in use.

[0017] In the BGA of FIG. 1A the die is wire bonded onto wire bond sites on the upper metal layer of the substrate to establish electrical connections. The die 14 and the wire bonds 16 are encapsulated with a molding compound 17 that provides protection from ambient and from mechanical stress to facilitate handling operations, and provides a surface for marking for identification. Solder balls 18 are reflowed onto bonding pads on the lower metal layer of the substrate to provide interconnection to the motherboard (not shown in the FIGS.) of a final product, such as a computer. Solder masks 125, 127 are patterned over the metal layers 121, 123 to expose the underlying metal at bonding sites for electrical connection, for example the wire bond sites and bonding pads for bonding the wire bonds 16 and solder balls 18.

[0018] FIG. 1B is a diagrammatic sketch in a sectional view illustrating the structure of a BGA, generally similar to the BGA shown in FIG. 1A, except that here the molding 117 completely covers the substrate as well as the die and wire bonds. The molding configuration of FIG. 1B is formed by applying the molding compound over an array of a number of BGAs, curing the molding, and then separating the encapsulated packages, for example by saw singulation. Typically the molding in such a package has vertical walls at the edges of the package. In such a package, unlike a BGA as in FIG. 1A, no marginal portion of the upper surface of the substrate 12 is exposed and, accordingly, no electrical traces are exposed on the upper surface of the substrate. Many smaller packages currently are saw-singulated packages, often referred to as “chip scale packages.”

[0019] FIG. 2 is a diagrammatic sketch in a sectional view illustrating the structure of an example of a 2-stack MPM, generally at 20, in which the z-interconnect is made by way of solder balls. In this MPM a first package (which may be referred to as the “bottom” package) is similar to a standard BGA as shown in FIG. 1A (and similar reference numerals are employed to point to similar features of the bottom package in FIGS. 1A and 2). A second package (which may be referred to as the “top” package) is stacked on the bottom package and is similar in structure to the package of FIG. 1B (and similar reference numerals are employed to point to similar features of the top package in FIGS. 1B and 2), except that the solder balls in the top package are arranged at the periphery of the top package substrate, so that they effect the z-interconnect without interference with the encapsulation of the bottom BGA. Particularly, the top package in FIG. 2 includes a die 24 attached onto a substrate 22 having at least one metal layer. The top package substrate 22 shown by way of example in FIG. 2 has two metal layers 221, 223, each patterned to provide appropriate circuitry and connected by way of vias 222. The die is conventionally attached to a surface of the substrate (the “upper” surface) using an adhesive, typically referred to as the die attach epoxy, shown at 23 in FIG. 2.

[0020] In the top package in the MPM of FIG. 2, as in the bottom package, the die is wire bonded onto wire bond sites on the upper metal layer of the substrate to establish electrical connections. The top package die 24 and wire bonds 26 are encapsulated with a top package molding compound 27. Solder balls 28 are reflowed onto bonding pads located on the peripheral margin of the lower metal layer of the top package substrate to provide z-interconnection to the bottom package. Solder masks 225, 227 are patterned over the metal layers 221, 223 to expose the underlying metal at bonding sites for electrical connection, for example the wire bond sites and bonding pads for bonding the wire bonds 26 and solder balls 28.

[0021] The z-interconnection in the MPM of FIG. 2 is achieved by reflowing the solder balls 28 attached to peripheral bonding pads on the lower metal layer of the top package substrate onto peripheral bonding pads on the upper metal layer of the bottom BGA. This type of z-interconnect requires that the upper and lower substrates be designed with matching pads for the interconnect balls. If one of the packages is exchanged for one in which the substrate has a different pad arrangement (different size or different design), then the substrate for the other package must be reconfigured accordingly. This leads to increased cost for manufacture of the MPM. In this configuration the distance h between the top and bottom packages must be at least as great as the encapsulation height of the bottom package, which may be 0.25 mm or more, and typically is in a range between 0.5 mm and 1.5 mm. The solder balls 28 must accordingly be of a sufficiently large diameter that when they are reflowed they make good contact with the bonding pads of the bottom BGA; that is, the solder ball 28 diameter must be greater than the encapsulation height. A larger ball diameter dictates a larger ball pitch that in turn limits the number of balls that can be fitted in the available space. Furthermore the peripheral arrangement of the solder balls forces the bottom BGA to be significantly larger than the mold cap of a standard BGA. Furthermore the peripheral arrangement of the solder balls increases the overall package size (the size increases according to the number of ball rows and the ball pitch). In small BGAs, usually referred to as Chip Scale Packages (“CSP”), the package body size is 1.7 mm larger than the die. In standard BGAs the body size can be as much as about 2-3 mm larger than the mold cap. Moreover, the top package in such a configuration must be made of comparable size to the bottom one even though it may contain a small chip with many fewer interconnects. In this configuration the top package substrate must have at least 2 metal layers to facilitate the electrical connections.

[0022] FIG. 3 is a diagrammatic sketch in a sectional view illustrating the structure of an example of a known 2-stack flip chip MPM, shown generally at 30. In this configuration the bottom BGA flip chip package includes a substrate 32 having a patterned metal layer 31 onto which the die 34 is connected by flip chip bumps 36, such as solder bumps, gold stud bumps or anisotropically conducting film or paste. The flip chip bumps are affixed to a patterned array of bump pads on the active surface of the die and, as the active surface of the die faces downward in relation to an upward-facing patterned metal layer of the substrate, such an arrangement may be referred to as a “die down” flip chip package. A polymer underfill 33 between die and substrate provides protection from ambient and adds mechanical integrity to the structure. Such a flip chip package, in which the substrate has a metal layer on only the upper surface, is connected to the underlying circuitry (such as a motherboard, not shown in the FIG.) by solder balls 38 connected to the metal layer through solder vias 35.

[0023] The top BGA in this configuration is similar to the bottom BGA, except that the top BGA has z-interconnect solder balls 338 connected (through solder vias 335 in the top substrate) to the metal layer 331 only at the periphery of the top substrate. Solder balls 338 are reflowed onto the metal layer 31 of the bottom substrate to provide the z-interconnect. Particularly, the top BGA in this configuration includes a substrate 332 having a patterned metal layer 331 onto which the top BGA die 334 is connected by flip chip bumps 336. Between the top BGA die and substrate is a polymer underfill 333. A structure as in FIG. 3 is more appropriate for high electrical performance applications, but it has similar limitations to configurations of the type shown in of FIG. 2. It presents an improvement over the FIG. 2 configuration in that the bottom BGA has no molding, allowing for use of smaller diameter (h) solder balls at the periphery of the top BGA for connection between the packages.

[0024] Particularly, this structure is more appropriate, for example, for modules containing stacks of identical memory chips having the same connections at the same locations to facilitate the z-interconnect. It is not appropriate for stacking packages that have different chips with connection points not located over one another in the stack. As in the configuration of FIG. 2, the peripheral arrangement of solder balls limits the number of interconnects. Moreover, the packages must necessarily be of comparable size, and where the chip in one package is smaller than that in the other, the package having the smaller chip will be forced to a larger size, imposing a higher cost.

[0025] FIG. 4 is a diagrammatic sketch in a sectional view illustrating the structure of an example of a known 2-stack folded flexible substrate MPM, shown generally at 40. The bottom package in the configuration of FIG. 4 has a 2-metal layer flexible substrate onto which the die is bonded via small beams to the first metal layer of the substrate. The second metal layer of the bottom package substrate carries the solder balls for connection to the underlying circuitry, such as a motherboard (not shown). The substrate is large enough to be folded over the top of the package, thus bringing the electrical interconnect lines upward where they are available for connection to the top package (an example of which is described below) by way of an array of solder balls on the top package. The space around the die and between the die and folded-over substrate is encapsulated to provide protection and rigidity.

[0026] Referring to FIG. 4, the two-metal layer bottom package substrate 42 includes a first metal layer 141 and a second metal layer 143, each patterned to provide appropriate circuitry and connected by way of vias 142. A part of the first metal layer, over a part of the bottom substrate, is processed (for example, using an array of punches) to present an array of cantilever beams or tabs 46 arranged to correspond to an array of interconnect pads on the active surface of the bottom package die 44. Over this part of the substrate 42, which may be referred to as the “die attach part”, the first metal layer 141 faces upwardly. The die is aligned, active surface downward, over the die attach part of the substrate, and the cantilevers and the corresponding interconnect pads are joined, typically for example by a “thermosonic” process employing a combination of pressure, heat, and ultrasonic energy to complete the electrical connections. The die 44 is affixed using an adhesive 43, typically a die attach epoxy, onto the die attach part of the flexible substrate 42. A second metal layer 143 of the bottom package substrate 42 faces downwardly in the die attach part of the substrate. Solder balls 48 are reflowed onto bonding pads located on an array on the downward-facing part of the second metal layer 143 to provide for interconnection of the MPM to underlying circuitry (not shown). A solder mask 147 is patterned over the second metal layer 143 to expose the underlying metal as bonding sites for electrical connection, including the bond pads for connection with the underlying circuitry by way of solder balls 48, and the bond pads for connection with the top package by way of solder balls 18, as described below.

[0027] Another part of the bottom package substrate 42, extending adjacent the die-attach portion, is folded up and over the bottom package die 44. On this folded-over portion of the flexible substrate 42 the first metal layer 143 faces upwardly. In the configuration of FIG. 4 the top package is generally similar to the BGA of FIG. 1, in which the die is wire bonded onto wire bond sites on the upper metal layer of the substrate to establish electrical connections. Particularly, the top package die 14 is attached onto a substrate 12 having (in this example) two metal layers 121, 123, each patterned to provide appropriate circuitry and connected by way of vias 122. The die is conventionally attached to the upper surface of the top package substrate using an adhesive 13, typically a die attach epoxy. The die 14 and the wire bonds 16 are encapsulated with a molding compound 17 that provides protection from ambient and from mechanical stress to facilitate handling operations, and provides a surface for marking for identification. Solder balls 18 are reflowed onto bonding pads 143 on the upward-facing metal layer of the folded-over bottom package substrate to provide z-interconnection between the top and the bottom packages.

[0028] An advantage of a structure as in FIG. 4 is that the folded-over substrate provides sufficient area on the upward-facing surface of the folded-over bottom package substrate to accommodate a full array of solder balls in the top package and to accommodate more complex interconnect between the two packages. It also provides for a small package footprint. A primary disadvantage of this configuration is the high cost of the substrate and the unavailability of folding technology and equipment.

[0029] A lack of folding technology and equipment makes manufacture of the 2-stack folded flexible substrate MPM configuration more complex and more costly. The two substrates must be designed such that the pads match for the interconnect balls. If one of the packages is exchanged for one in which the substrate has a different pad arrangement (different size or different design), then the substrate for the other package must be reconfigured accordingly. This leads to increased cost for manufacture of the MPM. Moreover, all the interconnects from the top to the bottom package must be routed through the folded portion of the flex substrate at one edge of the package. This increases the routing density and increases the length of the routing traces, resulting in higher inductance and lower electrical performance of the MPM.

[0030] A common feature of all these stacked package configurations is that they enable pretesting of each package, and provide for production MPMs with higher final test yields.

SUMMARY

[0031] This invention is directed to multi-package modules. According to the invention, z-interconnection between the stacked packages in the MPM is wire bond based, and an upper package is inverted. Generally, the invention features various configurations of various stacked packages, including a bottom (lower) package and at least one inverted top (upper) package, and methods for stacking and interconnecting the various packages by wire-bonding based z-interconnection.

[0032] In the multi-package module according to the invention the package stack can include any of a variety of BGA and/or any of a variety of Land Grid Array (“LGA”) packages and/or any of a variety of bump chip carrier packages; the package stack can include wire bonded and/or flip chip packages; the package stack can include a thermal enhancement feature enabled by one or more heat spreaders in or on the stack; the package stack can include one or more packages having a flip chip bonded die bonded either to the top or to the bottom of the BGA or LGA; the package stack can include one or more BGA and/or LGA having more than one die in the package stacked or side by side; the stack can include electromagnetic shield for one or more of the packages; and the stack can include any substrate, laminate or build-up or flexible or ceramic, provided that the z-interconnect pads are made available for bonding on the periphery of the packages.

[0033] In one general aspect the invention features a multi-package module having stacked lower and upper packages, each package including a die attached to a substrate, in which the upper package is inverted and the upper and lower substrates are interconnected by wire bonding.

[0034] The invention provides for excellent manufacturability, high design flexibility, and low cost to produce a stacked package module having a low profile and a small footprint. The wire bond z-interconnect is well established in the industry; it is the lowest cost interconnect technique and it is directly applicable, without significant modification, to the stacked multi-package modules of the invention. It provides design flexibility to the relative size of the BGA to LGA that can be bridged by wire length. Using available techniques and equipment the wire in a wire bond can be as short as 0.5 mm or as long as 5 mm. The arrangement of the z-interconnect pads can be implemented through either or both BGA and LGA substrate designs. Moreover, using wire bonds according to the invention z-interconnect can be formed between pads that are not precisely aligned over one another, by employing so-called “out of sequence bonding” that is in current use in the industry. The wire bonding pitch is the finest available technology in the industry at 50 microns currently, and projected to go to 25 microns. This is finer than any other interconnect including flip chip (around 200 microns) or solder balls (at about 500 microns), and therefore provides for more interconnects between packages (z-interconnects) in the same available space.

[0035] Wire bonding using a wire bonding machine provides design flexibility for interconnecting pads, because the connections are programmed in the wire bonder, avoiding the need for hard tooling substrates to match each other and connect with solder balls. When the relative BGA and LGA package sizes change, the wire bonding can be reconfigured to accommodate the differences by program changes. If the top package must be smaller than the bottom, wire bonding can accommodate size differences at least up to 9 mm. This allows for use of the smallest package needed to accommodate the chip size, and thus optimizes the total cost of the MPM.

[0036] Wire bonding can interconnect pads that are “out of sequence,” that is, not situated in the desired order and not precisely above each other in either package, so long as they are not too far apart. Where necessary, the pads can be appropriately routed to a location close enough for wire bonding. This flexibility allows stacking of packages that do not have the “desired” order or location of interconnect pads. As the chip technology advances usually the chip size shrinks and design variants are developed with either more connections or some connections with different order. The bonding flexibility provided by wire bonding allows the user to maintain the same package size but vary the substrate design. This results in lower cost and faster time to market, both critical for new products.

[0037] The BGAs and LGAs, including chip scale packages, are standard in the industry, providing the lowest cost and the widest availability. This provides significant flexibility in selecting the packages to be stacked and, therefore, in the kinds of functions that can be integrated into the MPM.

[0038] A typical BGA thickness is 1.0 mm and LGA thickness is 0.8 mm. The stacking of an inverted LGA on top of a BGA according to the invention can be completed using an adhesive having a finished thickness in the range 10-50 microns. This structure provides for a lower profile MPM compared to conventional constructs that employ solder balls for the z-interconnect. The footprint of the MPM according to the invention is determined by the maximum chip size of the stack. A typical minimum footprint for the BGA or LGA is 1.7 mm larger than the die size. The wire bond z-interconnect generally requires that the top LGA be minimally smaller than the bottom BGA, by about 0.1 mm to 0.8 mm, to accommodate the wires without shorting to the substrate metal edges. If the top package must be significantly smaller than the bottom package, wire bonding can accommodate size differences at least up to 9 mm. This allows for minimizing the size of the package needed to accommodate the chip size, and thus for optimizing the total cost of the MPM. Both the footprint and the thickness of the stacked package MPM according to the invention fall within accepted ranges for most applications.

[0039] In some embodiments the multi-package module includes three or more packages, affixed serially to form a stack.

[0040] In one general aspect the invention features a multi-package module having stacked first (“bottom”) and second (“top”) packages, the bottom package being a BGA package and the top package being an LGA package, each package including a first die attached to a substrate, in which the LGA package substrate and the BGA package substrate are interconnected by wire bonding, and in which the LGA package substrate is inverted so that the LGA substrate surface to which its die is attached is downward. In some embodiments the second package is an LGA package, and in some embodiments the second package is a saw-singulated package, and may be a chip scale package. In some embodiments the second package is a bump chip carrier package.

[0041] In another aspect the invention features a multi-package module having stacked first (“bottom”) and second (“top”) packages, the bottom package being a BGA package and the top package being an inverted LGA package, in which the inverted LGA package substrate and the BGA package substrate are interconnected by wire bonding, and in which at least one of the packages is provided with a heat spreader. In some such configurations a heat spreader may additionally be configured to serve as an electrical shield, particularly for example where the heat spreader is situated over a lower die, that is, between a bottom and a top package in the stack. In some embodiments the heat spreader is affixed to the upward surface of a topmost LGA package, and in such embodiments the heat spreader is exposed to ambient at the topmost surface of the MPM.

[0042] In another aspect the invention features a multi-package module having stacked first (“bottom”) and second (“top”) packages, the bottom package being a flip-chip BGA package having a flip-chip in a “die-up” configuration and the top package being an inverted LGA package, in which the top substrate and the bottom package are interconnected by wire bonding. In some embodiments the top package is a stacked die package; in some embodiments the adjacent stacked die in the stacked die package can be separated by spacers. In some embodiments the die on the BGA package is at least partially enclosed within an electrical shield (a “can” or “cage) affixed to the under surface of the BGA substrate. In some embodiments the bottom package substrate includes an embedded ground plane, the ground plane being configured to serve also for heat dissipation and as an electrical shield. In some embodiments a plurality of inverted second (“top”) packages is affixed over a plurality of die attach regions on the upper surface of the first (“bottom”) package substrate.

[0043] In another aspect the invention features a multi-package module having stacked first (“bottom”) and second (“top”) packages, the bottom package being a flip-chip BGA package having a flip-chip in a “die-down” configuration and the top package being an inverted LGA package, in which the top substrate and the bottom package are interconnected by wire bonding. In some embodiments the flip-chip die on the bottom package is provided with an electrical shield.

[0044] In another aspect the invention features a multi-package module having stacked first (“bottom”) and second (“top”) packages, the bottom package being a BGA package and the top package being an inverted LGA package, in which the inverted LGA package substrate and the BGA package substrate are interconnected by wire bonding, and in which either the top LGA package or the bottom BGA package is a stacked die package, that is, the package includes a stack of two or more die connected to a surface of the substrate; or in which both packages are stacked die packages.

[0045] In some such embodiments the top LGA package may include a stack of two or more die affixed to, and connected (as for example by wire bonding) to the upside of the LGA substrate (oriented downward in the inverted LGA package).

[0046] In another aspect the invention features a multi-package module having stacked bottom and top packages, the bottom package being a BGA package and the top package being an inverted LGA package, in which an additional die is attached to the bottom surface of the LGA substrate (oriented upward in the inverted LGA package), that is, on the LGA substrate surface opposite the surface to which a first die is attached. In such embodiments there is at least one die on both the upper and the lower (downward and upward) surfaces of the LGA substrate. In some embodiments the interconnect of the additional die on the LGA substrate is by wire bonding to the LGA substrate; in some embodiments the interconnect of the additional die on the LGA substrate is a is flip chip interconnect.

[0047] In another aspect the invention features a multi-package module having stacked bottom and top packages, the bottom package being a BGA package and the top package being an inverted LGA package, in which a third package is affixed upon the top LGA package. In some embodiments the third package is a second inverted LGA package, and the z-interconnect between the third package is by wire bonding; in some embodiments the third package is not inverted, and the z-interconnect with the inverted LGA package is by solder balls between ball pads on the lower surface (downward surface) of the third package and ball pads on the lower surface (that is, the upward surface) of the inverted LGA package.

[0048] In another aspect the invention features a multi-package module having stacked first (“bottom”) and second (“top”) packages, the bottom package being a BGA package and the top package being a bump chip carrier package, in which the bump chip carrier package substrate and the BGA package substrate are interconnected by wire bonding, and in which the bump chip carrier package is inverted so that the substrate surface to which its die is attached is oriented downward.

[0049] In another general aspect the invention features a method for making a multi-package module, by providing a first (“bottom”) molded package including a bottom package substrate and a die, dispensing adhesive onto an upper surface of the bottom molded package, placing a second (“top”) package including a top package substrate and a die in an inverted orientation such that an upper (downward) surface of the top package substrate contacts the adhesive on the upper surface of the bottom package, curing the adhesive, and forming z-interconnects between the top and bottom substrates.

[0050] In some embodiments the multi-package module includes a third or additional packages, and the method includes affixing the third or additional packages serially to form a stack.

[0051] In one aspect the invention features a method for making a multi-package module including an inverted top package, which may be an LGA package or a bump chip carrier (“BCC”) package stacked over a bottom BGA package, in which the top and bottom packages are electrically interconnected by wire bonding. According to this aspect, a BGA package is provided, usually in an unsingulated strip of molded BGA packages; preferably the BGA packages in the strip are tested for performance and reliability and packages identified as “good” are subjected to subsequent treatment; adhesive is dispensed over the upper surface of the molding on “good” BGA packages; a singulated (for example, saw-singulated) molded land grid array package or bump chip carrier package is provided; preferably the LGA package or BCC package is tested and identified as “good”; the “good” LGA or BCC package is inverted and placed onto the adhesive over the molding on the “good” BGA package, and the adhesive is cured; optionally and preferably a plasma clean operation is performed followed by formation of wire bond z-interconnections between the stacked top and bottom packages; optionally and preferably an additional plasma clean may be performed, followed by the formation of the MPM molding. Further steps include attachment of second-level interconnect solder balls to the underside of the module; testing and singulation of the completed module from the strip, for example by saw singulation or by punch singulation; and packaging for further use.

[0052] In some embodiments the method includes steps for providing the multi-package module with a heat spreader. In this aspect of the invention a similar process is performed, with additional steps interposed installation of supported heat spreader by a “drop-in” mold operation, or for installation of a simple planar heat spreader by a drop-in mold operation; or by applying adhesive onto an upper surface of the top package molding or onto an upper surface of a spacer upon the top package, and affixing the planar heat spreader onto the adhesive.

[0053] In another aspect the invention features a method for making a multi-package module including an inverted top package stacked over a die-down flip chip BGA bottom package, in which the top and bottom packages are electrically interconnected by wire bonding. According to this aspect, a die-down flip chip BGA bottom package, optionally molded, is provided, usually in unsingulated strip of die-down flip chip ball grid array bottom packages; preferably the BGA packages in the strip are tested for performance and reliability and packages identified as “good” are subjected to subsequent treatment; adhesive is dispensed onto the upper surface (back side) of the die on “good” BGA packages; singulated top (e.g., land grid array or bump chip carrier) packages, optionally molded, are provided; preferably the LGA or BCC package is tested and identified as “good”; the “good” LGA or BCC package is inverted and placed onto the adhesive over the shield, and the adhesive is cured; optionally and preferably a plasma clean operation is performed followed by formation of wire bond z-interconnections between the stacked top and bottom packages; optionally and preferably an additional plasma clean may be performed, followed by the formation of the MPM molding. Further steps include attachment of second-level interconnect solder balls to the underside of the module; testing and singulation of the completed module from the strip, for example by saw singulation or by punch singulation; and packaging for further use.

[0054] In another aspect the invention features a method for making a multi-package module including an inverted top package stacked over a die-down flip chip BGA bottom package, in which the top and bottom packages are electrically interconnected by wire bonding, and in which the bottom package is provided with an electrical shield. According to this aspect, a process is performed similar to that described above for the unshielded bottom flip chip bottom package, with an additional step interposed for installation of the shield over the bottom package flip chip die. A die-down flip chip BGA bottom package, optionally molded, is provided, usually in unsingulated strip of die-down flip chip ball grid array bottom packages; preferably the BGA packages in the strip are tested for performance and reliability and packages identified as “good” are subjected to subsequent treatment; an electrical shield is affixed over the die on “good” bottom BGA packages; adhesive is dispensed onto the upper surface of the shield on “good” BGA packages; singulated top (e.g., land grid array or bump chip carrier) packages, optionally molded, are provided; preferably the LGA or BCC package is tested and identified as “good”; the “good” LGA or BCC package is inverted and placed onto the adhesive over the shield, and the adhesive is cured; optionally and preferably a plasma clean operation is performed followed by formation of wire bond z-interconnections between the stacked top and bottom packages; optionally and preferably an additional plasma clean may be performed, followed by the formation of the MPM molding. Further steps include attachment of second-level interconnect solder balls to the underside of the module; testing and singulation of the completed module from the strip, for example by saw singulation or by punch singulation; and packaging for further use.

[0055] In another aspect the invention features a method for making a multi-package module including an inverted top package stacked over a die-up flip chip BGA bottom package, in which the top and bottom packages are electrically interconnected by wire bonding. According to this aspect, a die-up flip chip ball grid array package, usually not molded, is provided, usually as an unsingulated strip of die-up flip chip ball grid array packages; preferably the BGA packages in the strip are tested for performance and reliability and packages identified as “good” are subjected to subsequent treatment; adhesive is dispensed over the upper surface of the substrate on “good” BGA packages; a second package is provided, which may in some embodiments be a stacked die package, optionally and usually molded; preferably the second package is tested and identified as “good”; the “good” second package is inverted and placed onto the adhesive over the BGA substrate, and the adhesive is cured; optionally and preferably a plasma clean operation is performed followed by formation of wire bond z-interconnections between the stacked top and bottom packages; optionally and preferably an additional plasma clean may be performed, followed by the formation of the MPM molding. Further steps include attachment of second-level interconnect solder balls to the underside of the module; testing and singulation of the completed module from the strip, for example by saw singulation or by punch singulation; and packaging for further use.

[0056] In another aspect the invention features a method for making a multi-package module including an inverted top package stacked over a stacked die bottom package, in which the top and bottom packages are electrically interconnected by wire bonding. According to this aspect, a stacked die BGA package, usually molded, is provided, usually as an unsingulated strip of stacked die ball grid array packages is provided; preferably the BGA packages in the strip are tested for performance and reliability and packages identified as “good” are subjected to subsequent treatment; adhesive is dispensed over the upper surface of the “good” stacked die BGA package, usually on the generally planar upper surface of the package molding; a singulated second package is provided, usually molded, which may optionally be a stacked die package; preferably the second package is tested and identified as “good”; the “good” second package is inverted and placed onto the adhesive over the upper surface of the BGA, and the adhesive is cured; optionally and preferably a plasma clean operation is performed followed by formation of wire bond z-interconnections between the stacked top and bottom packages; optionally and preferably an additional plasma clean may be performed, followed by the formation of the MPM molding. Further steps include attachment of second-level interconnect solder balls to the underside of the module; testing and singulation of the completed module from the strip, for example by saw singulation or by punch singulation; and packaging for further use.

[0057] In some embodiments of the method two or more first molded packages are provided in an unsingulated strip, and assembly of the two or more modules proceeds on the strip, and singulation of the two or more modules is carried out after assembly has been completed.

[0058] In methods according to the invention for making multi-package modules the electrical connections between the stacked packages employs conventional wire bonding to form the z-interconnect between the inverted top package substrate and a bottom package substrate in the stack. Particular advantages include the use of established manufacturing infrastructure, low production cost, design flexibility, and a thin package product. The wire bonding process may be carried out in either a “forward” or in a “reverse” manner. That is, the z-interconnect wire bonding can be carried out, in the various package and module configurations, by drawing the wire to a conductive pad on the first package substrate from a bump formed on a conductive pad on the second package substrate; or, by drawing the wire to a conductive pad on the second package substrate from a bump formed on a conductive pad on the first package substrate.

[0059] The invention provides for assembly of more than one semiconductor in a thin and minimal footprint package at the lowest cost and highest final test yield. Furthermore some stack configurations according to the invention allow for high thermal performance, high electrical performance or electrical isolation of an RF component from a digital one. Other stack configurations provide a very thin structure appropriate for handheld or consumer products. All provide for a method for assembly that allows individual testing of the stacked packages to maximize the final yield of the module.

[0060] Additional process steps will be employed to complete the multi-package module according to the invention. For example, it may be preferred not to attach solder balls for connection of the lowermost package in the stack to the motherboard until the final step before singulation of the MPMs. And, for example, a plasma clean may be performed at any of a variety of points in the process, such as following adhesive cure and prior to encapsulation, and such as prior to and/or following z-interconnect wire bonding.

[0061] Advantageously, the individual packages can be provided as strips of several packages, connected in a row for ease of handling during manufacture, to be singulated following completion of process steps. In methods according to the invention, a strip of first packages of a selected type can be kept nonsingulated, and the package stacks can be formed on the strip by affixing singulated packages and forming the wire bonded z-interconnects serially until the process of forming the modules is complete, and then singulating the modules.

[0062] MPM according to the invention can be used for building computers, telecommunications equipment, and consumer and industrial electronics devices.

BRIEF DESCRIPTION OF THE DRAWINGS

[0063] FIG. 1A is a diagrammatic sketch in a sectional view thru a conventional ball grid array semiconductor package.

[0064] FIG. 1B is a diagrammatic sketch in a sectional view thru a conventional ball grid array semiconductor package having a molding cap over the entire substrate surface, as for example a chip scale package.

[0065] FIG. 2 is a diagrammatic sketch in a sectional view thru a conventional multi-package module having solder ball z-interconnection between stacked ball grid array semiconductor packages.

[0066] FIG. 3 is a diagrammatic sketch in a sectional view thru a conventional flip chip multi-package module having solder ball z-interconnection between stacked flip chip semiconductor packages.

[0067] FIG. 4 is a diagrammatic sketch in a sectional view thru a conventional multi-package module having a folded flexible substrate and solder ball z-interconnection between stacked semiconductor packages.

[0068] FIG. 5A is a diagrammatic sketch in a sectional view thru an embodiment of a multi-package module having wire bond z-interconnection between stacked lower BGA and inverted upper LGA semiconductor packages according to an aspect of the invention.

[0069] FIG. 5B is a sketch in a plan view showing bottom BGA z-interconnect bond pads in an arrangement suitable for use in an embodiment of the invention as shown in FIG. 5A.

[0070] FIG. 5C is a sketch in a plan view showing top LGA z-interconnect bond pads in an arrangement suitable for use in an embodiment of the invention as shown in FIG. 5A.

[0071] FIG. 5D is a diagrammatic sketch in a sectional view thru an embodiment of a multi-package module having wire bond z-interconnection between stacked lower BGA and inverted upper LGA semiconductor packages, having a heatspreader over the inverted LGA, according to an aspect of the invention.

[0072] FIG. 6A is a diagrammatic sketch in a sectional view thru an embodiment of a multi-package module having wire bond z-interconnection between stacked lower BGA and inverted upper LGA semiconductor packages, and having an electrical shield/heatspreader over the lower BGA and between the lower BGA and the inverted upper LGA, according to a further aspect of the invention.

[0073] FIG. 6B is a diagrammatic sketch in a sectional view thru an embodiment of a multi-package module having wire bond z-interconnection between stacked lower BGA and inverted upper LGA semiconductor packages, and having an electrical shield/heatspreader over the lower BGA and between the lower BGA and the inverted upper LGA as in FIG. 6A, and further having a heatspreader over the inverted LGA, according to a further aspect of the invention.

[0074] FIG. 7A is a diagrammatic sketch in a sectional view thru an embodiment of a multi-package module having wire bond z-interconnection between stacked bottom flip chip (die down) BGA and inverted top LGA semiconductor packages according to a further aspect of the invention.

[0075] FIG. 7B is a diagrammatic sketch in a sectional view thru an embodiment of a multi-package module having wire bond z-interconnection between stacked bottom flip chip (die down) BGA and inverted top LGA semiconductor packages according to a further aspect of the invention, the bottom package being provided with an electromagnetic shield/heat spreader.

[0076] FIG. 7C is a diagrammatic sketch in a sectional view thru an embodiment of a multi-package module having wire bond z-interconnection between stacked lower flip chip (die down) BGA and inverted upper LGA semiconductor packages according to a further aspect of the invention, the bottom package being provided with an electromagnetic shield/heat spreader, and the module being further provided with a top heat spreader.

[0077] FIG. 8A is a diagrammatic sketch in a sectional view thru an embodiment of a multi-package module having wire bond z-interconnection between stacked bottom flip chip (die up) BGA and inverted top LGA semiconductor packages according to a further aspect of the invention.

[0078] FIG. 8B is a diagrammatic sketch in a sectional view thru an embodiment of a multi-package module having wire bond z-interconnection between stacked bottom flip chip (die up) BGA and inverted top LGA semiconductor packages according to a further aspect of the invention, the bottom package being provided with an electromagnetic shield/heat spreader.

[0079] FIG. 8C is a diagrammatic sketch in a sectional view thru an embodiment of a multi-package module having wire bond z-interconnection between stacked lower flip chip (die up) BGA and inverted upper LGA semiconductor packages according to a further aspect of the invention, the bottom package being provided with an electromagnetic shield/heat spreader, and the module being further provided with a top heat spreader.

[0080] FIG. 8D is a diagrammatic sketch in a sectional view thru an embodiment of a multi-package module having wire bond z-interconnection between stacked lower flip chip (die up) BGA and multiple inverted upper LGA semiconductor packages according to a further aspect of the invention.

[0081] FIG. 9A is a diagrammatic sketch in a sectional view thru an embodiment of a multi-package module having wire bond z-interconnection between stacked lower BGA and inverted upper LGA semiconductor packages according to a further aspect of the invention, in which each of the inverted upper LGA and lower BGA has stacked die wire-bonded to the substrate.

[0082] FIG. 9B is a diagrammatic sketch in a sectional view thru an embodiment of a multi-package module having wire bond z-interconnection between stacked lower BGA and inverted upper LGA semiconductor packages according to a further aspect of the invention, in which each of the inverted upper LGA and lower BGA has stacked die wire-bonded to the substrate, and in which the module is provided with a top heat spreader.

[0083] FIG. 10A is a diagrammatic sketch in a sectional view thru an embodiment of a multi-package module having wire bond z-interconnection between stacked bottom BGA and inverted top semiconductor packages according to a further aspect of the invention, in which the top package is a BCC package.

[0084] FIG. 10B is a diagrammatic sketch in a sectional view thru an embodiment of a multi-package module having wire bond z-interconnection between stacked bottom BGA and inverted top semiconductor packages according to a further aspect of the invention, in which the top package is a BCC package having an additional die stacked on the BCC die.

[0085] FIG. 11A is a diagrammatic sketch in a sectional view thru an embodiment of a multi-package module having wire bond z-interconnection between stacked bottom BGA and inverted top LGA semiconductor packages according to a further aspect of the invention, in which the die in the bottom BGA is wire-bonded to the substrate, and in which a first die on the downward facing surface of the inverted top LGA is wire-bonded to the LGA substrate and a second die on the opposite (upward facing) surface of the top LGA is flip-chip interconnected to the LGA substrate.

[0086] FIG. 11B is a diagrammatic sketch in a sectional view thru an embodiment of a multi-package module having wire bond z-interconnection between stacked bottom BGA and inverted top LGA semiconductor packages according to a further aspect of the invention, in which the die in the bottom BGA is wire-bonded to the substrate, and in which both a first die on the downward facing surface of the inverted top LGA and a second die on the upward facing surface of the bottom package substrate are wire-bonded to the top LGA substrate.

[0087] FIG. 11C is a diagrammatic sketch in a sectional view thru an embodiment of a multi-package module having wire bond z-interconnection between stacked bottom BGA and inverted top LGA semiconductor packages according to a further aspect of the invention, in which a third package is stacked over the inverted top LGA package, and is wire bonded thereto.

[0088] FIG. 11D is a diagrammatic sketch in a sectional view thru an embodiment of a multi-package module having wire bond z-interconnection between stacked bottom BGA and inverted top LGA semiconductor packages according to a further aspect of the invention, in which a third package is stacked over the inverted top LGA package, and is connected by solder balls thereto.

[0089] FIG. 12 is a flow diagram showing a process for assembly of a multi-package module according to the invention.

[0090] FIG. 13 is a flow diagram showing a process for assembly of a multi-package module according to the invention, in which the bottom package is provided with a heat shield/heat spreader.

[0091] FIG. 14 is a flow diagram showing a process for assembly of a multi-package module according to the invention, in which the bottom package is provided with a heat shield/heat spreader, and the module is further provided with a top heat spreader.

[0092] FIG. 15 is a flow diagram showing a process for assembly of a multi-package module according to the invention, in which the bottom package is a flip chip package in a die-down configuration.

[0093] FIG. 16 is a flow diagram showing a process for assembly of a multi-package module according to the invention, in which the bottom package is a flip chip package in a die-down configuration, and the package is provided with a top heat spreader.

[0094] FIG. 17 is a flow diagram showing a process for assembly of a multi-package module according to the invention, in which the bottom package is a flip chip package in a die-up configuration.

[0095] FIG. 18 is a flow diagram showing a process for assembly of a multi-package module according to the invention, in which the top and bottom packages are stacked die packages.

DETAILED DESCRIPTION

[0096] The invention will now be described in further detail by reference to the drawings, which illustrate alternative embodiments of the invention. The drawings are diagrammatic, showing features of the invention and their relation to other features and structures, and are not made to scale. For improved clarity of presentation, in the Figs. illustrating embodiments of the invention, elements corresponding to elements shown in other drawings are not all particularly relabeled, although they are all readily identifiable in all the Figs.

[0097] Turning now to FIG. 5A, there is shown in a diagrammatic sectional view generally at 50 an embodiment of a multi-package module, including stacked first (“bottom”) and second (“top”) packages, in which the top package is inverted, and the stacked packages are interconnected by wire bonding, according to an aspect of the invention. In the embodiment shown in FIG. 5A, the bottom package 400 is a conventional BGA package such as that shown in FIG. 1A. Accordingly, in this embodiment the bottom package 400 includes a die 414 attached onto a bottom package substrate 412 having at least one metal layer. Any of various substrate types may be used, including for example: a laminate with 2-6 metal layers, or a build up substrate with 4-8 metal layers, or a flexible polyimide tape with 1-2 metal layers, or a ceramic multilayer substrate. The bottom package substrate 412 shown by way of example in FIG. 5A has two metal layers 421, 423, each patterned to provide appropriate circuitry and connected by way of vias 422. The die is conventionally attached to a surface of the substrate using an adhesive, typically referred to as the die attach epoxy, shown at 413 in FIG. 5A and, in the configuration in FIG. 5A, the surface of the substrate onto which the die is attached may be referred to as the “upper” surface, and the metal layer on that surface may be referred to as the “upper” metal layer, although the die attach surface need not have any particular orientation in use.

[0098] In the bottom BGA package of FIG. 5A the die is wire bonded onto wire bond sites on the upper metal layer of the substrate to establish electrical connections. The die 414 and the wire bonds 416 are encapsulated with a molding compound 417 that provides protection from ambient and from mechanical stress to facilitate handling operations, and provides a bottom package upper surface 419 onto which a second (“top”) package can be stacked. The connections to the die are exposed at the periphery of the package with pads on the top metal layer of the substrate and available for connecting with wire bonds as described in more detail below with reference to FIGS. 5B and 5C. These pads easily fit within the space available between the lower BGA mold cap and the edge of the package, without increasing the overall footprint of the BGA. The physical location and order of these pads is arranged so as to approximately lie under the equivalent pads on the LGA situated above. Solder balls 418 are reflowed onto bonding pads on the lower metal layer of the substrate to provide interconnection to underlying circuitry of, for example, a motherboard (not shown in the FIGS.) of a final product, such as a computer. Solder masks 415, 427 are patterned over the metal layers 421, 423 to expose the underlying metal at bonding sites for electrical connection, for example the wire bond sites and bonding pads for bonding the wire bonds 416 and solder balls 418.

[0099] In the embodiment shown in FIG. 5A, the top package 500 is a land grid array (“LGA”) package which may be a saw singulated LGA package, as shown for example in FIG. 1B, and may be a chip scale package; but here the top package has no solder balls mounted on bonding pads of the lower surface of the substrate. Particularly, in this example, the top package 500 includes a die 514 attached onto a top package substrate 512 having at least one metal layer. Any of various substrate types may be used; the top package substrate 512 shown by way of example in FIG. 5A has two metal layers 521, 523, each patterned to provide appropriate circuitry and connected by way of vias 522. The die is conventionally attached to a surface of the substrate using an adhesive, typically referred to as the die attach epoxy, shown at 513 in FIG. 5A. Referring again to FIGS. 1A and 1B, the die is referred to as being attached to an upper surface of the package substrate, it being appreciated that the package need not have any particular orientation in use. According to the invention, the top package is inverted, that is to say, it is attached upside downward and downside upward. Because the upper LGA is inverted in the module, so that it is relatively speaking upside-down or downside-up, the surface of the upper LGA to which the first die is attached, which would customarily be termed the upper surface or upper side of the LGA substrate, is referred to in the text herein as the downward or downward facing surface of the inverted LGA; and the opposite surface, which would customarily be termed the lower surface or lower side, is referred to in the text herein as the upward or upward facing surface.

[0100] In the configuration in FIG. 5A, for example, the surface of the top package substrate onto which the die is attached faces toward the bottom package, and, accordingly the “upper” surface of the top package, to which the die is affixed, is here referred to as the “downward facing” surface of the top package substrate, it being appreciated again that the module need not have any particular orientation in use. That is to say, once the top package has been inverted in the module according to the invention, for purposes of description the surface of the top package substrate having the “upper” metal layer 521 is said to be “downward facing”, and the surface of the top package substrate having the “lower” metal layer 523 is said to be “upward facing”.

[0101] In the top LGA package in the embodiment of FIG. 5A the die is wire bonded onto wire bond sites on the upper metal layer of the top package substrate to establish electrical connections. The die 514 and the wire bonds 516 are encapsulated with a molding compound 517 that provides protection from ambient and from mechanical stress to facilitate handling operations, and has a top package upper surface 519. The top package 500 is inverted (so that the surface 519 is “downward facing”, and is stacked over the bottom package 400 and affixed there using an adhesive 513. Solder masks 515, 527 are patterned over the metal layers 521, 523 to expose the underlying metal at bonding sites for electrical connection, for example the wire bond sites for bonding the wire bonds 516.

[0102] The z-interconnect between the stacked top package 500 and bottom package 400 is made by way of wire bonds 518 connecting traces on the upward facing metal layer (the “lower” metal layer 523) of the top package substrate with traces on the upper metal layer 421 of the bottom package substrate. At one end each wire bond 518 is electrically connected to upward facing surfaces of pads on the lower metal layer 523 of the top package substrate 512, and at the other end each wire bond is connected to upper surfaces of pads on the upper metal layer 421 of the bottom package substrate 412. The wire bonds may be formed by any wire bonding technique, well known in the art, such as is described, for example, in U.S. Pat. No. 5,226,582, which is hereby incorporated by reference herein. The package-to-package z-interconnect wire bonds are shown by way of example in FIG. 5A as having been made by forming a bead or bump on the upper surface of a pad on the upper metal layer of the top substrate, and then drawing the wire downward toward and fusing it onto, a pad on the upper metal layer of the bottom substrate. As will be appreciated, the wire bonds can be made in the inverse direction, that is, by forming a bead or bump on the upper surface of a pad on the upper metal layer of the bottom substrate, and then drawing the wire upward toward and fusing it onto, a pad on the upper metal layer of the top substrate. As will be appreciated, selection of a wire bonding strategy for the package-to-package z-interconnection will be determined according to the geometric arrangements of the margins of the stacked substrates and of the bonding surfaces on them.

[0103] The top LGA package may be either array molded and saw singulated (giving vertical walls at the edges, as shown for example in FIG. 1B and as the upper LGA in FIG. 2, or cavity molded and punch singulated. In either type, the top package has bond pads connected to the die (through vias to the die attach side of the substrate) and situated at the periphery of the package on the substrate surface opposite the surface on which the die is attached, that is, on the “lower” (upward-facing) side of the top package substrate, as described in further detail below with reference to FIG. 5C.

[0104] The structure according to the invention allows for pre-testing of both the BGA and LGA before assembly into the multi-package module, to permit rejection of nonconforming packages prior to assembly, and thereby to assure high final module test yields.

[0105] In the stacked package embodiment of FIG. 5A, the z-interconnect pads on the respective package substrates are arranged on upward facing metal layers near the margins of the package substrates. The location and order of the z-interconnect pads are generally arranged so that the z-interconnect pads on the top package substrate approximately overlie the corresponding z-interconnect pads on the bottom package when the packages are stacked. Conveniently, the top package 500 has a smaller substrate footprint than that of the bottom package 400, to allow clearance for the wire bonds without electrical shorting to the edges of the metal layers of the substrates. Once the z-interconnect wire bonds have been formed, a module encapsulation 507 is formed, to enclose and protect the z-interconnect wire bonds and to provide mechanical integrity to the completed module. Accordingly, the module includes molded packages within the module molding. As shown by way of example in FIG. 5A, the module may itself be saw-singulated; alternatively, the module may be individually molded rather than saw-singulated.

[0106] The arrangements of the z-interconnect pads on the top and bottom package substrates are shown by way of example in diagrammatic plan view in FIGS. 5B and 5C, generally at 500 and 400, respectively. Referring to FIG. 5B, top package z-interconnect pads 524 are formed by patterning regions of the lower metal layer peripherally situated on the “lower” surface 525 of the top package substrate 512. As will be appreciated, when the top package is inverted, the “lower” substrate surface 525 becomes the upward-facing surface of the top package substrate, and the top package z-interconnect pads 524 are, accordingly, also upward-facing in the module. Also, as may be appreciated, the more centrally situated ball attach pads on the upward-facing side of the top package substrate are not necessary for z-interconnection and may be lacking in certain embodiments, depending upon the design of the top package. They are omitted, for illustrative purposes, from FIG. 5C.

[0107] Optionally, and in some applications preferably, the ball attach pads on the upward-facing side of the inverted top package substrate may be employed to facilitate testing of the LGA using a conventional test socket. Such testing of the LGA can be carried out prior to attaching the top LGA package into the bottom package, to ensure that only top LGAs testing as “good” are stacked over the bottom BGA packages (which may also be tested and identified as “good”). Or, testing of the LGA can be carried out following inversion of the LGA and attachment as a top package, but prior to formation of the overall module molding, or prior to z-interconnect wire-bonding. Testing, facilitated according to the constructs of the invention, at any of various stages in manufacture, can significantly reduce the likelihood of further processing of components that do not meet specifications.

[0108] Referring now to FIG. 5C, bottom package z-interconnect pads 424 are formed by patterning regions of the upper metal layer situated at the margin 401 on the upper surface 425 of the bottom package substrate 412. The margin 401 extends beyond the footprint 426 of the stacked and overlying top package, defined by the edge 511 of the top package substrate 512. The width of the margin 401 can be less about 1 mm, and, in order to provide adequate clearance for the wire bonding the width of the margin 401 may preferably be greater than about 0.2 mm. Nominally in some embodiments the margin 401 is about 0.5 mm. Where the module is saw-singulated, the margin constitutes approximately the clearance between the edge of the top package substrate and the side of the module molding.

[0109] The clearance between the z-interconnect wire bonds 518 and the upper surface of the module molding may preferably be about 75 μm or greater, to avoid impact between the molding machinery and the wire loops during molding formation; and the molding thickness over the upward-facing surface of the top package may preferably be greater than about 150 μm, to avoid formation of voids in the module molding. Where reverse wire bonding is employed, so that an end of the wire loop is stitched onto the pads on the upward facing side of the top package, the wire loop height in practice may be as little as about 75 μm and, accordingly, a molding thickness of as little as about 150 μm can be achieved in such embodiments. A greater mold height will be required where forward wire bonding is employed, as the wire loop height over a ball (or bump) as more usually about 125 μm or greater using currently available wire bonding techniques forming wire having about 1 mil thickness.

[0110] As will be apparent from FIGS. 5A, 5B and 5C, z-interconnection between the top and bottom packages according to the invention is made by wire bond between (either bond-up or bond-down) the top package interconnect pads 524 in the margin 501 of the top package substrate and the bottom package interconnect pads 424 in the margin 401 of the bottom package substrate. The multipackage module structure is protected by formation of a module encapsulant 507, and solder balls 418 are reflowed onto exposed solder ball pads on the lower metal layer of the bottom package substrate, for connection to underlying circuitry, such as a motherboard (not shown in the FIGS.).

[0111] The multi-package module of the invention can be employed in any of a diverse variety of applications, such as, for example, computers, portable communications devices, consumer products.

[0112] For improved heat dissipation from the multi-package module, a heat spreader may be provided over the top package. The top heat spreader is formed of a thermally conductive material having at least the more central area of its upper surface exposed at the upper surface of the MPM to ambient for efficient heat exchange away from the MPM. The top heat spreader may be, for example, a sheet of metal (such as copper or aluminum) or of any of a variety of other thermally conductive materials, such as aluminum nitride. The heat spreader has a size and shape to substantially cover the package. The heat spreader can be made thicker in a central area over the top package to increase metal content, and thinner at the periphery so that it does not interfere with the z-interconnect wire bonds. If made thicker in a central area the heat spreader may be affixed to the upward facing surface of the top package. Or, a spacer may be placed over the upward facing surface of the package inboard of the wire bond sites, and the heat spreader may be affixed to the upper surface of the spacer. Alternately the heatspreader can be molded-in, resulting in a similar structure but without the adhesive; that is, the heat spreader may be dropped into the MPM encapsulant mold and affixed at the upper surface of the module during the molding material curing process. Or, the heatspreader may have a generally planar portion over the top package, and a peripheral supporting portion or supporting members resting on or near the upper surface of the bottom package substrate.

[0113] For example, a top heat spreader having a thicker central region can be affixed to the upward facing surface of the top package as shown diagrammatically in a sectional view in FIG. 5D. The construction of the stacked packages in MPM 52 is generally similar to that of MPM 50. in FIG. 5A, and like structures are identified in the FIGS. by like reference numerals. The top heat spreader 530 in the example of FIG. 5D is a generally planar piece of a thermally conductive material having at least the more central area of its planar upper surface exposed to ambient for efficient heat exchange away from the MPM. The top heat spreader 530 has a thicker central portion, inboard of the wire bond sites on the top package, and the thicker portion is affixed to the upward facing side 519 of the top package using an adhesive 532. The thickness of the heat spreader may in some embodiments be in the range 0.2 to 0.6 mm, nominally 0.4 mm. The top heat spreader may be, for example, constructed of metal (such as copper, or aluminum). Where the top heat spreader is made of copper, the lower surface is preferably treated to have a black oxide, for improved adhesion to the attachment material beneath; the exposed upper surface may be treated to form a black oxide, or it may be provided with a matte nickel (plate) surface. The adhesive 532 may optionally be a thermally conductive adhesive, such as a thermally conductive epoxy, to provide improved heat dissipation; and the adhesive may be electrically nonconductive, in embodiments having exposed electrical features on the upward facing (“lower”) side. Usually the top heat spreader is affixed to the top package before the molding material is injected for the MPM encapsulation 507. The periphery of the top heat spreader may be encapsulated with the MPM molding material. In the embodiment of FIG. 5D a step like re-entrant feature 534 is provided on the periphery of the heat spreader 530 to allow for better mechanical integrity of the structure with less delamination from the molding compound.

[0114] As a further alternative, an MPM as in FIG. 5A can be provided with a top heat formed of a thermally conductive material having a generally planar central portion situated over the top package, and peripheral supporting members extending from near the edges or the corners of the generally planar central portion to the upper surface of the bottom package substrate 412, outside the z-interconnect bond pads and near the edge of bottom package. The upper surface of the planar portion is exposed to ambient at the MPM upper surface for efficient heat exchange away from the MPM. The top heat spreader may be formed, for example, of a sheet of metal (such as copper), for example by stamping. The supporting members can optionally be affixed to the upper surface of the bottom package substrate using an adhesive. The heat spreader supporting members are embedded in the MPM encapsulant 507 during the molding material curing process. As in the embodiment of FIG. 5D a step like re-entrant feature can be provided on the periphery of the planar upper portion of the heat spreader to allow for better mechanical integrity of the structure with less delamination from the molding compound. In this embodiment the space between the lower surface of the planar central portion of the heat spreader and the upward facing surface 519 of the top package is filled by a thin layer of the MPM molding.

[0115] As a further alternative, an MPM as in FIG. 5A can be provided with a simple planar heat spreader, with no supporting members, that is not attached to the upper surface of the top package molding. In such embodiments, as in the embodiment of FIG. 5D, the top heat spreader can be a generally planar piece of a thermally conductive material such as, for example, a sheet of metal (such as copper or aluminum), and at least the more central area of the upper surface of the planar heat spreader is exposed to ambient for efficient heat exchange away from the MPM. Here, the heat spreader does not have a thicker central portion inboard of the wire bond sites on the upper package; instead, the space between the lower surface of the simple planar heat spreader and the upper surface 519 of the top package may be filled by a thin layer of the MPM molding, and such a simple planar heat spreader may be affixed to the MPM encapsulant 507 during the molding material curing process. The periphery of such an unattached simple planar top heat spreader can be encapsulated with the MPM molding material, as in the attached planar heat spreader of FIG. 5D, and may be provided with a step-like re-entrant feature on the periphery to allow for better mechanical integrity of the structure with less delamination from the molding compound.

[0116] An MPM structure having a heat spreader, as in FIG. 5D, or in the alternative embodiments described above, can provide significant thermal enhancement and may provide electrical shielding over the module, which can be critical to MPMs that combine RF and digital chips.

[0117] FIG. 6A is a diagrammatic sketch in a sectional view showing an inverted top LGA package stacked over a BGA package in an MPM 60 according to another aspect of the invention, in which a heat spreader/electrical shield is provided to the bottom package. The embodiment shown by way of example in FIG. 6A has a top land grid array (“LGA”) package 500 inverted and stacked over a bottom ball grid array (“BGA”) package 400, in which the inverted top LGA package is constructed generally as is the top LGA package in FIG. 5A. Referring to FIG. 6A, the top LGA package 500 may be similar to a BGA package, as shown for example in FIG. 1A, but having no solder balls mounted on bonding pads of the lower surface of the substrate. Particularly, in this example, the top package 500 includes a die 514 attached onto a top package substrate 512. Any of various substrate types may be used; the top package substrate 512 shown by way of example in FIG. 6A has two metal layers 521, 523, each patterned to provide appropriate circuitry and connected by way of vias 522. The die is conventionally attached to a surface of the substrate using an adhesive, typically referred to as the die attach epoxy, shown at 513 in FIG. 6A and, in the configuration in FIG. 6A, the surface of the substrate onto which the die is attached may be referred to as the “upper” surface, and the metal layer on that surface may be referred to as the “upper” metal layer, although the die attach surface need not have any particular orientation in use, and, for purposes of description the die attach side of the top package substrate is the downward facing side when the top package is inverted in the multi-package module according to the invention.

[0118] In the top LGA package in the embodiment of FIG. 6A the die is wire bonded onto wire bond sites on the upper metal layer of the substrate to establish electrical connections. The die 514 and the wire bonds 516 are encapsulated with a molding compound 517 that provides protection from ambient and from mechanical stress to facilitate handling operations, and has a top package molding surface. In the inverted orientation the top package molding surface is downward facing. Solder masks 515, 527 are patterned over the metal layers 521, 523 to expose the underlying metal at bonding sites for electrical connection, for example the wire bond sites for bonding the wire bonds 516. In its inverted orientation in the multi-package module, the top package has an upward facing surface 519.

[0119] The bottom BGA package 400 in the embodiment of FIG. 6A is a conventional BGA package such as that shown in FIG. 1A, except that the bottom BGA package of FIG. 6A is not encapsulated with a molding compound; rather, it is provided with a heat spreader that can additionally act as an electrical shield, as described below. Accordingly, in this embodiment the bottom package 400 includes a die 414 attached onto a bottom package substrate 412 having at least one metal layer. Any of various substrate types may be used, including for example: a laminate with 2-6 metal layers, or a build up substrate with 4-8 metal layers, or a flexible polyimide tape with 1-2 metal layers, or a ceramic multilayer substrate. The bottom package substrate 412 shown by way of example in FIG. 6A has two metal layers 421, 423, each patterned to provide appropriate circuitry and connected by way of vias 422. The die is conventionally attached to a surface of the substrate using an adhesive, typically referred to as the die attach epoxy, shown at 413 in FIG. 6A and, in the configuration in FIG. 6A, the surface of the substrate onto which the die is attached may be referred to as the “upper” surface, and the metal layer on that surface may be referred to as the “upper” metal layer, although the die attach surface need not have any particular orientation in use.

[0120] In the bottom BGA package of FIG. 6A the die is wire bonded onto wire bond sites on the upper metal layer of the substrate to establish electrical connections. Solder balls 418 are reflowed onto bonding pads on the lower metal layer of the substrate to provide interconnection to underlying circuitry of, for example, a printed circuit board (not shown in the FIGS.) of a final product, such as a computer. Solder masks 415, 427 are patterned over the metal layers 421, 423 to expose the underlying metal at bonding sites for electrical connection, for example the wire bond sites and bonding pads for bonding the wire bonds 416 and solder balls 418.

[0121] The bottom BGA package 400 of multipackage module 60 is provided with a metallic (for example, copper) heat spreader that acts additionally as an electrical shield to electrically contain any electromagnetic radiation from the die in the lower BGA and thereby prevent interference with the die in the upper package. An “upper” planar part of the heat spreader 406 is supported above the substrate 412 and over the die 414 by legs or vented sidewalls 407. Spots or lines 408 of an adhesive serve to affix the heat spreader support 407 to the upper surface of the bottom substrate. The adhesive can be a conductive adhesive, and can be electrically connected to the top metal layer 421 of the substrate 412, particularly to a ground plane of the circuit and thereby establishing the heat spreader as an electrical shield. To provide good shielding, the electric shield is constructed of a highly electrically conductive material, usually a metal such as aluminum or copper. Where it is copper, the copper surface is preferably treated to provide a black oxide surface, or is provided with a nickel plating, to improve adhesion. Or, the adhesive can be non-conductive and in such a configuration the heat spreader acts only as a heat spreading device. The supporting parts and the top part of the heat spreader 406 enclose the die 414 and the wire bonds 416, and can serve to protect those structures from ambient and from mechanical stress to facilitate handling operations and, particularly, during subsequent testing before the MPM assembly. Accordingly, no separate bottom package molding is necessary in such embodiments (the MPM molding, fills in later), making for decreased manufacturing cost.

[0122] The top package 500 of multipackage module 60 is stacked over the bottom package 400 upon the planar surface of the heat spreader/shield 406 and affixed there using an adhesive 503. The adhesive 503 can be thermally conductive, to improve thermal dissipation.

[0123] The z-interconnection between the top package 500 and the bottom package 400 according to the invention is made by wire bonds 518 between top package interconnect pads in the margin of the top package substrate 512 and bottom package interconnect pads in the margin of the bottom package substrate 400. The wire bonds may be formed in either up-bond or down-bond (forward or reverse bond) fashion. The multipackage module structure is protected by formation of a module encapsulant 607. Openings (vents) may be provided in the supporting parts 407 of the heat spreader to allow the MPM molding material to fill in the enclosed space during encapsulation.

[0124] Solder balls 418 are reflowed onto exposed solder ball pads on the lower metal layer of the bottom package substrate 412, for connection to underlying circuitry, such as a printed circuit board (not shown in the FIGS.) such as a motherboard.

[0125] Multi-package modules according to this aspect of the invention, in which an electric shield is provided over the bottom package, can be particularly useful in radio-frequency devices, as for example in communications equipment. In applications having digital and RF semiconductor chips, the electronic shield can provide noise reduction by suppressing RF interference either to or from the shielded die. This can be particularly useful for example where the bottom package semiconductor die is a radio-frequency device, as for example in communications equipment, to prevent electromagnetic interference between the RF die and the upper package.

[0126] As will be appreciated from the foregoing, the structure according to the invention allows for pre-testing of both the BGA and LGA before assembly into the multi-package module, to permit rejection of nonconforming packages prior to assembly, and thereby to assure high final module test yields.

[0127] For improved heat dissipation from the multi-package module, a top heat spreader may be provided over the top package in addition to the heat spreader/electrical shield over the bottom package as in FIG. 6A. The top heat spreader is formed of a thermally conductive material having at least the more central area of its upper surface exposed at the upper surface of the MPM to ambient for efficient heat exchange away from the MPM. The top heat spreader may be, for example, a sheet of metal (such as copper or aluminum) or of any of a variety of other thermally conductive materials, such as aluminum nitride. The heat spreader has a size and shape to substantially cover the package. The heat spreader can be made thicker in a central area over the top package to increase metal content, and thinner at the periphery so that it does not interfere with the z-interconnect wire bonds. If made thicker in a central area the heat spreader may be affixed to the upward facing surface of the top package. Or, a spacer may be placed over the upward facing surface of the package inboard of the wire bond sites, and the heat spreader may be affixed to the upper surface of the spacer. Alternately the heatspreader can be molded-in, resulting in a similar structure but without the adhesive; that is, the heat spreader may be dropped into the MPM encapsulant mold and affixed at the upper surface of the module during the molding material curing process. Or, the heatspreader may have a generally planar portion over the top package, and a peripheral supporting portion or supporting members resting on or near the upper surface of the bottom package substrate.

[0128] For example, a top heat spreader having a thicker central region can be affixed to the upward facing surface of the top package as shown diagrammatically in a sectional view in FIG. 6B. The construction of the stacked packages in MPM 62 is generally similar to that of MPM 60 in FIG. 6A, and like structures are identified in the FIGS. by like reference numerals. The top heat spreader 530 in the example of FIG. 6B is a generally planar piece of a thermally conductive material having at least the more central area of its planar upper surface exposed to ambient for efficient heat exchange away from the MPM. The top heat spreader 530 has a thicker central portion, inboard of the wire bond sites on the top package, and the thicker portion is affixed to the upward facing side 519 of the top package using an adhesive 532. The thickness of the heat spreader may in some embodiments be in the range 0.2 to 0.6 mm, nominally 0.4 mm. The top heat spreader may be, for example, constructed of metal (such as copper, or aluminum). Where the top heat spreader is made of copper, the lower surface is preferably treated to have a black oxide, for improved adhesion to the attachment material beneath; the exposed upper surface may be treated to form a black oxide, or it may be provided with a matte nickel (plate) surface. The adhesive 532 may optionally be a thermally conductive adhesive, such as a thermally conductive epoxy, to provide improved heat dissipation; and the adhesive may be electrically nonconductive, in embodiments having exposed electrical features on the upward facing (“lower”) side. Usually the top heat spreader is affixed to the top package before the molding material is injected for the MPM encapsulation 607. The periphery of the top heat spreader may be encapsulated with the MPM molding material. In the embodiment of FIG. 6B a step like re-entrant feature 534 is provided on the periphery of the heat spreader 530 to allow for better mechanical integrity of the structure with less delamination from the molding compound.

[0129] As a further alternative, an MPM as in FIG. 6A can be provided with a top heat formed of a thermally conductive material having a generally planar central portion situated over the top package, and peripheral supporting members extending from near the edges or the corners of the generally planar central portion to the upper surface of the bottom package substrate 412, outside the z-interconnect bond pads and near the edge of bottom package. The upper surface of the planar portion is exposed to ambient at the MPM upper surface for efficient heat exchange away from the MPM. The top heat spreader may be formed, for example, of a sheet of metal (such as copper), for example by stamping. The supporting members can optionally be affixed to the upper surface of the bottom package substrate using an adhesive. The heat spreader supporting members are embedded in the MPM encapsulant 607 during the molding material curing process. As in the embodiment of FIG. 6B a step like re-entrant feature can be provided on the periphery of the planar upper portion of the heat spreader to allow for better mechanical integrity of the structure with less delamination from the molding compound. In this embodiment the space between the lower surface of the planar central portion of the heat spreader and the upward facing surface 519 of the top package is filled by a thin layer of the MPM molding.

[0130] As a further alternative, an MPM as in FIG. 6A can be provided with a simple planar heat spreader, with no supporting members, that is not attached to the upper surface of the top package molding. In such embodiments, as in the embodiment of FIG. 6B, the top heat spreader can be a generally planar piece of a thermally conductive material such as, for example, a sheet of metal (such as copper or aluminum), and at least the more central area of the upper surface of the planar heat spreader is exposed to ambient for efficient heat exchange away from the MPM. Here, the heat spreader does not have a thicker central portion inboard of the wire bond sites on the upper package; instead, the space between the lower surface of the simple planar heat spreader and the upper surface 519 of the top package may be filled by a thin layer of the MPM molding, and such a simple planar heat spreader may be affixed to the MPM encapsulant 607 during the molding material curing process. The periphery of such an unattached simple planar top heat spreader can be encapsulated with the MPM molding material, as in the attached planar heat spreader of FIG. 5D, and may be provided with a step-like re-entrant feature on the periphery to allow for