DETAILED DESCRIPTION OF THE INVENTION

[0023] In general, the present invention is a method and structure for providing dense packing of transistors with p-type channels of a first orientation, and n-type channels of a second orientation, with all other design features orthonormal (i.e. orthogonal) to each other. A {100} surfaced silicon wafer is oriented with {100} planes at 22.5 degrees with respect to a vertical reference axis that lies along the plane of the upper surface of the wafer, which results in {110} planes having an orientation that lies 22.5 degrees to the opposite direction of the vertical reference axis. Freestanding silicon bodies are formed along these respective planes according to whether they are used to build n-type or p-type FETs. The gate electrode layer is patterned along a direction orthonormal to (i.e. oriented 90 degrees with respect to) the vertical reference axis of the wafer, with the gate length being defined by the width of the gate electrode overlaying the freestanding silicon body.

[0024] The present invention can be fabricated on either a bulk silicon wafer or a silicon-on-insulator (SOI) wafer. In general, while SOI is preferred for its ease of fabrication of the freestanding silicon bodies as described below relative to bulk silicon wafers, bulk silicon wafers could also be used. In addition, while the invention is discussed relative to a silicon body, other semiconductor bodies (such as conventional single crystal germanium, compounds of silicon and germanium (e.g.strained silicon materials such as SiGe and SiGeC), Group III-V materials such as GaAs and InAs, or Group II-VI materials) could be used.

[0025] In the invention, freestanding rails of silicon are formed to provide the silicon bodies for double gated FETs (that is, FETs having gate electrodes that control the channel region in multiple dimensions, not just from the top down as in conventional FETs). As a practical matter, any process that would form such freestanding silicon bodies, with or without a double gated architecture, could be used. That is, while the preferred embodiment of the invention is to use finFETs, for their relative ease of construction as well as their, resulting double gated architecture, other methods, structures, and architectures for forming FETs (or other active or passive integrated circuit components) on freestanding semiconductor bodies could be used.

[0026] In the description to follow, reference will be made to particular thicknesses, dimensions, and other parametrics for the various structures of the devices of the invention that are based on current semiconductor fabrication technologies as well as those that are foreseen in the future. It is to be understood that with future advances in process integration it may be possible to form the described structures using different/more advanced parametrics. The scope of the present invention is not to be interpreted as being limited to the parametrics set forth below.

[0027] In accordance with a preferred embodiment of the invention, finFET silicon bodies are formed by the following process. First, an SOI substrate 10 is provided, having a given crystal orientation. The SOI wafer has a silicon layer of a thickness of approximately 10-120 nm on top of a buried oxide layer. The silicon layer is covered with a 4-50 nm thick layer of silicon oxide 12 (thermally grown on the silicon layer using conventional techniques), and a 6-75 nm thick layer of undoped polysilicon (or other material suitable for the process as described below) on the silicon oxide layer 12 . Then a photomask is formed on the polysilicon, and the polysilicon layer is etched utilizing conventional techniques, stopping on the silicon oxide layer 12 . Then as shown in FIG. 1 , conventional processes are utilized to form silicon nitride sidewall spacers 30 on the sides of the etched polysilicon (mandrels) 20 N and 20 P. The spacers would be approximately 4-50 nm thick at their widest point (that is, just above the silicon oxide 12 ). Note that it is preferable for the thickness of the polysilicon layer to be on the order of 1.5× the thickness of the silicon nitride spacers; note also that it is preferable for the silicon nitride spacers to have the same general thickness as the silicon oxide 12 . Note, however, that such interrelationships are not required.

[0028] As shown in FIG. 2 , note that from a top view the mandrels 20 are oriented on different angles, as a function of which device is ultimately formed. The mandrels 20 N are oriented so that the resulting channel regions of the FET will be along the {100} plane of the silicon layer on SOI wafer 10 , and are used to form n-type finFETs. The mandrels 20 P are oriented so that the resulting channel regions of the FET will be along the {110} plane of the silicon layer on SOI wafer 10 , and are used to form p-type finFETs. Since in silicon the {100} and {110} planes are oriented at 45 degrees with respect to one another, the mandrels 20 N and 20 P are likewise oriented at 45 degrees with respect to one another. As previously discussed, different semiconductors have different planes at which hole and electron mobility is greatest. Hence, as a practical matter, for other semiconductors the mandrels 20 N and 20 P may be disposed at angles other than 45 degrees with respect to one another. They would be disposed at whatever angles align with the respective crystal orientations that maximize hole and electron mobility, respectively. Also, while only two finFET bodies are shown, as a practical matter other bodies would be formed on the substrate, at either the same orientations or orientations orthonormal to one of the bodies 20 N and 20 P.

[0029] Working with silicon as the preferred embodiment, note that the SOI wafer 10 has a notch 10 A. This notch is typically used to define the horizontal and vertical reference axes of the wafer during processing. Thus, for example, when the wafer is inserted into a photolithographic tool, the notch is used to define the vertical reference axis of the wafer, and the image is printed with that axis as a reference point. It is typical in CMOS technology to align the notch with the {110} crystal orientation of the wafer. In the invention, the notch is instead made at a location that lays 22.5 degrees away from the {100} plane.

[0030] Thus, the fins are generally oriented +/−22.5 degrees away from the four cardinal directions defined by the notch on the wafer. This will result in ‘fins’ of silicon with planes that lie in {110} or {100} planes according to whether they are 22.5 degrees clockwise or counterclockwise, respectively, from the vertical reference axis.

[0031] Returning to the process description, after the polysilicon mandrels 20 N, 20 P are removed, the silicon dioxide layer 12 and the underlaying silicon layer are etched to form the fin bodies, with the silicon nitride sidewalls 30 serving as a mask. Note that the combination of the nitride spacers 30 and the underlaying silicon oxide 12 collectively provide a hard mask that will maintain its dimensional integrity for the full etch of the silicon layer. Then the silicon nitrde sidewall spacers 30 are removed, resulting in finFET silicon bodies 40 N, 40 P, each with a remaining amount of the silicon oxide layer 12 on its upper surface. The resulting structure is shown in FIG. 3A (top view) and FIG. 3B (cross sectional view). Note that because the bodies 40 N, 40 P are defined by sidewall spacers formed on a mandrel, they are in the form of loops. Various mask/etch sequences can be used at this juncture to etch away the connecting parts of the loops, to form discrete finFET bodies. For purposes of the invention the presence or absence of these loops is not material.

[0032] Then the finFET bodies 40 N, 40 P are doped in accordance with the product application. Assuming the silicon layer was originally p-doped, the finFET bodies 40 N would be masked at this juncture and n-type dopant would be applied to the finFET bodies 40 P. As shown in FIGS. 4A and 4B , after suitable body doping, a suitable silicon oxide gate dielectric 50 is formed in the finFET bodies (typically 1-2.5 nm thick, formed by thermal oxidation). Other gate dielectrics (silicon oxide and silicon nitride layers, or silicon oxy nitride, or any one of the high k gate oxide dielectrics that have been recently proposed such as halfnium oxide, aluminum oxide, zirconium oxide, and metal silicates) could be used. Then a gate electrode material, typically polysilicon is deposited to a thickness of 50-150 nm, and is then etched to form gates 60 having a given gate length (in this orientation, the width of the gate 60 in the vertical plane of FIG. 4A ) of 7-180 nm.. Gate length is a critical parameter in determining the speed and proper function of FETs and, in particular, FinFETs. The gates are oriented along the reference axes, and thus control of the gate length is not impaired by the off-axis orientation of the finFET bodies. Moreover, note that this and all subsequent mask and etching steps are carried out in alignment with the reference axis which is favorable for lithographic control.

[0033] In FIG. 5 , source and drain extensions and halos are ion-implanted into finFETs 40N, with a masking layer 70 open only over regions where nFETs are designed. A like procedure is subsequently performed for pFETs and not illustrated. Note that each extension and halo implant is carried out as a sequence of implants, at orientations of approximately 150 degrees (implant 71 ), 30 degrees (implant 72 ), 210 degrees (implant 74 , and 330 degrees (implant 73 ) with respect to the horizontal reference axis of the wafer, so as to completely dope both sides of the finFET bodies 40 N. For the n devices, the extension implants are arsenic, at a dose on the order of 1 E 15 (that is 1×10 to the 15th power ions/cm squared) and an energy of approximately 0.5-15 kEV, and the halo implants are boron (B 11 ) at a dose on the order of 4 E 13 and an energy of approximately 0.4-10 kEV. For the p device, the extension implants would be BF 2 on the order of 1 E 15 and approximately 0.05-15 kEV, and the halo implants would be phosphorus, on the order of 5 E 13 to 1 E 14, and approximately 1-40 kEV. It is to be understood that all of these values are approximations, and are both technology and product dependent.

[0034] Then, after subsequent implantation of the source and drain regions 75 , the finFETs are interconnected using conventional planarized back-end-of line (BEOL) passivation layers (e.g. boro-phosho-silicate glass, fluoro-silicate glass, and low-k dielectrics such as those sold under the trade names SiLK and Black Diamond) and conductors 80 (doped silicon, aluminum, refractory metals and refractory metal alloys, copper and copper-based alloys). These structures can be single or dual Damascene (in which both the interconnecting stud and the metal line are formed by defining a via or groove into which the metal is deposited and subsquently planarized), or any other BEOL integration scheme that produces an interconnect density consistent with the density of the finFET bodies.

[0035] Utilizing the process as set forth above, an inverter circuit can be formed having a topology as shown in FIG. 6 . Note that the gate electrodes 60 are coupled to an overlaying metal stud 100 B that contacts the gate electrode landing pad 100 A. A feature of the process and structure of the invention is that the invention maximizes carrier mobility of the n and p devices while providing orthonormal shapes on all design levels except for the mandrel definition mask. Critical image control for the fins is maintained in non-orthonormal directions by use of edge-defined lithography (in this embodiment, by sidewall-image-transfer (SIT) using the sidewall spacers as masks). Note that in the invention, carrier mobility has been maximized without the introduction of extra masking steps or other process complexity. At the same time, while density is compromised somewhat by the introduction of non-orthonormal features, the density reduction is less than that provided by prior art approaches because it is applied at a single mask level (the mask that defines the freestanding bodies), and is compensated for by the combination of increased carrier mobility for both the n and p devices and the use of freestanding FET bodies.

[0036] In FIG. 7 a second embodiment of the present invention is illustrated. In this embodiment, the detailed layout differs from that of the previous embodiment in that the freestanding FET bodies 40 NA, 40 PA are in directions orthonormal to the cardinal reference axes of the wafer, except in the immediate vicinity of where the gate electrodes and the FET bodies intersect. This “dogleg” layout topology provides a tradeoff; it increases density over the FET density provided by the first embodiment, but introduces process complexity to the masking step that defines the polysilicon mandrels. For example, this shape could be formed by carrying out two sequential masking/etching steps on the silicon nitride mandrels, offset from one another by the angle of the dogleg.

[0037] FIG. 8 illustrates the relationship between the effective channel length of the freestanding FETs fabricated according to the present invention with respect to that of a conventionally defined finFET. Gate-level lithography often limits the minimum image by which FET gate length is determined. Since the inventive FinFET silicon 90 fin crosses the gate at 67.5 degrees instead of the usual 90 degrees, the minimum physical length of the channel plane covered by the gate will be secant (22.5 degrees) times that of the conventional FET, or 9% greater. Diffusion of the source and drain regions conventionally extend under the gate edge approximately 10% (that is, of the total length of the gate, approximately 10% of it overlays e.g. a source region); therefore, in order to achieve LEFF of comparable value in the finFET of FIG. 8 , processing would have to be modified to increase the distance of the source and drain diffusion under the gate to approximately 15%. As a practical matter the source and drain extensions of the invention can be further diffused beneath the edges of the gate electrode 93 using various techniques known in the art (e.g. extending the time or raising the temperature of the implant over conventional parameters). Thus the electrically effective channel length, LEFF, which determines the electrical behavior of the inventive FinFET, can be maintained equal to that of the conventional FinFET.

[0038] It will be readily apparent that various changes and/or modifications could be made herein without departing from the spirit and scope of the present invention as defined in the following claims. For example, while the invention has been described with reference to maximizing mobility for both the n and p devices, there may be product applications (such as SRAM cells) for which it may be desireable to maximize the carrier mobility for one device and not the other. Moreover, as previously stated, the invention applies to the fabrication of other devices such as capacitors or resistors, in which the freestanding body defines a semiconductor carrier path, and the “gate” consititutes a passing conductor or interconnecting conductor (depending on the nature of the element being fabricated).