DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS OF THE INVENTION

[0045] As previously mentioned, there is a need for a novel spin valve transistor device having insulating hard bias stabilization. Referring now to the drawings, and more particularly to FIGS. 2 through 9 , there are shown preferred embodiments of the method and structures according to the present invention, in which there is provided a spin valve transistor 1 comprising a magnetic field sensor 3 , an insulating layer 25 adjacent to the magnetic field sensor 3 , and a hard bias layer 30 adjacent to the insulating layer 25 .

[0046] The processing steps involved in manufacturing the are sequentially illustrated in FIGS. 2 through 8 , wherein there is shown in FIG. 2 a magnetic field sensor 3 comprising a base region 15 , a collector region 20 adjacent the base region 15 , an emitter region 5 adjacent the base region 15 , and a barrier region 10 located between the base region 15 and the emitter region 5 . A resist layer 8 is further shown adjacent the metal emitter 5 , which defines the track width of the sensor 3 .

[0047] As seen in FIG. 3 , the device 3 is defined by milling at various mill angles for sensor sidewall definition. Then, as illustrated in FIG. 4 , the insulator 25 is deposited around the remaining sensor 3 . The insulator 25 comprises an antiferromagnetic material, such as NiO or alumina and is operable to electrically isolate the emitter 5 from the free layer (base) 15 .

[0048] The magnetic field sensor 3 allows hot electrons emitted from the emitter 5 to travel through to the free layer 15 , and to reach the collector 20 , which collects the magnetocurrent (collects the electrons). The free layer 15 preferably comprises a soft ferromagnetic material such as NiFe, CoFe, Si, Cu, TB ₂ . In operation, the device 3 acts as a hot spin electron filter, whereby the barrier 10 between the emitter 5 and the free layer 15 operates to selectively allow the hot electrons to pass on through to the free layer 15 , and then on through to the collector 20 . The barrier layer 10 is preferably comprised of aluminum oxide, and is generally less than ten angstroms in thickness.

[0049] Next, as best seen in FIG. 5 , the resist 8 is either removed via a liftoff process or chemical mechanical polish (CMP) assisted liftoff to break the sidewall redeposition of metal on the side of the resist to allow a solvent to clean to the entire surface of the wafer 3 . At the air bearing surface (ABS), the sensor 3 would have insulation via the antiferromagnetic layer 25 adjacent to the sensor 3 .

[0050] FIG. 6 shows the next step in the processing, whereby a hard bias magnetic layer 30 is deposited adjacent to the insulator layer 25 . Then, a second antiferromagnetic insulating layer 33 , preferably comprising alumina, is deposited adjacent the hard bias layer 30 , wherein the hard bias layer 30 is sandwiched between the insulating layer 25 and the second insulating layer 33 . The thickness of the hard bias layer 30 serves to stabilize the device 3 , and moreover, allows the magnetization of the free layer 15 to point towards the hard bias layer 30 , that is parallel to the ABS plane. Thus, when the spin valve transistor 1 is not functioning, the device 3 is in a known state (magnetization of the free layer 15 is parallel to the ABS plane). This is advantageous over conventional devices because the free layer 15 is prevented from wandering, and in fact, is positioned (magnetization is pointed) in the correct position, as further explained below.

[0051] The scattering of electrons within the free layer 15 is dependent upon the orientation of the magnetization within the free layer 15 . For example, if the magnetization is pointing upwards in the free layer 15 (parallel to the ABS plane), as provided by the present invention, then the electrons are not scattered as much and the device 3 is in a known state. However, if the magnetization is pointing downwards, as with conventional devices, then there is little stability with regard to the magnetic field sensor. Therefore, the hard bias layer 30 of the present invention stabilizes the sensor 3 .

[0052] Next, in a preferred embodiment illustrated in FIG. 7, a ferromagnetic layer 35 is deposited over the hard bias layer 30 and acts as a shield 35 to the sensor 3 . After this, a ferromagnetic shield 35 is deposited over the second insulating layer 33 . The ferromagnetic shield 35 covers a majority of the sensor 3 including parts of the sides to minimize side reading. Moreover, the shield 35 also acts as the electrical connection for the emitter 5 . The shield 35 does not channel magnetization, but still allows for an electrical connection to occur. Moreover, the shield 35 provides a connection to an external lead (not shown).

[0053] The thickness of the hard bias layer 30 is a factor with regard to pinning strength. Pinning strength relates to the relative freedom with which the electrons move in the free layer. The hard bias layer 30 cannot be too thick because this would increase the space between the shield 35 and the free layer 15 , which would essentially pin the free layer 15 preventing it from flipping freely. Likewise, a hard bias layer 30 , which is too thin results in not enough pinning strength, causing an unstable sensor 3 .

[0054] Similarly, an insulator 25 or second insulating layer 33 , which is too thick also increases the spacing between the free layer 15 and the shield 35 , thereby effecting the pinning strength. Thus, preferably the hard bias layer 30 is approximately at least three times the thickness of the base region 15 (and preferably four times the thickness of the base region 15 ), wherein the base region 15 is approximately 30-40 angstroms, the hard bias layer 30 is approximately 120-160 angstroms, and the insulator 25 is approximately 100-800 angstroms in thickness.

[0055] A preferred method of manufacturing a spin valve transistor 1 is illustrated in the flow diagram of FIG. 8 , wherein the method comprises placing 100 an antiferromagnetic insulating layer 25 adjacent a magnetic field sensor 3 , and positioning 200 a magnetic hard bias layer 30 adjacent the insulating layer 25 , wherein the magnetic field sensor 3 comprises a base region 15 , a collector region 20 adjacent the base region 15 , an emitter region 5 adjacent the base region 15 , and a barrier region 10 located between the base region 15 and the emitter region 5 . The method further comprises laying 250 a second insulating layer 33 adjacent the hard bias layer 30 , and placing 350 a ferromagnetic layer 35 over the second insulating layer 33 .

[0056] A perspective view of a current tunnel transistor, embodied as a spin valve transistor, according to an embodiment of the invention is illustrated in FIG. 9 . In this view, the current tunnel transistor is shown without a hard bias layer 30 . As indicated the current tunnel transistor comprises a collector substrate 20 , preferably comprising silicon, with an oxide barrier layer 10 disposed thereon. Above the barrier layer 10 is a base layer (free layer) 15 . Another tunnel barrier layer 10 is configured over the base layer 15 , wherein this tunnel barrier layer 10 creates a separation between the base layer 15 and the emitter (top lead) 5 . A lead connection 35 , which may be embodied as a ferromagnetic shield 35 is positioned over the emitter region 5 . A base lead 36 is positioned over the base 15 . As indicated, the stripe height hs is defined by the dimensions of the emitter 5 , while the track width WT is defined by the dimensions of the emitter 5 , base 15 , and collector 20 .

[0057] The spin valve transistor is manufactured using several lithographic steps. In FIG. 10 , the collector substrate 20 is shown with the insulating oxide barrier 10 disposed thereon. A resist pattern 43 is used to remove a portion of the oxide barrier 10 , which creates a via 44 down to the semiconductor substrate 20 , which is shown in FIG. 11 . The removal of the oxide barrier 10 may be performed using conventional etching techniques. The air bearing surface of the resulting sensor structure is represented by a dotted line 11 in FIGS. 12 ( a ) and 12 ( b ) as well as in the subsequent drawings.

[0058] In FIG. 13 ( a ) a sensor stack 18 is placed over the insulating barrier 10 and into the via 44 . The sensor stack 18 comprises the emitter region 5 positioned over the base layer 15 . The top plan view of FIG. 13 ( b ) illustrates the upper cap of the sensor stack 18 , which is actually the emitter surface 5 . Next, as depicted in FIGS. 14 ( a ) and 14 ( b ), another resist 46 is used to pattern the sensor stack 18 , where portions of the emitter region 5 are removed using known techniques such as ion milling or reactive ion etching. This exposes the base layer 15 and defines the stripe height hs of the device. Thereafter, as shown in FIGS. 15 ( a ) and 15 ( b ), an insulator 25 , such as alumina, is filled in the areas over the exposed base layer 15 .

[0059] In the next stage of processing illustrated in FIGS. 16 ( a ) and 16 ( b ), a resist 47 is used to pattern the transistor device along the track width location WT of the device. The resist pattern 47 is best seen in FIG. 16 ( b ) along with exposed portions of the insulator 25 and emitter 5 . After the resist 47 is removed a hard bias layer 30 and second insulator layer 33 are deposited over the first insulator layer 25 . Collectively, the first insulator 25 , hard bias layer 30 , and second insulator layer 33 form a stack 29 , which is seen in FIG. 17 ( a ), which illustrates the device in the ABS plane, and FIG. 17 ( b ), which illustrates a top plan view of the device.

[0060] In FIGS. 18 ( a ) (viewed in the ABS plane) and 18 ( b ) portions of the stack 29 are removed, and the device is configured such that the only portion of the emitter 5 and base 15 remaining is located between the insulator/bias/insulator stack 29 . A resist 48 is used to pattern the device and an insulator 38 fills the exposed portions of the device. FIGS. 19 ( a ) and 19 ( b ) illustrate the device with a resist 49 used to pattern a via 56 to the base layer 15 and a via (not shown) to the collector 20 . Thereafter, after patterning is completed, the transistor device is plated with a top lead 35 and base lead 36 , wherein both leads 35 , 36 preferably comprise NiFe. Other leads, such as the collector lead (not shown) are also included.

[0061] The advantages of the present invention are several. First, the present invention can stabilize a free layer 15 in a highly sensitive read head device 1 . Also, the present invention can create a read head in a shielded environment. Moreover, the present invention provides a spin valve transistor 1 with insulating hard bias stabilization that is adjacent to a magnetic field sensor 3 , wherein the sensor 3 has its track width and stripe height defined by separate lithography steps. The present invention also has three separate output connection pads 45 on top of the slider body 40 . The present invention further has a magnetic shield 35 that covers the sensor device 3 in an asymmetric shape relative to the plane of the deposited end of the substrate, thereby stabilizing the device 3 .

[0062] While the invention has been described in terms of preferred embodiments, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the appended claims.