DETAILED DESCRIPTION OF THE INVENTION

[0041] Embodiments in accordance with the invention are described herein with reference to FIGS. 1 - 13 .

[0042] It should be understood that FIGS. 1 and 2 , depicting integrated circuit devices, are not meant to be actual plan or cross-sectional views of any particular portion of actual integrated circuit devices. In actual devices, the layers will not be as regular and the thicknesses may have different proportions. The various layers in actual devices often are curved and possess overlapping edges. The figures instead show idealized representations which are employed to explain more clearly and fully the method of the invention than would otherwise be possible. Also, the figures represent only one of innumerable variations of ferroelectric and dielectric devices that could be fabricated using the method of the invention. For example, FIG. 1 depicts a portion of a ferroelectric memory 100 containing a switch in the form of a field effect transistor 114 in electrical connection with a ferroelectric capacitor 130 . Although the ferroelectric element 126 depicted in FIG. 1 is substantially above switch element 114 , the invention is also useful, for example, to fabricate a thin film of layered superlattice material in a memory cell or other integrated circuit device disposed in a sideways or vertical orientation with respect to the horizontal plane of FIG. 1 . In addition, a method in accordance with the invention may also be used to fabricate a ferroelectric FET memory in which the ferroelectric element comprising layered superlaftice material is incorporated in the switch element. Such a ferroelectric FET, as depicted in FIG. 2 , was described in U.S. Pat. No. 5,523,964 issued Jun. 4, 1996 to McMillan et al. and U.S. patent application Ser. No. 09/365,628 filed Aug. 2, 1999.

[0043] FIG. 1 shows a cross-sectional view of an exemplary nonvolatile ferroelectric memory 100 fabricated in accordance with the invention. The general manufacturing steps for fabricating integrated circuits containing MOSFETs and ferroelectric capacitor elements are described in U.S. Pat. No. 5,466,629, issued Nov. 14, 1995 to Mihara et al., and U.S. Pat. No. 5,468,684, issued Nov. 21, 1995 to Yoshimori et al. General fabrication methods have been described in other references also, and are well known in the art. Therefore, the elements of the circuit of FIG. 1 will be simply identified here.

[0044] FIG. 1 shows a ferroelectric random access memory cell 100 . Memory cell 100 includes a transistor switch 114 and a capacitor 130 formed on a semiconductor wafer 101 . In the embodiment shown, transistor 114 is a MOSFET and includes source region 106 , drain region 108 , a channel region 107 , gate insulating layer 110 and gate electrode 112 . Capacitor 130 includes bottom electrode 124 , ferroelectric layer 126 , and top electrode 128 . A field oxide region 104 is formed on a surface of a silicon substrate 102 . Source region 106 and drain region 108 are formed separately from each other within silicon substrate 102 . A gate insulating layer 110 is formed on silicon substrate 102 between the source and drain regions 106 and 108 . Further, a gate electrode 112 is formed on gate insulating layer 110 .

[0045] A first interlayer dielectric layer (ILD) 116 made of BPSG (boron-doped phospho-silicate glass) is formed on substrate 102 and field oxide region 104 . ILD 116 is patterned to form vias 117 , 118 to source region 106 and drain region 108 , respectively. Vias 117 , 118 are filled to form plugs 119 , 120 , respectively. Plugs 119 , 120 are electrically conductive and typically comprise tungsten or polycrystalline silicon. Diffusion barrier material is deposited and patterned on ILD 116 to form diffusion barriers 121 , 122 in electrical contact with plugs 119 , 120 , respectively. Diffusion barriers 121 , 122 are made of, for example, titanium nitride, and typically have a thickness of 10 nm to 20 nm. Diffusion barrier layers, such as titanium nitride, inhibit the diffusion of chemical species between the underlying and overlying layers of memory 100 .

[0046] As depicted in FIG. 1, a bottom electrode layer 124 made of platinum and having a thickness of 100 nm is deposited on diffusion barrier layer 121 . Then a ferroelectric thin film 126 of layered superlattice material is formed in accordance with the invention on bottom electrode layer 124 . A top electrode layer 128 , made of platinum and having a thickness of 100 nm, is formed on ferroelectric thin film 126 .

[0047] Wafer substrate 102 may comprise silicon, gallium arsenide or other semiconductor, or an insulator, such as silicon dioxide, glass or magnesium oxide (MgO). The bottom and top electrodes of ferroelectric capacitors conventionally contain platinum. It is preferable that the bottom electrode contains a non-oxidized precious metal such as platinum, palladium, silver, and gold. In addition to the precious metal, metal such as aluminum, aluminum alloy, aluminum silicon, aluminum nickel, nickel alloy, copper alloy, and aluminum copper may be used for electrodes of a ferroelectric memory. Adhesive layers (not shown), such as titanium, enhance the adhesion of the electrodes to adjacent underlying or overlying layers of the circuits. Hydrogen barrier layer 132 is formed above ferroelectric capacitor 130 and MOSFET 114 , to cover the surface area above memory cell 100 . The composition, fabrication and etching of hydrogen barriers are known in the art. See, for example, U.S. Pat. No. 6,225,565 B1 issued May 1, 2001 to Cuchiaro et al., and U.S. Pat. No. 6,180,971 issued Jan. 30, 2001 to Maejima, which are hereby incorporated by reference.

[0048] A second interlayer dielectric layer (ILD) 136 made of NSG (nondoped silicate glass) is deposited to cover ILD 116 , diffusion barrier layer 121 , and ferroelectric capacitor 130 . A doped silicate glass, such as FSG (fluorosilicate glass), PSG (phospho-silicate glass) film or a BPSG (boron phospho-silicate glass) film could also be used in layer 136 . ILD 136 is patterned to form a via 137 through barrier 132 to plug 119 . A metallized wiring film 140 is deposited to cover ILD 136 and fill via 137 and then patterned to form plug 137 and source electrode wiring 142 . Top electrode wiring (not shown in cross-section) makes electrical connection to top plate-electrode 128 . Wirings 140 , 142 preferably comprise Al—Si—Cu standard interconnect metal with a thickness of about 200 nm to 300 nm. Typically, a film of adhesion material (not shown), for example, comprising Ti and TiN, is deposited on the substrate and wiring film 140 is then formed on the adhesion film. Dielectric layer 150 covers wiring film 140 and ILD 136 .

[0049] FIG. 2 shows a cross-sectional view of a portion of a ferroelectric FET memory 210 as may be fabricated using a method in accordance with an embodiment of the invention. Memory 210 comprises a ferroelectric FET 250 formed on a wafer 211 , comprising a standard semiconductor material 212 , preferably a p- 100 silicon material. A semiconductor substrate 214 comprises a highly doped source region 216 and a highly doped drain region 218 , which are formed about a doped channel region 220 . Doped source region 216 , drain region 218 and channel region 220 are preferably n-type doped regions, but also may be p-type regions formed in an n-type semiconductor. Semiconductor substrate 214 typically also includes a gate oxide 222 usually located above channel region 220 , but which can extend beyond channel region 220 to cover parts of source region 216 , drain region 218 and other parts of semiconductor material 212 . Typically, gate oxide 222 is formed from semiconductor material 212 during high temperature process steps. When semiconductor material 212 is silicon, then gate oxide 222 usually comprises silicon dioxide. An interface insulator layer 224 may be formed above semiconductor substrate 214 above channel 220 , usually on gate oxide 222 . A ferroelectric thin film 226 , formed in accordance with the invention, is located above interface insulator layer 224 and channel region 218 , usually on interface insulator layer 224 . Gate electrode 230 is formed above ferroelectric thin film 226 , usually on ferroelectric thin film 226 .

[0050] U.S. Pat. No. 5,519,234 issued May 21, 1996 to Paz de Araujo et al. discloses that layered superlattice compounds, such as strontium bismuth tantalate, have excellent properties in ferroelectric applications as compared to the best prior materials and have high dielectric constants and low leakage currents. U.S. Pat. No. 5,434,102 issued Jul. 18, 1995 to Watanabe et al. and U.S. Pat. No. 5,468,684 issued Nov. 21, 1995 to Yoshimori et al. describe processes for integrating these materials into practical integrated circuits.

[0051] The layered superlattice materials may be summarized generally under the formula: 1 $\begin{array}{cc}{\mathrm{A1}}_{\mathrm{w1}}^{+\mathrm{a1}}{\mathrm{A2}}_{\mathrm{w2}}^{+\mathrm{a2}}\dots {\mathrm{Aj}}_{\mathrm{wj}}^{+\mathrm{aj}}{\mathrm{S1}}_{\mathrm{x1}}^{+\mathrm{s1}}{\mathrm{S2}}_{\mathrm{x2}}^{+\mathrm{S2}}\dots {\mathrm{Sk}}_{\mathrm{xk}}^{+\mathrm{sk}}{\mathrm{B1}}_{\mathrm{y1}}^{+\mathrm{b1}}{\mathrm{B2}}_{\mathrm{y2}}^{+\mathrm{b2}}\dots {\mathrm{Bl}}_{\mathrm{yl}}^{+\mathrm{bl}}Q_z^{-q}& \left(1\right)\end{array}$

[0052] where A 1 , A 2 . . . Aj represent A-site elements in the perovskite-like structure, which may be elements such as strontium, calcium, barium, bismuth, lead, and others; S 1 , S 2 . . . Sk represent superlaffice generator elements, which usually is bismuth, but can also be materials such as yttrium, scandium, lanthanum, antimony, chromium, thallium, and other elements with a valence of +3; B 1 , B 2 . . . BI represent B-site elements in the perovskite-like structure, which may be elements such as titanium, tantalum, hafnium, tungsten, niobium, zirconium, and other elements; and Q represents an anion, which generally is oxygen but may also be other elements, such as fluorine, chlorine and hybrids of these elements, such as the oxyfluorides, the oxychlorides, etc. The superscripts in Formula (1) indicate the valences of the respective elements; for example, if Q is oxygen, then q=2. The subscripts indicate the number of moles of the material in a mole of the compound, or in terms of the unit cell, the number of atoms of the element, on the average, in the unit cell. The subscripts can be integer or fractional. That is, Formula (1) includes the cases where the unit cell may vary uniformly throughout the material; for example, in SrBi ₂ (Ta _0.75 Nb _0.25 ) ₂ O ₉ , 75% of the B-sites are occupied by strontium atoms, and 25% of the B-sites are occupied by barium atoms. If there is only one A-site element in the compound, then it is represented by the “A 1 ” element and w 2 . . . wj all equal zero. If there is only one B-site element in the compound, then it is represented by the “B 1 ” element, and y 2 . . . yl all equal zero, and similarly for the superlattice generator elements. The usual case is that there is one A-site element, one superlattice generator element, and one or two B-site elements, although Formula (1) is written in the more general form since the invention is intended to include cases where either of the sites and the superlattice generator can have multiple elements. The value of z is found from the equation:

( a 1 w 1 + a 2 w 2 . . . + ajwj )+( s 1 ×1+ s 2 × 2 . . . + skxk )+( b 1 y 1 + b 2 y 2 . . . + blyl )=qz. (2)

[0053] Formula (1) includes all three of the Smolenskii type compounds discussed in U.S. Pat. No. 5,519,234 issued May 21, 1996 to Paz de Araujo et al., referenced above. The layered superlattice materials do not include every material that can be fit into Formula (1), but only those which form crystalline structures with distinct alternating layers upon heating.

[0054] U.S. Pat. No. 5,803,961 issued Sep. 8, 1998 to Azuma et al. discloses that mixed layered superlattice materials, such as strontium bismuth tantalum niobate, can have even more improved properties in ferroelectric applications. The mixed layered superlattice materials are typically characterized by nonstoichiometric amounts of A-site and B-site elements. For example, a preferred precursor used in accordance with the invention comprises metal organic precursor compounds having metals in relative molar proportions corresponding to the stoichiometrically unbalanced formula Sr _0.8 Bi ₂ (Ta _0.7 Nb _0.3 ) ₂ O _8.8 .

[0055] Currently, ferroelectric layered superlaftice materials, like the metal oxides SrBi ₂ Ta ₂ O ₉ (SBT), SrBi ₂ (Ta _1-x Nb _x ) ₂ O ₉ (SBTN), where 0≦x≦1, and particularly Sr _a Bi _b (Ta _1-x Nb _x ) _c O _{[9+(a-1)+(b-2)(1.5)+(c-2)(2.5)]} , where 0.7≦a≦1, 2≦b≦2.2, 0≦x≦0.3 and 1.9≦c≦2.1 (SBTN), are being used and are under further development for use as a capacitor dielectric in nonvolatile memory applications, such as in FeRAMs and nondestructible read-out ferroelectric FETs. Polycrystalline thin films of these layered superlattice materials, as well as other layered superlattice materials represented by Formula (1), may be fabricated and used in accordance with the invention.

[0056] Methods in accordance with the present invention are also generally useful for fabrication of integrated circuits containing metal oxide thin films, including but not limited to, ABO ₃ -type perovskite metal oxides. In the general formula ABO ₃ , A and B are cations and O is the anion oxygen. The term is intended to include materials where A and B represent multiple elements; for example, it includes materials of the form A′A″BO ₃ , AB′B″O ₃ , and A′A″B′B″O ₃ , where A′, A″, B′ and B″ are different metal elements. Preferably, A, A′, A″, are metals selected from the group of metals consisting of Ba, Bi, Sr, Pb, Ca, and La, and B, B′, and B″ are metals selected from the group consisting of Ti, Zr, Ta, Mo, W, and Nb. A, A′, and A″ are collectively referred to herein as A-site materials. B, B′, and B″ are collectively referred to herein as B-site materials. Some perovskite metal oxides, such as PZT and PLZT, are classified as ferroelectrics, though some may not exhibit ferroelectricity at room temperature. Others do not exhibit ferroelectric properties, but have high dielectric constants and are useful in high dielectric constant capacitors. For example, barium strontium titanate (“BST”) and other ABO ₃ -type perovskite metal oxides, are used as capacitor dielectric in DRAMs. Preferably, BST is fabricated in accordance with the invention by blending excess A-site and B-site materials in a BST-precursor solution, as described in U.S. Pat. No.6,025,619, issued Feb. 15, 2000, to Azuma et al., which is hereby incorporated by reference. The excess A-site and B-site materials increase the dielectric constant of the dielectric layer of the capacitorwith little or no effect on leakage current. These BST solutions are typically prepared by reacting barium with 2-methoxyethanol and 2-ethylhexanoic acid, adding strontium, allowing the mixture to cool, and adding titanium isopropoxide and 2-methoxyethanol.

[0057] An RTP operation in accordance with the invention is generally conducted in a conventional rapid thermal processing apparatus. In accordance with the invention, an initial RTP operation is generally at least partially conducted in an oxygen-containing atmosphere to enhance formation of the metal oxide bonds in polycrystalline layered superlattice materials and other ferroelectric or dielectric compounds. It is contemplated, however, that an oxygen-free unreactive atmosphere may be used for a significant part of the holding time.

[0058] A method in accordance with the invention includes rapidly ramping the temperature in the oven of an RTP apparatus up to the hold temperature. It is contemplated, however, that a plurality of hold temperatures may be used. As a result of the RTP, the annealing of the layered superlattice material, or other dielectric or ferroelectric metal oxide, occurs substantially at the hold temperature, rather than the lower temperature region. That is, it is believed that by using RTP, the crystallization process proceeds directly into the high temperature crystalline phase, thus reducing or eliminating altogether the generation of the low temperature crystalline phases, which are referred to in the art as the “fluorite phases”. The actual ramping rate is typically in the range of from 10° C. to 150° C. per second, preferably about 100° C. per second. The term “ramp rate” applies to the rate of temperature increase experienced in the integrated circuit substrate. Typically, the hold temperature is the maximum temperature reached during the RTP. After annealing at the RTP hold temperature, the substrate may be cooled using conventional cooling techniques.

[0059] The word “substrate” can mean the underlying semiconductor material 102 , 212 on which the integrated circuit is formed, as well as any object on which a thin film layer is deposited. In this disclosure, “substrate” shall generally mean the object to which the layer of interest is applied. For example, when we are talking about a ferroelectric thin film 126 of FIG. 1 , the substrate on which it is initially deposited may include various elements, in particular, bottom electrode 124 .

[0060] The long horizontal dimensions of substrates 102 , 212 define planes that are considered to be a “horizontal” plane herein, and directions perpendicularto this plane are considered to be “vertical”. The terms “lateral” or “laterally” referto the direction of the flat plane of the semiconductor substrate, that is, parallel to the horizontal direction. Terms of orientation herein, such as “above”, “top”, “upper”, “below”, “bottom” and “lower”, mean relative to substrate 102 , 214 . That is, if a second element is “above” a first element, it means it is farther from semiconductor substrate 102 , 212 ; and if it is “below” another element, then it is closer to semiconductor substrate 102 , 214 than the other element. Terms such as “above” and “below” do not, by themselves, signify direct contact. However, terms such as “on” or “onto” do signify direct contact of one layer with an underlying layer. It is understood that thin films of layered superlattice material fabricated in accordance with the invention have various shapes and conform to various topographies and features of an integrated circuit substrate. Accordingly, thin films of layered superlattice material in accordance with the invention are formed on planar substrates, in trenches and vias, on vertical sidewalls, and in other various nonhorizontal and three-dimensional shapes.

[0061] The term “thin film” is used herein as it is used in the integrated circuit art. Generally, it means a film of less than a micron in thickness. The thin films disclosed herein are typically less than 500 nm in thickness. A thin film of layered superlaffice material fabricated by a method in accordance with the invention typically has a final thickness in a range of about from 20 nm to 300 nm, preferably in a range of about from 25 nm to 150 nm. The thin films having a thickness of about 50 nm or less are specifically designated “ultra-thin films” in this specification. These thin films and ultra-thin films of the integrated circuit art should not be confused with the layered capacitors of the macroscopic capacitor art which are formed by a wholly different process that is incompatible with the integrated circuit art.

[0062] The term “stoichiometric” herein may be applied to both a solid film of a material, such as a layered superlattice material, or to the precursor for forming a material. When it is applied to a solid thin film, it refers to a formula which shows the actual relative amounts of each element in a final solid thin film. When applied to a precursor, it indicates the molar proportion of metal atoms in the precursor. A “balanced” stoichiometric formula is one in which there is just enough of each element to form a complete crystal structure of the material with all sites of the crystal lattice occupied, though in actual practice there always will be some defects in the crystal at room temperature. For example, both SrBi ₂ (TaNb)O ₉ and SrBi ₂ (Ta _1.5 Nb _0.5 )O ₉ are balanced stoichiometric formulae. In contrast, a precursor for strontium bismuth tantalum niobate in which the molar proportions of strontium, bismuth, tantalum, and niobium are 0.9, 2.18, 1.5, and 0.5, respectively, is represented herein by the unbalanced “stoichiometric” formula Sr _0.9 Bi _2.18 (Ta _1.5 Nb _0.5 )O ₉ , since it contains excess bismuth and deficient strontium relative to the B-site elements tantalum and niobium. It is common in the art to write an unbalanced stoichiometric formula of a metal oxide in which the subscript of the oxygen symbol is not corrected to balance completely the subscript values of the metals.

[0063] The word “precursor” used herein can mean a solution containing one metal organic solute that is mixed with other precursors to form intermediate precursors or final precursors, or it may refer to a final liquid precursor solution or gas mixture, that is, the precursorto be applied to a particular surface during fabrication. The precursor as applied to the substrate is usually referred to as the “final precursor”, “precursor mixture”, or simply “precursor”. In any case, the meaning is clear from the context.

[0064] A “precursor compound” in this disclosure refers to a metal organic compound containing at least one metal that is included in the desired layered superlattice material of the thin film formed in accordance with the invention. The metal organic precursor compounds disclosed herein are useful because they can be easily dissolved in organic liquid precursor solutions, which can be stored until used. In a liquid-source misted chemical deposition (“LSMCD”) method in accordance with the invention, one or more liquid precursor solutions are atomized to form a mist that contains precursor compounds suitable for formation of the desired thin film. See, for example, U.S. Pat. No. 6,326,315 B1 issued Dec. 4, 2001 to Uchiyama etal., and U.S. Pat. No. 6,258,733 B1 issued Jul. 10, 2001 to Solayappan et al., which are hereby incorporated by reference. In embodiments in accordance with the invention utilizing a metal-organic chemical vapor deposition (“MOCVD”) technique to deposit a precursor coating on a substrate, typically one or more liquid precursor streams are vaporized, and then one or more gaseous precursor compounds flow into a CVD reaction chamber, in which a solid coating containing desired metal compounds forms on a wafer substrate. See, for example, U.S. Pat. No. 6,110,531, issued Aug. 29, 2000 to Paz de Araujo et al., which is hereby incorporated by reference. The composition of a precursor solution may be described in two ways. The actual dissolved metal organic precursor compounds (solutes) and solvents and concentrations may be specified; or, for the sake of clarity, the stoichiometric formula representing the composition of the final oxide compound to be formed with the precursor may be specified. Similarly, a precursor compound may be described using its name or stoichiometric formula, or it may simply be identified by the metal atoms it contains.

[0065] Metal organic precursor compounds and liquid precursor solutions used in accordance with the invention can be manufactured reliably. Their composition can be easily controlled and varied, if necessary. They can be safely stored for long periods, up to six months. They are relatively nontoxic and nonvolatile, compared with many precursors of the prior art.

[0066] Thin film layers formed in accordance with the invention have smooth, continuous and uniform surfaces, even when not planar, and they can be reliably fabricated to have thicknesses in the range of from 25 nm to 300 nm, maintaining important structural and electrical characteristics. The reduced heating time at elevated temperature of a low-thermal-budget technique reduces the formation of hillocks and other non-uniformities at the surfaces of deposited layers. The resulting enhanced smoothness improves interfacial contacts and inhibits electrical shorting.

[0067] It should be understood that the specific processes and electronic devices described herein are exemplary; that is, the invention contemplates that the layers in FIGS. 1 and 2 may be made of many other materials than those mentioned above and described below. There are many other variations of the method of the invention than can be included in a document such as this, and the method and materials may be used in many other electronic devices other than integrated circuit devices 100 and 210 .

[0068] In general, some form of heating or annealing of a deposited metal-containing film in oxygen at elevated temperature is necessary for desired formation and crystallization of the desired metal oxide material, in particular for crystallization of layered superlattice material. An important feature of embodiments of the invention is that the total heating times at elevated temperature are minimized compared to the prior art. In certain embodiments described in detail in this specification, RTP treatments are conducted in oxygen-containing gas. In otherembodiments described herein, however, RTP is conducted in an oxygen-containing gas for part of the total thermal-budget time, followed by annealing in an unreactive gas. The term “elevated temperature” as used herein generally refers to a temperature in a range of about from 500° C. to 900° C., typically in excess of about 550° C. The term “gas” is used in its broader sense of being either a pure gas or a mixture of several gases. The term “oxygen-containing” means that the relative amount of oxygen present is not less than one mole-percent. It is believed that heating at about 500° C. or higher is necessary to achieve the activation energies associated with crystallization of layered superlattice material.

[0069] Terms such as “heating”, “drying”, “baking”, “rapid thermal process” (“RTP”), “furnace anneal” (“FA”), and others all involve the application of heat. For the sake of clarity, the various terms are used in the art to distinguish certain techniques and method steps from one another. In this specification, the terms “drying” and “baking” are used practically synonymously. The terms “heat”, “heating”, and related terms generally designate heating processes conducted in a temperature range of about from 500° C. to 900° C., and include RTP and furnace-annealing techniques. A rapid thermal processing, RTP, technique in accordance with the invention is distinct from other heating techniques in being characterized by a very rapid rise in ambient temperature and in the temperature of the heated object, typically at an actual ramp rate of 10° C. to 200° C. per second. It is further understood that one skilled in the art may accomplish a desired process result using a baking, heating, or RTP-heating technique as disclosed herein, while referring to the technique with a term different from the one used herein.

[0070] A method in accordance with the invention for fabricating integrated circuit memories generally includes at least one RTP-heating of a coating of ferroelectric precursor compounds before deposition of a top-electrode layer on the ferroelectric layer, and generally further includes at least one RTP-heating of the ferroelectric layer after deposition of the top-electrode layer. In this specification, an RTP treatment before deposition of a top-electrode layer is referred to as a “pre-top-electrode” RTP, or a “pre-TE” RTP. Similarly, an RTP treatment after deposition of a top-electrode layer is referred to as a post-top-electrode RTP, or a “post-TE” RTP. In this specification, when reference is made to heating “using rapid thermal processing”, it is understood that RTP is included, but that the heating is not necessarily exclusively by RTP.

[0071] The terms “liquid coating”, “precursor coating”, “coating” and similar terms in this specification generally designate a liquid or solid coating containing metal atoms in stoichiometric amounts for forming metal-oxide ferroelectric layered superlaftice material upon heating in accordance with the invention. In certain embodiments, particularly in embodiments utilizing a liquid deposition technique, a liquid coating initially possesses essentially the same chemical composition as the precursor solutions deposited on the substrate. During drying and heating steps, the chemical composition and state of a liquid coating change. In this specification, such a deposited coating is generally denoted as a precursor coating, an “FE coating” or simply a “coating”. Similarly, in embodiments utilizing an MOCVD technique, a coating as deposited on a substrate in the CVD reaction chamber typically has a chemical composition different from the chemical composition of the initial gaseous precursor streams entering the reaction chamber. Such a deposited coating is also generally denoted as a “precursor coating”, an “FE coating” or a coating.

[0072] After initial deposition on a substrate, a coating containing metal atoms in stoichiometric amounts for forming layered superlattice material achieves desired ferroelectric and other electronic properties only during the course of subsequent fabrication processes in accordance with the invention. For clarity and identification purposes in this specification, the terms “coating”, “precursor coating”, “FE coating”, “FE” and similar terms are used broadly to refer to the layer of metal-containing material disposed on an integrated circuit substrate, typically on a bottom electrode layer, that is treated in accordance with the invention to form a thin film of ferroelectric layered superlattice material. The terms “ferroelectric film”, “ferroelectric thin film”, “ferroelectric layer” and similar terms in this specification generally refer to the element resulting from heat treatment of a metal-containing coating in accordance with the invention, such as pre-TE RTP and post-TE RTP. The use in this specification of the terms “FE coating” and related terms, on the one hand, and of the terms “ferroelectric thin film” and related terms, on the other hand, overlap somewhat; nevertheless, their meaning is clear from the context in which they are used.

[0073] Individual precursor compounds of a precursor solution for fabricating a layered superlattice material thin film may be selected from the group including metal beta-diketonates, metal polyalkoxides, metal dipivaloylmethanates, metal cyclopentadienyls, metal alkoxycarboxylates, metal carboxylates, metal alkoxides, metal ethylhexanoates, octanoates, and neodecanoates. An individual metal organic decomposition (“MOD”) precursor compound is formed, for example, by interacting each metal of a desired compound, for example, strontium, bismuth, tantalum or niobium, or an alkoxide of the metal, with a carboxylic acid, or with a carboxylic acid and an alcohol, and dissolving the reaction product in a solvent. Carboxylic acids that may be used include 2-ethylhexanoic acid, octanoic acid, and neodecanoic acid, preferably 2-ethylhexanoic acid. Alcohols that may be used include 2-methoxyethanol, 1-butanol, 1-pentanol, and 2-pentanol. Solvents that may be used include xylenes, n-octane, n-butyl acetate, n-dimethylformamide, 2-methoxyethyl acetate, methyl isobutyl ketone, and methyl isoamyl ketone, as well as many others. The metal, metal alkoxide, acid, and alcohol react to form a mixture of metal-alkoxocarboxylate, metal-carboxylate and/or metal-alkoxide, which mixture is heated and stirred as necessary to form metal-oxygen-metal bonds and boil off any low-boiling point organics that are produced by the reaction. Initial MOD precursors are usually made or bought in batches prior to their use; the final precursor mixtures are usually prepared immediately before application to the substrate. Final preparation steps typically include mixing, solvent exchange, and dilution. For example, a precursor comprising a metal 2-ethylhexanoate compound is well suited for use in a liquid deposition technique, such as a liquid spin-on technique or a liquid-source misted chemical deposition (“LSMCD”) technique. A metal 2-ethylhexanoate is well suited for use in a liquid deposition technique because the ethylhexanoates are stable in solution, have a long shelf life, form smooth liquid films, and decompose smoothly on a substrate. The ethoxyhexanoates and other metalorganic precursor compounds may be stored for periods of several months when dissolved in xylenes or n-octane.

[0074] The diagram of FIG. 3 is a flow sheet of fabrication processes of a generalized LTB method 310 in accordance with the invention utilizing a liquid-deposition technique to make a ferroelectric memory, as depicted in FIG. 1 , containing layered superlaftice material. Although method 310 of FIG. 3 is discussed herein with reference to FIG. 1 , it is clear that the method of FIG. 3 and numerous variations of the method in accordance with the invention may be used to fabricate thin films of polycrystalline layered superlattice materials of other compositions in various types of ferroelectric structures of the integrated circuit art, and generally to fabricate metal oxide thin films in integrated circuits.

[0075] In processes 312 , a semiconductor substrate is provided on which a switch is formed in processes 314 . The switch is typically a MOSFET. In processes 316 , an insulating layer is formed by conventional techniques to separate the switching element from the ferroelectric element to be formed. Using conventional processes, the insulating layer is patterned to form vias, which are filled with conductive plugs to electrically connect the switch to the memory capacitor and the rest of the integrated circuit. In processes 318 , a diffusion barrier layer is deposited on the insulating layer and patterned. Preferably, the diffusion barrier comprises titanium nitride and has a thickness of about 10 nm to 20 nm. Preferably, the diffusion barrier is deposited by a conventional sputtering method, using a titanium nitride target, although a titanium target with a nitrogen-containing sputter gas may also be used. In processes 320 , a bottom electrode is formed. Preferably, the electrode is made of platinum and aluminum and is sputter-deposited to form a layer with a thickness in a range of about 100 nm to 200 nm. In processes 322 , chemical precursors of the layered superlattice material that will form the desired ferroelectric thin film are prepared. Usually, precursor solutions are prepared from commercially available solutions containing the chemical precursor compounds. If necessary, the concentrations of the various precursors-supplied in the commercial solutions are adjusted in processes 322 to accommodate particular manufacturing or operating conditions. Preferred embodiments of a method in accordance with the invention utilize a final liquid precursor solution containing relative molar proportions of the elements strontium, bismuth, tantalum and niobium corresponding approximately to SrBi ₂ Ta ₂ O ₉ (SBT) and Sr _a Bi _b (Ta _1-x Nb _x ) _c O _{[9+(a-1)+(b-2)(1.5)+(c-2)(2.5)]} (SBTN), where 0.7≦a≦1, 2≦b≦2.2, 0≦x≦0.3 and 1.9≦c≦2.1. A liquid coating of precursor solution is applied to the substrate in processes 324 . The precursor for forming the ferroelectric thin film of layered superlattice material is applied as a coating on the bottom electrode in processes 324 . In accordance with the invention, the precursor may be applied using a conventional liquid deposition technique, such as a misted deposition method as described in U.S. Pat. No. 6,326,315 B1 issued Dec. 4, 2001 to Uchiyama et al., and U.S. Pat. No. 6,258,733 B1 issued Jul. 10, 2001 to Grant et al., or a spin-coating method. In a liquid-source misted chemical deposition (“LSMCD”) method in accordance with the invention, one or more liquid precursor solutions are atomized to form a mist that contains precursor compounds suitable for formation of the desired thin film. In some of the examples below, the precursor solution was applied using liquid spin-coating techniques. Depending on the liquid coating method used (for example, spin-on coating or misted deposition) and desired film thickness, among other factors, the concentration of a final liquid precursor coating applied to a substrate is typically in a range of about from 0.02 moles to 0.4 moles per liter. For example, a single spin-on coating of about 1 ml of 0.06 molar solution spun at 2500 rpm for 2 minutes to 3 minutes is suitable for forming an SBT film having a thickness of about 25 nm. In contrast, two spin-on coatings of about 1 ml of 0.1 molar solution spun at about 2500 rpm for 2 minutes to 3 minutes are suitable for forming an SBT film having a thickness of about 120 nm. In drying processes 326 , the substrate with the coating of liquid precursor is baked and dried at a temperature not exceeding 300° C. Preferably, the drying processes are conducted on a hot plate in substantially pure O ₂ gas, or at least in an oxygen-containing gas, for a time period not exceeding 15 minutes. Preferably, drying of each layer is conducted in two substeps. For example, in a first substep, the liquid coating is dried by baking the substrate at about 160° C. for about one minute, and in the second substep, the substrate is baked at about 260° C. for about four minutes.

[0076] When only a single coating is applied to a substrate, integrated circuit fabrication continues after drying/baking processes 326 and proceeds to RTP processes 328 . When a plurality of liquid coatings are applied in sequence to form a thin film of layered superlattice material, then either an RTP treatment of the substrate is conducted in processes 328 , or another liquid coating is applied to the substrate on the previously dried coating. Dashed flow line 327 in FIG. 3 indicates an alternative flow path of an embodiment comprising application of a plurality of liquid layers. Different variations of process flow are suitable in a method in accordance with the invention. For example, in certain embodiments, a first liquid coating is applied and baked, and a second liquid coating is applied and baked, then an RTP treatment is conducted in processes 328 , and then a third liquid coating is applied and baked, and the substrate is treated a second time using RTP.

[0077] In other embodiments comprising application of a plurality of liquid layers in accordance with the invention, process flow proceeds from baking processes 326 to RTP processes 328 after application of each coating, and then returns to processes 324 , as indicated by dashed flow line 329 . In still other embodiments involving liquid misted deposition of a liquid coating, deposition of liquid coating is interrupted one or more times so that the partial coating is dried/baked before more liquid is applied, or the partial coating is dried/baked and RTP-treated before more liquid is applied by misted deposition.

[0078] RTP treatment in processes 328 is conducted at a temperature in a range of about from 500° C. to 900° C., for a time period in the range of about from 5 seconds to 10 minutes. Preferably, the RTP is conducted at a temperature of from 550° C. to 700° C. for about 5 seconds to 30 seconds with an actual ramping rate in a range of from 10° C. to 200° C. per second, preferably about 100° C. per second. Radiation from a halogen lamp, an infrared lamp, or an ultraviolet lamp provides the source of heat for the RTP step. In the examples below, an AG Associates Model 410 Heat Pulser utilizing a halogen source at ambient atmospheric pressure was used. The RTP is performed in an oxygen-containing gas, preferably in substantially pure O ₂ gas, for at least part of the total holding time. An RTP treatment conducted in processes 328 is referred to as a pre-TE RTP. It is,believed that pre-TE RTP serves to vaporize and to burn off residual organics from the FE coating. At the same time, it is believed that the rapid temperature rise of the RTP promotes nucleation, that is, the generation of numerous crystalline grains of layered superlattice material in the dried precursor, or FE, coating. These grains act as nuclei upon which further crystallization can occur. The presence of oxygen in a pre-TE RTP treatment enhances formation of these grains.

[0079] In one aspect, a method in accordance with the invention does not include a furnace anneal of the substrate. Nevertheless, an optional furnace anneal, as known in the art, may be conducted after RTP processes 328 . A furnace anneal after processes 328 , and before processes 330 , is typically conducted at a temperature in a range of from 500° C. to 800° C. An optional furnace anneal is performed either in an oxygen-containing gas, or preferably in an unreactive gas. When a furnace anneal is conducted, furnace-annealing time does not exceed 30 minutes; typically, a furnace anneal is conducted for 30 minutes in a temperature range of about from 600° C. to 750° C.

[0080] A top electrode layer having a thickness of about 100 to 200 nm is deposited in processes 330 . Preferably, the electrode is formed by RF sputtering of a platinum single layer, but it also may be formed by DC sputtering, ion beam sputtering, vacuum deposition, or other appropriate conventional deposition process. If desirable for the electronic device design, before the metal deposition, the ferroelectric layered superlaftice material may be patterned using conventional photolithography and etching, and the top electrode is then patterned in a second process after deposition. In preferred embodiments, as indicated in FIG. 3 , and in the examples described below, the top electrode layer and the FE coating are patterned and etched together in processes 332 using conventional photolithography techniques and ion beam milling.

[0081] In processes 334 , a post-top-electrode (“post-TE”) RTP treatment of the substrate is conducted. The post-TE RTP in processes 334 is typically performed at a temperature in a range of from 500° C. to 900° C. for time duration in a range of about from 5 seconds to 30 minutes, preferably in a range of about from 550° C. to 800° C. for less than 5 minutes, and most preferably in a range of about from 5 to 30 seconds. Conducting a post-TE RTP in processes 334 in an unreactive gas, such as helium, argon, and nitrogen, achieves substantially the same result as when conducted in oxygen. Conducting a post-TE RTP in a nonreactive gas decreases exposure of the integrated circuit to oxygen at elevated temperature. In certain embodiments, it is preferable to conduct post-TE RTP treatment, as in processes 334 , prior to etching the top electrode layer.

[0082] It is believed that the solid precursor coating, or FE coating, disposed on a substrate after pre-TE RTP treatment in oxygen in one or in a sequence of processes 328 comprises oxidized amorphous material that is not yet sufficiently crystallized to ferroelectric layered superlattice material. It is further believed that post-TE RTP treatment in processes 334 serves to complete crystallization of the thin film of layered superlattice material. It is further believed that post-TE RTP treatment in processes 334 serves to release internal stress present in the top electrode and in the interface between the electrode and the ferroelectric thin film. The effect is the same whether the post-TE RTP is performed before or after the patterning processes mentioned in connection with processes 336 below. The circuit is generally completed in processes 336 , which can include a number of processes; for example, deposition of an ILD, patterning and milling, and deposition of wiring layers.

[0083] FIG. 4 is a top view of an exemplary wafer 400 on which thin film capacitors 496 , 498 and 500 fabricated on substrate 410 in accordance with the invention are shown greatly enlarged. FIG. 5 is a portion of a cross-section 505 of FIG. 4 taken through the lines 5 - 5 , illustrating thin film capacitor 500 fabricated in accordance with the invention. Section 505 includes a silicon dioxide layer 504 formed on a silicon crystal substrate 502 . Bottom electrode 508 made of platinum then is sputter-deposited on layer 504 . Layer 510 represents a ferroelectric thin film made in accordance with the invention, and layer 512 represents a top electrode made of platinum.

[0084] In the examples presented herein, ferroelectric thin film capacitors were fabricated in accordance with the invention on semiconductor wafers, as depicted schematically in FIGS. 4 and 5 . Electronic properties of representative capacitors were measured using standard techniques. In selecting a representative capacitorfor a measurement of a particular electronic property, at least three capacitors in each of four quadrants of a wafer were measured to confirm substantially uniform values of the electronic property among the wafers, and then the electronic property of one of the wafers was measured and recorded and presented herein.

EXAMPLE 1

[0085] Ultra-thin ferroelectric thin film capacitors, as depicted in FIGS. 4 and 5 , containing a thin film of strontium bismuth tantalate layered superlattice material having a thickness of approximately 25 nm, were fabricated using a low thermal budget in accordance with the invention. Electronic and ferroelectric properties, including remanent polarization, coercive field, leakage current, and fatigue characteristics of representative capacitors were measured.

[0086] Each of a series of P-type 100 Si wafer substrates 502 was oxidized to form a layer of silicon dioxide 504 . The substrate was dehydrated in a vacuum oven at 180° C. for 30 minutes. A bottom platinum electrode 508 layer having a thickness of 200 nm then was sputter-deposited on the substrate, using an argon atmosphere, 8 mTorr pressure and 0.53 amps. On each wafer, the bottom electrode layer was pre-annealed at 650° C. for 30 minutes in O ₂ gas flowing at 6 l/m, using 10 minute push-pull. A dehydration bake was conducted in a vacuum oven at 180° C. for 30 minutes.

[0087] SBT thin films were fabricated using a strontium bismuth tantalate (SBT) liquid precursor solution purchased from the Kojundo Chemical Corporation. The solution contained amounts of metal compounds corresponding to the stoichiometric formula Sr _0.9 Bi _2.2 Ta ₂ O ₉ . The 0.2 mol precursor solution contained: bismuth 2-ethylhexanoate, strontium 2-ethylhexanoate, and tantalum 2-ethylhexanoate in n-octane. The 0.2 molar solution was diluted with n-butyl acetate to 0.06 molar final precursor solution immediately before use.

[0088] On each wafer, a liquid coating of the precursor was deposited by spin-coating approximately 0.75 ml of 0.06 molar solution of the SBT-precursor on bottom electrode layer 508 at 2500 rpm for 30 seconds. This was dried by baking on a hot plate in O ₂ gas for one minute at 160° C., followed by four minutes at 260° C. The substrate then was pre-TE RTP-treated in accordance with the invention at 650° C. for 30 seconds in O ₂ gas, with a ramping rate of 100° C. per second. Thus, the contribution of the pre-TE RTP to the thermal budget was 19,500° C.-sec. The resulting thin film of SBT precursor material had a thickness of about 25 nm. Next, platinum was sputter-deposited on the SBT thin film to make a top electrode layer 512 having a thickness of about 200 nm. The top electrode and SBT layers were milled (dry etch) to form capacitors, and then ashing was performed. A post-TE RTP treatment in accordance with the invention was conducted at a hold temperature of 750° C. for 120 seconds in O ₂ gas, with a ramping rate of 100° C. per second. Thus, the cumulative heating time was about 2.5 minutes. The contribution of the post-TE RTP to the thermal budget was 90,000° C.-sec, and the total thermal budget of the fabrication method was 109,500° C.-sec. The resulting ferroelectric capacitors had a surface area of 7854 μm ² (100 μm diameter).

[0089] The process conditions are summarized here: 1

[0090] The polarization of a representative exemplary capacitor was measured at a series of voltage values and the resulting hysteresis curves are plotted in the graph of FIG. 6 . In FIG. 6 , the polarization value, in units of μC/cm ² , is plotted as a function of applied field, in units of kV/cm. When measured at 3 volts, the remanent polarization value, 2Pr, was about 10 μC/cm ₂ . At 1 volt, the remanent polarization value, 2Pr, was about 9 μC/cm ² . The coercive voltage was about 0.25 volts, which corresponds to a coercive field of about 200 kV/cm. In FIG. 7 , polarization, in units of μC/cm ² , is plotted as a function of applied voltage. Saturation voltage is the voltage at which remanent polarization, Pr, does not increase more than about ten percent even as voltage is increased without limit. FIG. 7 shows that the exemplary capacitor had a saturation voltage of about 1.1 volts. FIG. 8 is a graph of current density measured in a representative exemplary ultra-thin 25-nm capacitor, in units A/cm ² , plotted as a function of applied voltage. FIG. 8 shows that at 3 volts the leakage current was less than 10 ⁻⁶ A/cm ² , and at 1 volt it was less than 10 ⁻⁷ A/cm ² . The breakdown voltage, V _B , was about 3.7 V, corresponding to a breakdown field, F _B , of approximately 1500 kV/cm.

[0091] FIG. 9 shows the fatigue behavior of an exemplary ultra-thin 25-nm capacitor. Fatigue cycling was conducted with 10 ¹¹ square-wave cycles at 2 MHz in a field of 400 kV/cm. The remanent polarization, 2Pr, was measured at selected intervals during the fatigue cycling, and normalized with the 2Pr-value before fatigue cycling. In the graph of FIG. 9 , normalized 2Pr is plotted as a function of the number of fatigue cycles. The data in the graph of FIG. 9 indicate that there was virtually no degradation in polarizability after 10 ¹¹ square-wave cycles.

[0092] Two PUND tests were conducted using exemplary capacitors. PUND measurements are described in U.S. Pat. No. 6,281,534 B1 issued Aug. 28, 2001 to Arita et al., which is hereby incorporated by reference. In Test 1, which tested the dynamic imprint, initial PUND measurements were conducted by applying a series of unidirectional switching pulses having an amplitude of 1 volt with a rise time of 30 ns, a fall time of 30 ns, and a pulse width of one microsecond, with a pulse delay of 75 ns between pulses. Following the initial PUND-curve measurements, 10 ⁹ positive square-wave voltage imprint pulses were applied to the ferroelectric capacitors at 75° C., a frequency of 1 MHz, each pulse having an amplitude of 3 volts, resulting in a field strength of 400 kV/cm. The results of Test 1 are presented in the graph of FIG. 10 , in which normalized polarization is plotted as a function of the number of applied unidirectional pulses. The results in FIG. 10 indicate a decrease of about 3 percent to 5 percent in polarizability in both the positive and negative directions of a representative capacitor after 10 ⁹ cycles. Test 2, which tested retention/static imprint, was conducted at a storage temperature of 125° C. during 100 hours using a series of exemplary capacitors. At selected retention times, a program/read voltage of 1 volt was applied to exemplary capacitors to test static imprint characteristics. Results are presented in the graph of FIG. 11 , in which normalized 2Pr-values are plotted as a function of retention time, in units of hours. The square-shaped “retention” data points plotted in the graph of FIG. 11 show that the charge, or polarization, on a