DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0030] FIG. 3 is a circuit diagram of an ODT system according to a first embodiment of the present invention. Referring to FIG. 3 , the ODT system includes a synchronous memory device 300 in which a termination voltage port VTP, a termination resistor R-term 1 , and a switch TM are installed.

[0031] One end of the termination resistor R-term 1 is connected to a data input/output (“I/O”) port DQ, and the switch TM is connected between the other end of the termination resistor R-term 1 and the termination voltage port VTP. The switch TM is made of a transmission gate and selectively connects the other end of the termination resistor R-term 1 to the termination voltage port VTP in response to a termination enable signal TE. In FIG. 3 , PM and NM denote a pull-up transistor of an output buffer and a pull-down transistor of the output buffer, respectively, and reference numeral 31 denotes an input buffer.

[0032] More specifically, termination voltage VTTP, which is input via the termination voltage port VTP, is applied to the termination resistor R-term 1 or the application of the termination voltage VTTP is discontinued, using the switch TM. In this way, it is possible to selectively control the termination of a transmission line DB, i.e., a data bus, which is connected to the data I/O port DQ. A termination resistance value is the sum of a channel resistance value of the switch TM and a resistance value of the termination resistance R-term 1 . However, the channel resistance value of the switch TM may be so small that it can be considered negligible.

[0033] It is preferable that the number of termination voltage ports VTP is at least one. That is, the termination voltage VTTP input via the termination voltage port VTP must act as a sync and source of an electric current, and therefore, the more the termination voltage ports VTP, the better. In general, a DRAM has a configuration of ×4, ×8, ×16, or so on. Therefore, if the number of the data I/O ports DQ increases, the number of termination voltage ports VTP must also increase in order to obtain sufficient signal integrity. In this case, one termination voltage port VTP may be installed for each data I/O port DQ or one termination voltage port VTP may be installed for several data I/O ports DQ.

[0034] The termination enable signal TE may be generated using an internal signal that is enabled only in a period when input data is input during write operations of a synchronous memory device. Otherwise, the termination enable signal TE may be generated using an internal signal that is continuously enabled except during read operations of the synchronous memory device. If necessary, the termination enable signal TE may be generated using a mode register set (“MRS”) included in a synchronous memory device.

[0035] FIG. 4 is a circuit diagram of a termination enable signal generating circuit (hereinafter, ‘the first circuit’) according to a first embodiment of the present invention. Referring to FIG. 4 , the first circuit includes an NOR gate 41 , a first inverter 42 , a second inverter 43 , a first NAND gate 44 , a second NAND gate 45 , and a third inverter 46 .

[0036] The NOR gate 41 receives a signal WV or a signal TRST and receives an MRS enable signal MRS-EN. During write operations of a synchronous memory device, the signal WV indicates an effective section of input data and the signal TRST indicates that the current period is not a read period. The first inverter 42 inverts a signal output from the NOR gate 41 , and the second inverter 43 inverts a signal MRS_TE.

[0037] The first NAND gate 44 receives the MRS enable signal MRS-EN and a signal output from the second inverter 43 , and the second NAND gate 45 receives a signal output from the first inverter 42 and a signal output from the first NAND gate 44 . The third inverter 46 inverts a signal output from the second NAND gate 45 to finally generate a termination enable signal TE.

[0038] The signal WV is generated in the synchronous memory device and enabled to logic ‘high’ only when input data is input during write operations of the synchronous memory device. The signal TRST is also generated in the synchronous memory device but is continuously enabled to logic ‘high’ except during read operations of the synchronous memory device. In general, the signal TRST is used as an enable signal for enabling an output driver of a synchronous memory device.

[0039] The MRS enable signal MRS_EN is a signal output from an MRS installed in the synchronous memory device and is enabled to logic ‘high’ when the MRS is set from the outside of the synchronous memory device. The signal MRS_TE is a signal for the termination of the transmission line DB during the enabling of the MRS enable signal MRS_EN.

[0040] More specifically, the termination enable signal TE is at logic ‘high’ when the signal WV, which indicates an effective section of input data, or the signal TRST, which indicates that the current period is not a read period, is at logic ‘high’ while the MRS enable signal MRS_EN is disabled to logic ‘low’. Then, the switch TM shown in FIG. 3 is turned on to connect the termination voltage port VTP to the termination resistor R-term 1 , thereby causing the termination of the transmission line DB connected to the data I/O port DQ.

[0041] If the signal MRS_TE is at logic ‘high’ when the MRS enable signal MRS_EN is enabled to logic ‘high’, the termination enable signal TE is at logic ‘high’. In other words, when both the MRS enable signal MRS_EN and the signal MRS_TE are at logics ‘high’, the termination enable signal TE is enabled to logic ‘high’ regardless of the level of the signal WV or the signal TRST, thereby causing the termination of the transmission line DB.

[0042] FIG. 5 is a circuit diagram of a termination enable signal generating circuit (hereinafter, ‘the second circuit’) according to a second embodiment of the present invention. Referring to FIG. 5 , the second circuit includes a first inverter 51 , a first NAND gate 52 , a second NAND gate 53 , and a second inverter 54 .

[0043] The first inverter 51 inverts a signal MRS_TE. The first NAND gate 52 receives a signal WV or a signal TRST and receives a signal output from the first inverter 51 . During write operations of a synchronous memory device, the signal WV indicates an effective section of input data and the signal TRST indicates that the current period is not a read period. The second NAND gate 53 receives the signal WV or the signal TRST and receives a signal output from the first NAND gate 52 .

[0044] More specifically, if the signal WV or the signal TRST is at logic ‘low’, a termination enable signal TE is disenabled to logic ‘low’ regardless of the level of the signal MRS_TE. If the signal WV or the signal TRST is at logic ‘high’, the termination enable signal TE is enabled to logic ‘high’ when the signal MRS_TE is at logic ‘high’ but is disenabled to logic ‘low’ when the signal MRS_TE is at logic ‘low’.

[0045] FIG. 6 is a circuit diagram of an ODT system according to a second embodiment of the present invention. Referring to FIG. 6 , as compared to the ODT system according to the first embodiment, the ODT system further includes a second termination resistor R-term 2 in a memory device 600 .

[0046] One end of the second termination resistor R-term 2 is connected to a data I/O port DQ, and the other end thereof is connected to a termination voltage port VTP. Here, a resistance value of the second termination resistor R-term 2 is considerably larger than that of a first resistor R-term 1 .

[0047] In detail, if the termination of a transmission line DB is enabled only during write operations of the memory device 60 , the transmission line DB is floated in periods, except for a read period, other than a write period, i.e., in periods other than read and write periods. However, during new write operations, it takes a predetermined time to place the transmission line DB at a termination level, thus weighing down a system.

[0048] To solve this problem, the ODT system according to the first embodiment provides that the termination of the transmission line DB be enabled in periods other than a read period. However, in this case, if a memory controller and a memory device perform write and read operations without a break, the transmission line DB may possibly be floated and as a result, the transmission line DB may possibly have an undesired voltage level at an instant of time.

[0049] Thus, to prevent the possible floating of the transmission line DB, the ODT system according to the second embodiment of the present invention further includes the second termination resistor R-term 2 that continuously connects the data I/O port DQ to the termination voltage port VTP. As mentioned above, the second termination resistor R-term 2 is used only to prevent the floating of the transmission line DB and thus has a still larger resistance value than the first termination resistor R-term 1 .

[0050] In the ODT system according to the second embodiment, when the switch TM is turned on to enable the termination of the transmission line DB, a termination resistance value becomes a parallel resistance value between the first termination resistor R-term 1 and the second termination resistor R-term 2 . The parallel resistance value may approximate the resistance value of the first termination resistor R-term 1 because the second termination resistor R-term 2 is remarkably greater than the first termination resistor R-term 1 .

[0051] FIG. 7 is a block diagram of an example of a memory system that adopts a synchronous memory device 75 including an ODT circuit 751 according to the present invention. In the memory system of FIG. 7, a voltage regulator 73 generates a termination voltage VTTP. The synchronous memory device 75 , which includes the ODT circuit 751 as shown in FIG. 3 or FIG. 6 , receives termination voltage VTTP, which is generated by the voltage regulator 73 , via a termination voltage port VTP.

[0052] FIG. 8 is a block diagram of another example of a memory system that adopts a synchronous memory device 85 including an ODT circuit 851 according to the present invention. In the memory system of FIG. 8, a memory controller 81 generates termination voltage VTTP. The synchronous memory device 85 , which includes the ODT circuit 851 , receives the termination voltage VTTP, which is generated by the memory controller 81 , via a termination voltage port VTP.

[0053] FIG. 9 is a block diagram of a memory system that adopts a multi-drop net shared by a plurality of synchronous memory devices 91 , . . . , 93 , and 94 , each of the synchronous memory devices including an ODT circuit according to the present invention. It is preferable that in a memory system adopting a multi-drop net as shown in FIG. 9 , ODT is enabled in only the memory device 94 furthest from a memory controller 91 , and is disabled in the other memory devices 91 , . . . , and 93 . Accordingly, only an MRS in the memory device 94 farthest from the memory controller 91 is set, without setting MRSs in the other memory devices 92 , . . . , and 93 .

[0054] In other words, in the memory device 94 having the set MRS, both signals MRS_EN and MRS_TE are at logic ‘high’, and thus a termination enable signal TE is enabled to logic ‘high’ in the termination enable signal generating circuit of FIG. 4 , thereby enabling the ODT. However, in each of the memory devices 92 , . . . , and 93 in which the MRS is not set, signals MRS_EN and MRS_TE are at logic ‘low’, and thus a termination enable signal TE is disenabled to logic ‘low’, thereby enabling the ODT.

[0055] In this disclosure, the memory system of FIG. 9 is constructed such that ODT of only the memory device 94 is enabled. However, if necessary, it is possible to make a memory system in which ODT of at least one memory device farthest from the memory controller 91 is enabled.

[0056] Also, in the memory system of FIG. 9 , ODT of the memory device 94 is enabled or disabled depending on whether an MRS is set or not. A memory system can be fabricated such that each memory device has an identify (“ID”) register instead of an MRS and the ID register is set by a memory controller to enable the ODT of the memory device.

[0057] As described above, in an ODT circuit and ODT method according to the present invention, the path of an electric current does not form between supply voltage VDD and ground voltage VSS during the enabling of ODT, thereby minimizing the consumption of an on-chip DC current.

[0058] While the present invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those of ordinary skill in the pertinent art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.