DETAILED DESCRIPTION

[0037] In accordance with an embodiment of the present invention, a capacitor with improved capacitance is provided. The fabrication process includes forming islands in a trench and then etching around the islands to increase the dimensions of the trench. The materials and processes described below can be employed with various kinds of substrates, including, but not limited to silicon (Si), gallium arsenide (GaAs), indium phosphide (InP), and silicon carbide (SiC). It is to be appreciated that the numbers used, by way of example only, temperature, pressure, time and dimensions, are approximations and may be varied, and it is obvious to one of ordinary skill in the art that certain steps may be performed in a different order.

[0038] FIG. 1 is a schematic cross-sectional illustration of a trench 102 formed in a semiconductor substrate 100 at one step of the process of fabricating a trench capacitor in accordance with the present invention. The trench 102 is defined by sidewalls 104 . As shown in FIG. 1 , the trench 102 is bottle-shaped. However, it is to be appreciated that one of ordinary skill in the art of manufacturing trench capacitors may design trenches having different shapes. For instance, the trench 102 may have substantially vertical sidewalls or some other geometric structure. The trench 102 may be formed as follows. A masking layer having an opening may be applied to the surface of the semiconductor substrate 100 . Then an etching procedure such as Reactive Ion Etching (“RIE”) or an equivalent process is performed to remove substrate material and form the trench 102 . RIE is a form of etching that recesses a material by bombarding it with charged particles. RIE is anisotropic, meaning that when recessing a material, RIE will etch more in one direction than another direction. Preferably, a bottle etch is then performed to create the bottle shape. The bottle etch is preferably performed using a “wet etch” of an ammonium hydroxide (NH ₄ OH) solution having a concentration of between 5:1 and 200:1 at a temperature between about 35° C. to 70° C. The pressure is preferably atmospheric. The time of the etch is preferably on the order of 90-180 seconds.

[0039] A collar 108 may then be formed over the sidewalls 104 in an upper region of the trench 102 . The collar 108 is preferably an oxide that may be grown or deposited on the sidewalls 104 . Growth may be performed by a thermal oxidation process. Deposition may be performed by a type of chemical vapor deposition (“CVD”) such as low pressure CVD (“LPCVD”). Preferably, the collar 108 is between about 300-400 Å thick. A pad stack 106 is formed on the surface of the semiconductor substrate either before or after the collar 108 is formed. The pad stack 106 may be used in further processing steps.

[0040] The pad stack 106 preferably comprises a pad oxide 106 a and a pad nitride 106 b disposed over the pad oxide 106 a. In one process, the pad oxide 106 a may be thermally grown on the semiconductor substrate 100 . In an alternative process, the pad oxide 106 a may be formed by first depositing tetraethylorthosilicate (TEOS) in an LPCVD process and then annealing the TEOS in oxygen, as is known in the art. The pad oxide 106 a is preferably on the order of 50 Å thick. The pad nitride 106 b comprises silicon nitride (hereinafter “nitride”), which may be deposited as is known in the art. The pad nitride is preferably on the order of 1000 Å thick.

[0041] FIG. 2 illustrates the trench 102 after a mask 110 has been formed along the sidewalls 104 . The mask 110 may be deposited or grown within the trench 102 . Preferably, the mask 110 is an oxide mask that is grown by means of Rapid Thermal Oxidation (“RTO”). The RTO process is typically done in a single wafer processor between 700-1000° C. The time preferably ranges between 5-60 seconds. The mask 110 is preferably between about 20-50 Å thick, or approximately an order of magnitude thinner than the collar 108 . The exact thickness may vary depending on the specific process conditions.

[0042] FIG. 3 illustrates a subsequent step wherein islands 112 are deposited over the mask 110 . The islands 112 are preferably nitride deposited using LPCVD. The deposition preferably occurs before any additional processing, e.g., cleaning or smoothing, of the mask 110 . The LPCVD deposition preferably occurs at temperatures ranging between 575-800° C. The time preferably ranges from 1 minute to 30 minutes. More preferably, the temperature is between 650° C. and 750° C., and the time is between 5-20 minutes. Typically, the lower the temperature, the longer the time, and the higher the temperature the shorter the time. For example, at 650° C. the process may take 20 minutes, and at 750° C. the process may take 5 minutes. The pressure is preferably 15 mTorr. Such a process, known as “nucleation,” forms a series of distributed islands 112 on the mask 110 , but not on the collar 108 . The islands 112 form because of surface wetting on silicon dioxide and begin to coalesce after about 40 Å into a continuous film. The collar 108 at this point in the process is a disposable collar that is preferably made of Si ₃ N ₄ . The islands 112 do not form on the collar 108 , but do form on the mask 110 because of the surface wetting. The LPCVD process preferably grows the islands 112 such that they are distributed across the mask 110 . The islands 112 preferably have a thickness of below about 40 Å, although the actual thickness may be greater or lesser. The nucleation of the islands 112 provides a micro-masking structure, which preferably includes portions of the mask 110 . The micro-masking structure will be employed to create further recesses within the trench 102 , as will be explained below.

[0043] FIG. 4 illustrates a further step in the manufacturing process where exposed portions of the mask 110 have been removed. Preferably, the exposed portions of the mask 110 are removed by an etching process using, for example, hydrofluoric acid (HF). The HF etch is a selective process. Selectivity is the ratio of the etch rate of one material as compared to the etch rate of another material. HF is selective to nitride, meaning that the mask 110 comprising oxide is removed more rapidly than the islands 112 comprising nitride. HF containing solutions in H ₂ O or a buffer in concentrations from 7:1 to 200:1 are preferably used. Room temperature is preferably used.

[0044] FIG. 5 illustrates the trench 102 after the exposed sidewalls 104 are etched back to form recesses 114 . The recesses 114 increase the size of the trench 102 , which in turn will increase the amount of material that can be used for the inner electrode of the capacitor, as well as the surface area of the dielectric layer which will cover the inner electrode. Preferably, an etch process employing NH ₄ OH recesses the sidewalls 104 . NH ₄ OH is selective to oxide and nitride, so the sidewalls 104 , which are formed of the same material as the semiconductor substrate 100 , will be etched more rapidly than the micro-masking structure. The NH ₄ OH wet etch is preferably performed using an NH ₄ OH solution having a concentration of between 5:1 and 200:1 (i.e., 1 part NH ₄ OH to 5 (or 200) parts of H ₂ O) at a temperature between about 35° C. to 70° C. The pressure is preferably atmospheric. The time is preferably between 90-180 seconds. The etch rate and etch depth may be controlled by varying one or more of these parameters. An alternative etching process which may be employed is an isotropic plasma etch. Plasma etching is a chemical process that employs gasses and plasma energy to cause a chemical reaction.

[0045] After the recesses 114 have been formed, the micro-masking structure is removed. The result is illustrated in FIG. 6 . The mask 110 and the islands 112 may be removed in one or more stages. Preferably, two stages are used, wherein the islands 112 are first removed by a hot phosphoric acid (H ₃ PO ₄ ) etch, followed by removal of the mask 110 using an HF etch. The hot H ₃ PO ₄ etch preferably takes place at a temperature of between 140-180° C. The time depends on thickness of material to be etched, but in this process approximately 1 minute is preferred. HF containing solutions in H ₂ O or a buffer in concentrations from 7:1 to 200:1 may be used. Typically room temperature is used. In an alternative process, the micro-masking structure is removed in one stage using a combination of HF and ethylene glycol (EG). The HF/EG process is preferably performed using an HF/EG solution having a concentration of between 5:1 and 20:1 at a temperature of approximately 80° C. The pressure is preferably atmospheric and the times preferably vary between 5-60 seconds.

[0046] FIG. 7 illustrates a subsequent step in the process of manufacturing a trench capacitor. At this stage the outer electrode 120 of the capacitor, also known as a “buried plate,” is formed around the trench 102 . Doping the semiconductor substrate 100 around the trench 102 with a dopant creates the outer electrode 120 . Preferably, the dopant in an n-type semiconductor is arsenic, although other materials such as antimony or phosphorous may be used. Boron is typically used to dope a p-type substrate. In a preferred embodiment, the arsenic is provided as a gas and diffuses into the semiconductor substrate 100 at a concentration of between about 1×10 ¹⁹ and 1×10 ²⁰ atoms per cm ³ . More preferably, the dopant concentration is as high as possible subject to manufacturing limitations.

[0047] After the outer electrode 120 is formed, a dielectric liner, the “node dielectric” 122 , is formed along the sidewalls 104 in the portion of the trench below the collar 108 . FIG. 8 shows the node dielectric 122 disposed within the trench 102 . The node dielectric 122 may be any suitable material having a high dielectric constant, i.e., “high K.” As used herein, “high K” materials have a dielectric constant greater than silicon dioxide (SiO ₂ ), which has a dielectric constant of about 3.9.

[0048] One preferred dielectric material is tantalum pentoxide (Ta ₂ O ₅ ), which has a dielectric constant of between 25-50. Other suitable dielectric materials include SiN, having a dielectric constant of about 7; titanium oxide (TiO ₂ ), having a dielectric constant of between about 30-40; zirconium oxide (ZrO ₂ ), having a dielectric constant of between about 14-28; strontium titanate (SrTiO ₃ ), having a dielectric constant of approximately 230; and barium-strontium-titanate (BST), having a dielectric constant between about 320-800. Additional dielectric materials may be employed besides those enumerated herein. The node dielectric 122 may be formed of one or more layers of material, such as an oxide-nitride-oxide (ONO) combination, which may have a dielectric constant of about 7. The process for forming the node dielectric 122 depends on the materials used. By way of example only, Ta ₂ O ₅ , TiO ₂ and ZrO ₂ may be formed using metal oxide CVD (“MOCVD”), BST and SrTiO ₃ may be formed using a combination of MOCVD and molecular beam epitaxy (“MBE”), and ONO may be formed using a combination of oxidation and CVD, as is known in the art.

[0049] After formation of the node dielectric 122 , the inner electrode may be created by substantially filling the trench 102 with a capacitor fill material 130 having a top surface 132 , as shown in FIG. 9 . The capacitor fill material 130 is preferably poly-Si doped with arsenic. The capacitor fill material may be formed as follows. First, the trench is filled with poly-Si using LPCVD or a similar process. Then the arsenic is provided as a gas and diffuses into the poly-Si at a concentration of between about 1×10 ¹⁹ and 1×10 ²⁰ atoms per cm ³ . More preferably, the arsenic concentration is as high as possible, subject to manufacturing limitations. Alternatively, the poly-Si may be in situ doped with the arsenic. By way of example only, such in situ doping may be performed using a mixture of silane (SiH ₄ ) and arsine (AsH ₃ ) gases flowed simultaneously over the trench 102 at a deposition temperature of between about 400° C. and 700° C. and a pressure of between 100 to 1000 Torr.

[0050] Upon completion of the trench capacitor, a transistor and accompanying connections may be formed on the semiconductor substrate 100 in order to fabricate a DRAM memory cell. FIG. 10 illustrates the semiconductor substrate 100 after the transistor is formed. Specifically, the figure shows a drain 150 and buried strap contact 152 adjacent to one side of the capacitor fill material 130 . A source 154 and a gate conductor/word line 156 complete the transistor. On the other side of the capacitor fill material 130 is shallow trench isolation (“STI”) 140 , which serves to electrically isolate the memory cell from adjacent memory cells in the semiconductor substrate 100 . The source 154 is connected to a bit line 162 through a bit line contact 160 . Spacers 158 provides isolation to the capacitor and to the gate conductor/word line 156 . The transistor of FIG. 10 is planar, but a vertical or other transistor design may be used.

[0051] While the enhanced capacitor design of the present invention is illustrated as a trench capacitor, the invention may also be used in a stacked capacitor design. In accordance with another embodiment of the present invention, a capacitor with enhanced capacitance is provided in a stacked configuration. The fabrication process includes forming an inner electrode and processing the inner electrode to provide increased surface area. As with the trench structure of FIGS. 1 - 10 , the materials and processes described below may be employed with various kinds of substrates. Furthermore, the numbers used are approximations and may be varied, and certain steps may be performed in a different order.

[0052] FIG. 12 is a schematic cross-sectional illustration of a semiconductor substrate 300 at one step of the process of fabricating a stacked semiconductor device. Prior to the formation of a stacked capacitor, a transistor is preferably formed on the semiconductor substrate 300 . The transistor includes a source 310 , a drain 312 and a gate conductor/word line 314 . Spacers 316 , which are preferably oxide spacers, may isolate the gate conductor/word line 314 . STI 318 isolates the stacked semiconductor device from adjacent devices in the semiconductor substrate 300 . The source 310 , the drain 312 , the gate conductor/word line 314 , the spacers 316 and the STI 318 may be formed using known processes. Next, a buffer 320 may be deposited over the substrate 300 , substantially covering the drain 312 , the gate conductor/word line 314 , the spacers 316 and the STI 318 . The buffer 320 is preferably boro-phospho-silicate glass (BPSG).

[0053] FIG. 13 illustrates the result of a subsequent step after the buffer 320 is etched to create a trench which is then filled with an inner electrode. The trench may be formed in multiple stages. For example, a narrow, deep trench may first be etched, followed by a wider, shallower trench. The trench formation process is preferably performed using RIE. The inner electrode preferably comprises a stem 330 and a body 332 each having sidewalls 334 . The stem 330 and the body 332 may be formed in one or more stages. Preferably, the stem 330 and the body 332 both comprise doped poly-Si. The dopant is preferably arsenic having a concentration of at least 1×10 ¹⁹ atoms per cm ³ . Alternatively, titanium nitride (TiN) or another suitable material may be used.

[0054] FIG. 14 illustrates the result of a subsequent step after the buffer 320 has been recessed below the body 332 of the inner electrode. RIE may be used to recess the buffer 320 .

[0055] FIG. 15 illustrates the stacked semiconductor device after a mask 340 is formed over the sidewalls 334 of the body 332 of the inner electrode. As with the mask 110 ( FIG. 2 ), the mask 340 may be deposited or grown over the sidewalls 334 . Preferably, the mask 340 is an oxide mask that is grown by a thermal oxidation process such as RTO. The mask 340 is preferably on the order of 20-30 Å thick. The exact thickness may be larger or smaller than this range depending upon the process conditions.

[0056] FIG. 16 illustrates a subsequent step wherein islands 342 are deposited over the mask 340 . As with the islands 112 ( FIG. 3 ), the islands 342 are preferably nitride, which are deposited using LPCVD within a temperature range of approximately 575° C. to 800° C. for between 1 to 30 minutes. More preferably, the LPCVD process occurs at a temperature of between 650° C. and 750° C. and a pressure of 15 mTorr for between 5 to 20 minutes. Typically, the lower the temperature the longer the time, and the higher the temperature the shorter the time. The deposition preferably occurs before any additional processing, e.g., cleaning or smoothing, of the mask 340 . As described above with reference to FIG. 3 , the LPCVD process preferably grows the islands 342 such that they are distributed across the mask 340 . The islands 342 may be less than about 40 Å, and preferably have a thickness between about 20-30 Å. The thickness may be higher or lower depending on process conditions. The nucleation of the islands 342 provides a micro-masking structure, which preferably includes portions of the mask 340 .

[0057] FIG. 17 illustrates the results of a further step in the manufacturing process where portions of the mask 340 not covered by the islands 342 have been removed. Preferably, an etching process using, for example, HF, removes the exposed portions of the mask 340 . The HF etch preferably occurs at the same process parameters as the HF etch described with relation to FIG. 4 .

[0058] FIG. 18 illustrates the results of another step after the sidewalls 334 exposed by the HF etch are recessed. Recesses 344 are formed in the sidewalls 334 , increasing the surface area of the body 332 of the inner electrode. The increased surface area will provide an increase in the capacitance of a stacked capacitor of the present invention as compared to a stacked capacitor without the recesses 344 . Recessing is preferably accomplished by applying a solution of NH ₄ OH having a concentration of between 5:1 and 200:1 and a temperature between about 35° C. and 70° C. for approximately 1-2 minutes. The etch rate and depth may be controlled by varying one or more of these parameters.

[0059] After the recesses 344 have been formed, the micro-masking structure is removed. The result is illustrated in FIG. 19 . The mask 340 and the islands 342 may be removed in one or more stages. Preferably, two stages are used, wherein the islands 342 are first removed by a hot H ₃ PO ₄ etch, followed by removal of the mask 340 using an HF etch. The H ₃ PO ₄ etch and the HF etch preferably take place at the same process parameters as the etches described with relation to FIG. 6 . In an alternative process, the micro-masking structure is removed in one stage using an HF/EG combination. The HF/EG solution preferably has a concentration of between 5:1 and 20:1 and a temperature of approximately 80° C. The temperature and pressure of the process are preferably the same as described with respect to FIG. 6 .

[0060] FIG. 20 illustrates a subsequent step in the process of manufacturing a stacked capacitor. At this stage, a node dielectric 346 is formed along the sidewalls 334 . The node dielectric 346 may be any suitable high K material as discussed above with reference to the node dielectric 122 ( FIG. 8 ). Node dielectric 346 formation may be performed in the same manner as forming the node dielectric 122 .

[0061] An outer electrode 348 is then formed over the node dielectric 346 , as shown in FIG. 21 . The outer electrode 348 preferably comprises poly-Si doped with arsenic, wherein the arsenic is at a concentration of at least 1×10 ¹⁹ atoms per cm ³ . Alternatively, other materials and dopants may be used for the outer electrode 348 as well as the stem 330 and the body 332 of the inner electrode. By way of example only, TiN may be used.

[0062] FIG. 22 illustrates the result of a further processing step after additional connections to the transistor have been formed. The source 310 is connected to a bit line 352 through a bit line contact 350 , as is known in the art. The bit line 352 and the bit line contact 350 are typically formed from a metal such as tungsten. As shown in FIG. 22 , the stacked capacitor is formed over the transistor, but other structural configurations are possible.

[0063] One advantage of the present invention is that the micro-masking structure can be used in any trench structure or aspect ratio to provide enhanced capacitance. Another advantage of the present invention is that conventional node dielectric and storage electrode materials can be employed, avoiding expensive materials and processing. Yet another advantage of the present invention is that capacitors can be fabricated with a capacitance in excess of 25 fF, ensuring sufficient signal margin and retention time. The present process also circumvents problems of HSG by removing the need for a Recess RIE process. The area-enhancement of the present invention may be achieved by etching into the silicon and not by adding conductive silicon, thus removing the possibility of a short. The islands are removed from the collar region during the area enhancement etchback process. In addition, if the islands are formed of Si ₃ N ₄ and were to remain on the collar region, it would not short circuit the memory cell because Si ₃ N ₄ is itself an insulator.

[0064] Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims.