Title:
Active filter circuit with dynamically modifiable internal gain
Document Type and Number:
Kind Code:
A1

Abstract:
Techniques are provided for the implementation of a signal processing circuit (100) which expands the dynamic range of the signal processing circuit (100) without interrupting the output of the circuit. The techniques can receive an input signal (104), process the signal (104) through one of a plurality of dynamically modifiable signal processing circuits, and switch (130) to processing the signal through another of the plurality of signal processing circuits without disturbing the output of the system.

Representative Image:
Active filter circuit with dynamically modifiable internal gain
Inventors:
Palaskas, George (Portland, OR, US)
Tsividis, Yannis (New York, NY, US)
Toth, Laszlo (New York, NY, US)
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Sponsored by:
Flash of Genius
Application Number:
10/450804
Publication Date:
05/13/2004
Filing Date:
12/17/2003
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Referenced by:
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Export Citation:
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Primary Class:
375/229
International Classes:
(IPC1-7): H03K005/159; H03H007/30
Attorney, Agent or Firm:
BAKER & BOTTS (30 ROCKEFELLER PLAZA, NEW YORK, NY, 10112)
Claims:
1. An active filter system comprising: a system input for receiving a system input signal; a system output for providing a system output signal; a main filter having at least one successive filter stage having an input and an output, including a first filter stage, each filter stage having an associated input amplification stage including a signal input, a signal output coupled to the input of the associated filter stage and a gain control input for receiving a gain control signal that determines the amplification factor of the associated input amplification stage, the input of the input amplification stage associated with each filter stage, except for the input amplification stage associated with the first filter stage, being coupled to the output of a preceding filter stage, if any, the input of the amplification stage associated with the first filter stage being coupled to the system input, each filter stage having an associated output amplification stage including a signal input coupled to the output of the associated filter stage, a signal output and a gain control input for receiving a gain control signal that determines the amplification factor of the associated output amplification stage, the signal output of the output amplification stage associated with a selected one of the at least one filter stage being coupled to the system output; a strength detector having an input coupled to the output of the first filter stage, and having a first output and a second output for providing respective output signals indicative of whether the first filter stage is approaching saturation or is providing an output signal having less than a minimum acceptable signal to noise ratio; a zero crossing detector having at least one input coupled to respective ones of the at least one output of the at least one filter stage of the main filter, and having at least one output for providing at least one signal indicative of when a successive one of the at least one filter stage of the main filter provides a signal at its output that is approximately equal to zero; and a gain control unit having a first input and a second input respectively coupled to the output of the strength detector and coupled to the at least one output of the zero crossing detector, and having a multiplicity of outputs for providing respective gain control signals to the gain control input of each input amplification stage and each output amplification stage associated with the at least one filter stage of the main filter, the gain control unit being responsive to signals provided initially by the strength detector indicative of the first filter stage approaching saturation or providing an output signal having less than the minimum acceptable signal to noise ratio, and a signal from the zero crossing detector indicative of the output signal provided by the first filter stage being approximately equal to zero for providing a gain control signal to the gain control input of the input amplification stage associated with the first filter stage so that the input amplification stage associated with the first filter stage has an amplification factor that results in a signal strength at its signal output which avoids saturation of the first filter stage and avoids the first filter stage providing a signal having less than the minimum acceptable signal to noise ratio, and for providing a gain control signal to the gain control input of the output amplification stage associated with the first filter stage so that the output amplification stage associated with the first filter stage has an amplification factor which is the reciprocal of the amplification factor of the input amplification stage associated with the first filter stage, the gain control unit being thereafter responsive to signals provided initially by the strength detector indicative of the first filter stage of the main filter approaching saturation or providing an output having less than the minimum acceptable signal to noise ratio, and to a signal from the zero crossing detector indicating that an output signal at the output of a successive filter stage, if any, being approximately equal to zero for providing a gain control signal to the gain control input of the input amplification stage associated with the successive filter stage so that the input amplification stage associated with the successive filter stage has an amplification factor that results in a signal strength at its signal output that avoids saturation of the successive filter stage and avoids the successive filter stage providing a signal having less than the minimum acceptable signal to noise ratio, and for providing a gain control signal to the gain control input of the output amplification stage associated with the successive filter stage so that the output amplification stage associated with the successive filter stage has an amplification factor which is a reciprocal of the amplification factor of the input amplification stage associated with the successive filter stage.

2. An active filter system according to claim 1, wherein the at least one filter stage of the main filter comprises a first filter stage and a second filter stage, and the zero crossing detector comprising: a switching unit having a first signal input coupled to the output of the first filter stage, a second signal input coupled to the output of the second filter stage, a switch control input, and a signal output, the switching unit being responsive to a first switch control signal received by the switch control terminal for connecting the first signal input to the signal output and disconnecting the second signal input from the signal output, and being responsive to a second switch control signal received by the switch control terminal for connecting the second signal input to the signal output and disconnecting the first signal input from the signal output; a comparator having a signal input coupled to the signal output of the switching unit, and a signal output for providing an output signal, the comparator providing a first logical signal on the signal output if the signal received at the signal input is approximately equal to zero, and providing a second logical signal on the signal output if the signal received at the signal input is not approximately equal to zero; and a three-stage shift register having a clock input coupled to the signal output of the comparator, a reset/enable input, a first stage output, a second stage output and a third stage output, the shift register being responsive to a first logical signal received at the reset/enable input for producing a first logical signal at the first stage output, a second logical signal at the second stage output and a second logical signal at the third stage output, and being responsive to receiving the second logical signal at the reset/enable input and a signal changing from the second logical signal to the first logical signal at the clock input while having the first logical signal at the first stage output, the second logical signal at the second stage output and the second logical signal at the third stage output for providing the second logical signal at the first stage output, the first logical signal at the second stage output and the second logical signal at the third stage output, the shift register being responsive to the first logical signal received at the reset/enable input and a signal changing from the second logical signal to the first logical signal at the clock input while having the second logical signal at the first stage output, the first logical signal at the second stage output and the second logical signal at the third stage output for providing the second logical signal at the first stage output, the second logical signal at the second stage output and the first logical signal at the third stage output, and being responsive to the first logical signal received at the reset/enable input and a signal changing from the second logical signal to the first logical signal at the clock input while having the second logical signal at the first stage output, the second logical signal at the second stage output and the first logical signal at the third stage output for providing the second logical signal at the first stage output, the second logical signal at the second stage output and the first logical signal at the third stage output, and wherein the first stage output, the second stage output and the third stage output are the output signals of the zero crossing detector provided to the gain control unit, and the first stage output is also the switch control terminal of the switching unit.

3. The active filter system of claim 2, wherein the gain control unit has a first zero cross input coupled to the first stage output of the shift register and the switch control input of the switching unit, a second zero cross input coupled to the second stage output of the shift register, a third zero cross input coupled to the third stage output of the shift register, a reset/enable output for providing a reset/enable signal to the reset/enable input of the shift register, a first gain control output terminal, a second gain control output terminal, a third gain control output terminal, a fourth gain control output terminal and a fifth gain control output terminal; the gain control unit being responsive to receiving a first signal from the strength detector indicative of the first filter stage providing a signal having less than the minimum acceptable signal to noise ratio when the first gain control terminal is providing a second logical signal, the second gain control terminal is providing the second logical signal, the third gain control terminal is providing the second logical signal, the fourth gain control terminal is providing a first logical signal and the fifth gain control terminal is providing the second logical signal, for providing the second logical signal on the reset/enable output, and being thereafter responsive to receiving the second logical signal on the first zero cross input, the first logical signal on the second zero cross input and the second logical signal on the third zero cross input for providing the second logical signal on the reset/enable output, the second logical signal on the first gain control output terminal, the first logical signal on the second gain control output terminal, the second logical signal on the third gain control output terminal, the second logical signal on the fourth gain control output terminal and the first logical signal on the fifth gain control output terminal, and being thereafter responsive to receiving the second logical signal on the first zero cross input, the second logical signal on the second zero cross input and the first logical signal on the third zero cross input for providing the second logical signal on the reset/enable output, the first logical signal on the first gain control output terminal, the second logical signal on the second gain control output terminal, the second logical signal on the third gain control output terminal, the first logical signal on the fourth gain control output terminal and the second logical signal on the fifth gain control output terminal; the gain control unit being responsive to receiving a signal from the signal strength detector indicative of the first filter stage providing a signal having less than the minimum acceptable signal to noise ratio while the first gain control output terminal is providing the first logical signal, the second gain control output terminal is providing the second logical signal, the third gain control output terminal is providing the second logical signal, the fourth gain control output terminal is providing the first logical signal and the fifth gain control output is providing the second logical signal, for providing after a particular time delay the second logical signal on the reset/enable output, and being thereafter responsive to receiving the second logical signal on the first zero cross input, the first logical signal on the second zero cross input and the second logical signal on the third zero cross input for providing the second logical signal on the reset/enable output, the second logical signal on the first gain control output terminal, the first logical signal on the second gain control output terminal, the first logical signal on the third gain control output terminal, the second logical signal on the fourth gain control output terminal and the second logical signal on the fifth gain control output terminal, and being thereafter responsive to receiving the second logical signal on the first zero cross input, the second logical signal on the second zero cross input and the first logical signal on the third zero cross input for providing the second logical signal on the reset/enable output, the second logical signal on the first gain control output terminal, the first logical terminal on the second gain control output terminal, the second logical signal on the third gain control output terminal, the first logical signal on the fourth gain control output terminal and the second logical signal on the fifth gain control output terminal; the gain control unit being responsive to receiving a signal from the strength detector indicative of the first filter stage approaching saturation while the first gain control output is providing the second logical signal, the second gain control output is providing the first logical signal, the third gain control output terminal is providing the second logical signal, the fourth gain control output is providing the second logical signal and the fifth gain control output terminal is providing the second logical signal, for providing after a particular time delay the second logical signal on the reset/enable output, and being thereafter responsive to receiving the second logical signal on the first zero cross input, the first logical signal on the second zero cross input and the second logical signal on the third zero cross input for providing the second logical signal on the reset/enable output, the second logical signal on the first gain control output terminal, the second logical signal on the second gain control output terminal, the first logical signal on the third gain control output terminal, the second logical signal on the fourth gain control output terminal and the second logical signal on the fifth gain control output terminal, and being thereafter responsive to receiving the second logical signal on the first zero cross input, the second logical signal on the second zero cross input and the first logical signal on the third zero cross input for providing the second logical signal on the reset/enable output, the second logical signal on the first gain control output terminal, the second logical signal on the second gain control output terminal, the second logical signal on the third gain control output terminal, the first logical signal on the fourth gain control output terminal and the second logical signal on the fifth gain control output terminal, and wherein: the gain control input of the input amplification stage associated with the first filter stage comprises a first gain control terminal and a second grain control terminal, the first gain control terminal of the input amplification stage associated with the first filter stage of the main filter being coupled to the first gain control output terminal of the gain control unit, and the second gain control terminal of the input amplification stage associated with the first filter stage of the main filter is coupled to the second gain control output terminal of the gain control unit, the input amplification stage associated with the first filter stage being responsive to receiving the second logical signal on its first gain control terminal and the second logical signal on its second gain control terminal for amplifying the input signal by a first amplification factor, and being responsive to receiving the second logical signal on the first gain control terminal and the first logical signal on the second gain control terminal for amplifying the input signal by a second amplification factor which is greater than the first amplification factor, and being responsive to receiving the first logical signal on the first gain control terminal and the second logical signal on the second gain control terminal for amplifying the input signal by a third amplification factor which is greater than the second amplification factor; the gain control input of the output amplification stage associated with the first filter stage comprises a first gain control terminal and a second gain control terminal, the first gain control terminal of the output amplification stage associated with the first filter stage being coupled to the first gain control output terminal of the gain control unit, the second gain control terminal of the output amplification stage associated with the first filter stage is coupled to the second gain control output terminal of the gain control unit, the output amplification stage associated with the first filter stage being responsive to receiving the second logical signal on its first gain control terminal and the second logical signal on its second gain control terminal for amplifying a signal provided by the output of the first filter stage by the third amplification factor, and being responsive to receiving the second logical signal on its first gain control terminal and the first logical signal on its second gain control terminal for amplifying the signal provided by the output of the first filter stage by the second amplification factor, and being responsive to receiving the first logical signal on the first gain control terminal and the second logical signal on the second gain control terminal for amplifying the signal provided by the output of the first filter stage by the first amplification factor; the gain control input of the input amplification stage associated with the second filter stage comprises a third grain control terminal and a fourth gain control terminal, the third gain control terminal of the input amplification stage associated with the second filter stage being coupled to the third gain control output terminal of the gain control unit, and the fourth gain control terminal of the input amplification stage associated with the second filter stage is coupled to the fourth gain control output terminal of the gain control unit, the input amplification stage associated with the second filter stage being responsive to receiving the first logical signal on its third gain control terminal and the second logical signal on its fourth gain control terminal for amplifying a signal provided by the output of the first filter stage by a fourth amplification factor, and being responsive to receiving the second logical signal on its third gain control terminal and the first logical signal on its fourth gain control terminal for amplifying the signal provided by the output of the first filter stage by a fifth amplification factor which is greater than the fourth amplification factor, and being responsive to receiving the first logical signal on its third gain control terminal and the second logical signal on its fourth gain control terminal for amplifying the signal provided by the output of the first filter stage by a sixth amplification factor which is greater than the fifth amplification factor; and the gain control input of the output amplification stage associated with the second filter stage comprises a fourth gain control terminal and a fifth gain control terminal, the fourth gain control terminal of the output amplification stage associated with the second filter stage being coupled to the fourth gain control output terminal of the gain control unit, the fifth gain control terminal of the amplification stage associated with the second filter stage being coupled to the fifth gain control unit, the output amplification stage associated with the second filter stage being responsive to receiving the second logical signal on its fourth gain control terminal and the second logical signal on its fifth gain control terminal for amplifying a signal provided by the output of the second filter stage by the fourth amplification factor, and being responsive to receiving the second logical signal on its fourth gain control terminal and the first logical signal on its fifth gain control terminal for amplifying the signal provided by the output of the second filter stage by the sixth amplification factor, and being responsive to receiving the first logical signal on its fourth gain control terminal and the second logical signal on its fifth gain control terminal for amplifying the signal provided by the output of the second filter stage by the fifth amplification factor.

4. The active filter system of claim 3, wherein the signal strength detector comprises: a peak detector having an input coupled to the output of the first filter stage of the main filter and an output, the peak detector detecting a voltage envelope peak of the signal provided by the output of the first filter stage and providing a signal representative of the voltage envelope peak at its output; a first threshold detector having an input coupled to the output of the peak detector and an output, the first threshold detector comparing the signal provided by the peak detector with a first threshold representative of a signal strength at the input of the first filter stage that would cause the first filter stage to approach saturation, the first threshold detector providing the first logical signal at its output if the signal received from the peak detector is less than the first threshold, and providing the second logical signal at its output if the signal received from the peak detector is greater than or equal to the first threshold; and a second threshold detector having an input coupled to the output of the peak detector and an output, the second threshold detector comparing the signal from the peak detector with a second threshold representative of an input signal strength at the input of the first filter stage that would cause a signal provided by the output of the first filter to have less than a minimum acceptable signal to noise ratio, the second threshold detector providing the first logical signal at its output if the signal from the peak detector is greater than or equal to the second threshold, and for providing the second logical signal at its output if the signal from the peak detector is less than the second threshold, wherein the output of the first threshold detector and the output of the second threshold detector comprise the first and second outputs of the strength detector, respectively.

5. The active filter system of claim 3, wherein the first filter stage comprises a first integrator having an input and an output, and the second filter stage comprises a second integrator having an input and an output.

6. The active filter system of claim 2, wherein the input of the output amplification stage associated with the second filter stage is coupled to the output of the second filter stage, and the output of the output amplification stage associated with the second filter stage is coupled to the signal input of the input amplification stage associated with the second filter stage, and wherein the signal output of the output amplification stage associated with the first filter stage is coupled to the system output.

7. The active filter system of claim 2, wherein the input amplification stage associated with the first filter stage includes circuitry for clamping an output signal provided by the input amplification stage so as to prevent saturation of the first filter stage.

8. The active filter system of claim 2, wherein the input amplification stage associated with the second filter stage includes circuitry for clamping an output signal provided by the input amplification stage so as to prevent saturation of the second filter stage.

9. The active filter system of claim 6, wherein the output amplification stage associated with the second filter stage includes circuitry for clamping an output signal provided by the output amplification stage so as to prevent saturation of the second filter stage.

10. An active filter system according to claim 5, wherein the input amplification stage associated with the first filter stage includes: a first resistor; a second resistor; a third resistor; a fourth resistor; a capacitor; a first switch having a first terminal, a second terminal and a switch control terminal; a second switch having a first terminal, a second terminal and a switch control terminal; and an operational amplifier having an inverted input, a normal input and an output, the first resistor being connected between the system input and the inverting input of the operational amplifier, the second resistor being connected between the system input and the first terminal of the first switch, the third resistor being connected between the system input and the first terminal of the second switch, the second terminal of the first switch being coupled to the inverting input of the operational amplifier, the second terminal of the second switch being coupled to the inverting input of the operational amplifier, the fourth resistor being coupled between the output and the inverting input of the operational amplifier, the capacitor being coupled between the output and the inverting input of the operational amplifier, the normal input of the operational amplifier being coupled to ground, the switch control terminal of the first switch being coupled to the second gain control terminal, the switch control terminal of the second switch being coupled to the first gain control terminal, wherein each of the first switch and the second switch is responsive to receiving the first logical signal on its switch control terminal for connecting its first terminal to its second terminal, and is responsive to receiving the second logical signal on its switch control terminal for disconnecting its first terminal from its second terminal.

11. The active filter system of claim 10, wherein the first resistor has a resistance of 200 kΩ, the second resistor has a resistance of 22.22 kΩ, the third resistor has a resistance of 2.02 kΩ has a resistance of 20 kΩ, and the capacitor 80 pF.

12. The active filter system of claim 5, wherein the first integrator comprises: a resistor; a capacitor; and an operational amplifier having an inverting input, a normal input and an output, the resistor being coupled between the output and the inverting input of the operational amplifier, the capacitor being coupled between the output and the inverting input of the operational amplifier, the normal input of the operational amplifier being coupled to ground, the inverting input of the operational amplifier being coupled to the input of the first integrator, and the output of the operational amplifier being coupled to the output of the first integrator.

13. The active filter system of claim 12, wherein the resistor has a resistance of 20 kΩ and the capacitor has a capacitance of 80 pF.

14. The active filter system of claim 5, wherein the output amplification stage associated with the first filter stage comprises: a first resistor; a second resistor; a third resistor; a fourth resistor; a first switch having a first terminal, a second terminal and a switch control terminal; a second switch having a first terminal, a second terminal and a switch control terminal; and an operational amplifier having a normal input, an inverting input and an output, the first resistor being coupled between the output of the first integrator and the inverting input of the operational amplifier, the second resistor being coupled between the output and the inverting input of the operational amplifier, the third resistor being coupled between the inverting input of the operational amplifier and the first terminal of the first switch, the fourth resistor being coupled between the inverting input of the operational amplifier and the first terminal of the second switch, the second terminal of the first switch being coupled to the output of the operational amplifier, the second terminal of the second switch being coupled to the output of the operational amplifier, the normal input of the operational amplifier being coupled to ground, the switch control terminal of the first switch being coupled to the second gain control input terminal and the switch control terminal of the second switch being coupled to the first gain control terminal, wherein each of the first switch and the second switch is responsive to receiving the first logical signal on its switch control terminal for connecting its first terminal to its second terminal, and is responsive to receiving the second logical signal on its switch control terminal for disconnecting its first terminal from its second terminal.

15. The active filter system according to claim 14, wherein the first resistor has a resistance of 20 kΩ, the second resistor has a resistance of 200 kΩ, the third resistor has a resistance of 22.22 kΩ and the fourth resistor has a resistance of 2.02 kΩ.

16. The active filter system of claim 5, wherein the input amplifier stage associated with the second filter stage comprises: a first resistor; a second resistor; a third resistor; a capacitor; a first switch having a first terminal, a second terminal and a switch control terminal; a second switch having a first terminal, a second terminal and a switch control terminal; and an operational amplifier having a normal input, an inverting input and an output, the first resistor being coupled between the output of the first integrator and the inverting input of the operational amplifier, the second resistor being coupled between the output of the first integrator and the first terminal of the first switch, the third resistor being coupled between the output of the first integrator and the first input of the second switch, the second terminal of the first switch being coupled to the inverting input of the operational amplifier, the second terminal of the second switch being coupled to the inverting input of the operational amplifier, the capacitor being coupled between the output and the inverting input of the operational amplifier, the normal input of the operational amplifier being coupled to ground, the switch control terminal of the first switch being coupled to the fourth gain control terminal and the switch control terminal of the second switch being coupled to the third gain control terminal, wherein each of the first switch and the second switch is responsive to receiving a first logical signal on its switch control terminal for connecting its first terminal to its second terminal, and is responsive to receiving the second logical signal on its switch control terminal for disconnecting its first terminal from its second terminal.

17. The active filter system of claim 16, wherein the first resistor has a resistance of 10 kΩ, the second resistor has a resistance of 1.01 kΩ, the third resistor has a resistance of 0.10 kΩ and the capacitor has a capacitance of 80 pF.

18. The active filter system of claim 5, wherein the second integrator comprises a capacitor, and an operational amplifier having a normal input, an inverting input and an output, the capacitor being coupled between the output and the inverting input of the operational amplifier, the inverting input of the operational amplifier being coupled to the input of the second integrator, the output of the operational amplifier being coupled to the output of the second integrator, the normal input of the operational amplifier being coupled to ground.

19. The active filter system of claim 6, wherein the output amplification stage associated with the second filter stage comprises: a first resistor; a second resistor; a third resistor; a fourth resistor; a fifth resistor; a sixth resistor; a capacitor; a first switch having a first terminal, a second terminal and a switch control terminal; a second switch having a first terminal, a second terminal and a switch control terminal; a first operational amplifier having a normal input, an inverting input and an output; and a second operational amplifier having a normal input, an inverting input and an output, the first resistor being coupled between the output of the second integrator and the inverting input of the first operational amplifier, the second resistor being coupled between the output and the inverting input of the first operational amplifier, the third resistor being coupled between the output of the first operational amplifier and the inverting input of the second operational amplifier, the fourth resistor being coupled between the inverting input of the second operational amplifier and the first terminal of the first switch, the fifth resistor being coupled between the inverting input of the second operational amplifier and the first terminal of the second switch, the second terminal of the first switch being coupled to the output of the first operational amplifier, the second terminal of the second switch being coupled to the output of the first operational amplifier, the normal output of the first operational amplifier being coupled to ground, the sixth resistor being coupled between the output and the inverting input of the second operational amplifier, the capacitor being coupled between the output and the inverting input of the second operational amplifier and the normal input of the second operational amplifier being coupled to ground, wherein each of the first switch and the second switch is responsive to receiving the first logical signal on its switch control terminal for connecting its first terminal to its second terminal, and is responsive to receiving the second logical signal on its switch control terminal for disconnecting its first terminal from its second terminal.

20. The active filter system of claim 19, wherein the first resistor has a resistance of 10 kΩ, the second resistor has a resistance of 10 kΩ, the third resistor has a resistance of 10 kΩ, the fourth resistor has a resistance of 1.11 kΩ, the fifth resistor has a resistance of 0.10 kΩ, the sixth resistor has a resistance of 20 kΩ, and the capacitor has a capacitance of 80 pF.

21. The active filter system of claim 4, wherein the gain control unit comprises a multiple state logic circuit responsive to the signals provided by the first and second threshold detectors of the strength detector, and the signals received at the first zero cross input, the second zero cross input and the third zero cross input for deriving respective signals on the first gain control output terminal, the second gain control output terminal, the third gain control output terminal, the fourth gain control output terminal and the fifth gain control output terminal.

Description:

SPECIFICATION

[0001] This application claims priority to U.S. Provisional Application Serial No. 60/260,722 filed Jan. 10, 2001, and U.S. Provisional Application Serial No. 60/288,976 filed May 4, 2001, each of which is incorporated by reference herein in its entirety.

BACKGROUND OF THE INVENTION

[0002] The present invention relates to signal processors and, more particularly, to signal processors that are dynamically modifiable for optimal performance and reduced power dissipation.

[0003] In order to expand the dynamic range of a signal processing system, companding signal processors can be used. A companding signal processor uses an input amplifier to amplify or attenuate a signal before it is provided to a signal processor, and an output amplifier is used to amplify or attenuate the signal provided by the signal processor. A signal processing circuit or signal processor includes an active filter. The gain of the output amplifier is the inverse of the gain of the input amplifier, thus conserving the overall gain of the signal processor. Ideally, the gains of the input amplifier and output amplifier should be dynamically variable. A signal strength detector can be used to measure the strength of the input signal and provide a processor appropriate gain control signal to the input amplifier and the output amplifier. See Y. Tsividis, “Externally linear, time-invariant systems and their application to companding signal processors,” IEEE Transactions on Circuits and Systems II, Vol. 44, No. 2, February 1997. The gain control signal sets the amplification factors of the input amplifier and the output amplifier. However, this approach has the problem in that because the signal processor has memory, distortion in the output of the signal processor occurs whenever the amplification factors of the input amplifier and the output amplifier are changed.

[0004] The analog floating point technique addresses the problem of distortion in the output whenever the amplification factors change. See E. Blumenkrantz, “The analog floating point technique,” Proc. IEEE Symposium on Low Power Electronics, p. 72-73, 1995. This technique avoids distortion by altering the state variables of the signal processor when the amplification factors change. However, implementation of the analog floating point technique is complicated, and is sensitive to parasitics and component mismatch. Accordingly, there is a need for circuits which expand the dynamic range of a signal processor without interrupting the output of the system or causing distortion.

SUMMARY OF THE INVENTION

[0005] It is therefore an object of this invention to provide a circuit which has a large dynamic range and which operates in an energy-efficient manner without interrupting the output of the circuit or causing distortion.

[0006] In accordance with the present invention, there is provided an active filter system including a system input for receiving a system input signal, a system output for providing a system output signal, a main filter, a strength detector, a zero crossing detector and a gain control unit. The main filter having at least one successive filter stage having an input and an output, including a first filter stage, each filter stage having an associated input amplification stage including a signal input, a signal output coupled to the input of the associated filter stage and a gain control input for receiving a gain control signal that determines the amplification factor of the associated input amplification stage, the input of the input amplification stage associated with each filter stage, except for the input amplification stage associated with the first filter stage, being coupled to the output of a preceding filter stage, if any, the input of the amplification stage associated with the first filter stage being coupled to the system input, each filter stage having an associated output amplification stage including a signal input coupled to the output of the associated filter stage, a signal output and a gain control input for receiving a gain control signal that determines the amplification factor of the associated output amplification stage, the signal output of the output amplification stage associated with a selected one of the at least one filter stage being coupled to the system output. The strength detector having an input coupled to the output of the first filter stage, and having a first output and a second output for providing respective output signals indicative of whether the first filter stage is approaching saturation or is providing an output signal having less than a minimum acceptable signal to noise ratio. The zero crossing detector having at least one input coupled to respective ones of the at least one output of the at least one filter stage of the main filter, and having at least one output for providing at least one signal indicative of when a successive one of the at least one filter stage of the main filter provides a signal at its output that is approximately equal to zero. The gain control unit having a first input and a second input respectively coupled to the output of the strength detector and coupled to the at least one output of the zero crossing detector, and having a multiplicity of outputs for providing respective gain control signals to the gain control input of each input amplification stage and each output amplification stage associated with the at least one filter stage of the main filter, the gain control unit being responsive to signals provided initially by the strength detector indicative of the first filter stage approaching saturation or providing an output signal having less than the minimum acceptable signal to noise ratio, and a signal from the zero crossing detector indicative of the output signal provided by the first filter stage being approximately equal to zero for providing a gain control signal to the gain control input of the input amplification stage associated with the first filter stage so that the input amplification stage associated with the first filter stage has an amplification factor that results in a signal strength at its signal output which avoids saturation of the first filter stage and avoids the first filter stage providing a signal having less than the minimum acceptable signal to noise ratio, and for providing a gain control signal to the gain control input of the output amplification stage associated with the first filter stage so that the output amplification stage associated with the first filter stage has an amplification factor which is the reciprocal of the amplification factor of the input amplification stage associated with the first filter stage, the gain control unit being thereafter responsive to signals provided initially by the strength detector indicative of the first filter stage of the main filter approaching saturation or providing an output having less than the minimum acceptable signal to noise ratio, and to a signal from the zero crossing detector indicating that an output signal at the output of a successive filter stage, if any, being approximately equal to zero for providing a gain control signal to the gain control input of the input amplification stage associated with the successive filter stage so that the input amplification stage associated with the successive filter stage has an amplification factor that results in a signal strength at its signal output that avoids saturation of the successive filter stage and avoids the successive filter stage providing a signal having less than the minimum acceptable signal to noise ratio, and for providing a gain control signal to the gain control input of the output amplification stage associated with the successive filter stage so that the output amplification stage associated with the successive filter stage has an amplification factor which is a reciprocal of the amplification factor of the input amplification stage associated with the successive filter stage.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Further objects, features, and advantages of the invention will become apparent from the following detailed description taken in conjunction with the accompanying figures showing illustrative embodiments of the invention, in which:

[0008] FIG. 1 is a block diagram illustrating a prior art signal processing system;

[0009] FIG. 2 is a block diagram illustrating a signal processing system in accordance with the present invention;

[0010] FIG. 3 is a circuit diagram illustrating the main filter of a signal processing system in accordance with the present invention;

[0011] FIG. 4 is a circuit diagram illustrating a switching unit of a signal processing system in accordance with the present invention;

[0012] FIG. 5 is a circuit diagram illustrating a shift register usable in a signal processing system in accordance with the present invention;

[0013] FIG. 6 is a circuit diagram illustrating a strength detector of a signal processing system in accordance with the present invention;

[0014] FIG. 7 is a circuit diagram illustrating a peak detector of a signal processing system in accordance with the present invention;

[0015] FIG. 8 is a circuit diagram illustrating a threshold detector of a signal processing system in accordance with the present invention;

[0016] FIGS. 9 ( a ) and 9 ( b ) are circuit diagrams illustrating a gain control unit of a signal processing system in accordance with the present invention;

[0017] FIG. 10 is a circuit diagram illustrating a comparator of a signal processing system in accordance with the present invention; and

[0018] FIG. 11 is a circuit diagram illustrating a transconductor of a signal processing system in accordance with the present invention.

[0019] Throughout the figures, unless otherwise stated, the same reference numerals and characters are used to denote like features, elements, components, or portions of the illustrated embodiments. Moreover, while the subject invention will now be described in detail with reference to the figures, and in connection with the illustrative embodiments, various changes and modifications to the described embodiments will be apparent to those skilled in the art without departing from the true scope and spirit of the subject invention as defined by the appended claims.

DETAILED DESCRIPTION OF THE INVENTION

[0020] FIG. 1 illustrates an example of a prior art signal processing system 10 . The signal processing system 10 is a companding filter. A companding filter amplifies or attenuates an input signal that is applied to a filter circuit, and attenuates or amplifies the output signal from the circuit. The prior art companding filter 10 includes an input 12 , a signal strength detector 14 , an input variable gain amplifier 16 , a main filter 18 , an output variable gain amplifier 20 , and an output 22 .

[0021] The input 12 of the signal processing system 10 is coupled to input 11 of the signal strength detector 14 and an input 30 of a variable gain input amplifier 16 . The variable gain input amplifier 16 amplifies or attenuates the signal received by the input 30 depending on a gain control input signal received at a gain control input 13 of the variable gain input amplifier 16 and provides the resulting signal at its output 15 . The output 15 of the variable gain input amplifier 16 is coupled to input 17 of a main filter 18 . The main filter 18 processes the signal received at its input 17 and produces a processed output signal at its output 19 . The output 19 of the main filter 18 is coupled to input 21 of a variable gain output amplifier 20 . The variable gain output amplifier 20 amplifies or attenuates the signal received at its input 21 depending on a gain control signal received at a gain control input 23 of the variable gain output amplifier 20 and provides a resulting signal at its output 24 . The gain of the variable gain output amplifier 20 is the inverse of the gain of the variable gain input amplifier 16 . The output 24 of the variable gain output amplifier 20 is connected to the output 22 of the signal processing system 10 .

[0022] The signal strength detector 14 measures the strength (e.g., the voltage envelope) of the signal applied to the input 11 of the signal strength detector 14 and provides a gain control signal at its output 25 , which is connected to the gain control inputs 13 and 23 of the variable gain input amplifier 16 and the variable gain output amplifier 20 , respectively. Depending on the strength of the signal at the input 11 of the signal strength detector 14 , different gain control signals are provided at the output 25 of the signal strength detector 14 . If the signal applied to the input 12 of the signal processing system 10 is small, the strength detector 11 provides a gain control signal that causes the variable gain input amplifier 16 to have a relatively high gain, thereby causing the signal applied to the input 12 of the signal processing system 10 to be amplified before it is applied to the main filter 18 , such that the signal is above the noise floor of the filter 18 , i.e., the noise generated by the filter. If the signal applied to the input 12 of the signal processing system 10 , the strength deflector 14 provides a gain control signal that causes the variable gain input amplifier 16 to have a relatively low gain, thereby causing the signal applied to the input 12 of the signal processing system 10 to be slightly amplified or even attenuated before it is applied to the main filter 18 to avoid saturating the main filter 18 .

[0023] FIG. 2 illustrates an exemplary signal processing system 100 in accordance with the present invention. The signal processing system 100 generates a processed signal with a strong in channel component well above the filter noise. The signal processing system 100 includes a system input 102 , a main filter 106 , a switching unit 130 , a comparator 136 , a shift register 144 , a strength detector 154 , a gain control unit 172 , and a system output 190 .

[0024] A signal received by the system input 102 of the signal processing system 100 , which typically includes an in-band component and an out-band component, is applied to an input 104 of the main filter 106 . In the present embodiment, the main filter 106 is a second order filter, which includes two integrators (not shown in FIG. 2 ). Preferably, the main filter 106 has enough linear range to accommodate the in-band component and the out-band component of the signal without saturating. Each of the first and second integrators has a variable input gain stage and a variable output gain stage associated with it (not shown in FIG. 2 ). The main filter 106 processes the signal received at its input 104 as controlled by respective signals received at inputs 108 , 110 , 112 , 114 and 116 . These signals control the gain of the variable input gain stage and the variable output gain stage for each of the first and second integrators. The gain of the variable input gain stage and variable output gain stages associated with the first integrator should only be changed when the output of the first integrator is at or near zero. By changing the gain of the variable input gain stage and the variable output gain stage associated with the first integrator when the output of the first integrator is at or near zero, little or no transients are created in the signal produced at the output of the first integrator. Likewise, the gain of the variable input gain stage and the variable output gain stage associated with the second integrator should only be changed when the output of the second integrator is at or near zero. The main filter 106 produces a processed signal at each of its outputs 118 , 120 and 122 . The signal produced at the output 118 of the main filter 106 is the output of the first integrator of the main filter 106 . The output 118 of the main filter 106 is connected to an input 124 of the switching unit 130 , and an input 152 of the strength detector 154 . The signal produced at the output 120 of the main filter 106 is the output of the second integrator of the main filter 106 . The output 120 of the main filter 106 is connected to another input 126 of the switching unit 130 . The signal produced at the output 122 of the main filter 106 is the output of the variable gain output stage associated with the first integrator of the main filter 106 . The output 122 of the main filter 106 is connected to the system output 190 of the signal processing system 100 . The structure and operation of the main filter 106 is described in greater detail hereinbelow with reference to FIG. 3 .

[0025] The switching unit 130 applies one of the signals received at its inputs 124 , 126 to its output 132 in response to a signal received at an input 128 . If a logical one voltage level (i.e., 5 V) is received at the input 128 , the switching unit 130 connects the input 124 and the output 132 , and disconnects the input 120 from the output 132 . If a logical zero voltage level (i.e., ground potential) is received at the input 128 , the switching unit 130 connects the input 126 to the output 132 and disconnects the input 124 from the output 132 . The output 132 is connected to an input 134 of the comparator 136 .

[0026] The comparator 136 compares a signal received at the input 134 against a reference voltage. If the voltage of the signal received at the input 134 is approximately equal to the reference voltage, the comparator 136 produces a signal equal to a logical one voltage level at an output 138 of the comparator 136 . If the voltage of the signal received at the input 134 is not approximately equal to the reference voltage, the comparator 136 produces a signal equal to a logical zero voltage level at the output 138 of the comparator 136 . The output 138 of the comparator 136 is connected to a clock input 140 of the shift register 144 . In the present embodiment, the reference voltage may be zero.

[0027] The shift register 144 determines which of the outputs of the integrators of the main filter 106 the comparator 136 should measure against the reference voltage. A reset/enable input 142 of the shift register 144 is connected to an output 176 of the gain control unit 172 . Outputs 146 , 148 , 150 of the shift register 144 are connected to inputs 166 , 168 , 170 , respectively, of the gain control unit 172 . If a logical one voltage level is received at the reset/enable input 142 , the shift register 144 provides a logical one voltage level signal at the output 146 , a logical zero voltage level signal at the output 148 and a logical zero voltage level signal at the output 150 . If a logical zero voltage level signal is received at the reset/enable input 142 and a positive edge (i.e., a logical zero voltage level changing to a logical one voltage level) is received at the input 140 , the shift register 144 produces a logical zero voltage level signal on the output 146 , produces a signal on the output 148 equal to the signal formerly on the output 146 , and produces a signal on the output 150 equal to a logical OR of the signal formerly on the output 148 and the signal formerly on the output 150 . The structure and operation of the shift register will be described in greater detail hereinbelow with reference to FIG. 5 .

[0028] The signal strength detector 154 selects an amplification factor that is the most suitable for processing the signal received by the system input 102 of the signal processing system 100 . The input 152 of the signal strength detector 154 is connected to the output 118 of the main filter 106 , and outputs 156 and 158 of the signal strength detector 154 are connected to inputs 160 and 162 , respectively, of the gain control unit 164 . The signal strength detector 154 detects the voltage envelope of a signal received at the input 152 of the signal strength detector 154 . A combination of a rectifier and a low-pass filter, well-known for use in many other applications, is one example of a circuit which can be used as an envelope detector of the signal strength detector 154 . The signal strength detector 154 determines if the voltage envelope of the signal provided by the output 118 of the main filter 106 is below a first threshold whereby the signal to noise ratio of the output signal of the main filter 106 is approaching a minimum tolerable value with the main filter 106 having the present amplification factors, or exceeds a second threshold whereby the main filter 106 is entering saturation with the present amplification factors.

[0029] If the signal strength detector 154 detects that the voltage envelope of the signal received at its input 152 is not below the first threshold or does not exceed the second threshold, the signal strength detector 154 produces a signal equal to a logical zero voltage level on the output 156 , and a signal equal to a logical zero voltage level on the output 158 . For purposes of the specification and claims, positive logic is assumed. If the signal strength detector 154 detects that the voltage envelope of the signal received at its input 152 falls below the first threshold and does not exceed the second threshold, the signal strength detector 154 produces a logical one voltage level signal on its output 158 , and a logical zero voltage level signal on its output 156 . If the signal strength detector 154 detects that the voltage envelope of the signal received at its input 152 exceeds the first threshold and exceeds the second threshold, the signal strength detector produces a logical zero voltage level signal on its output 158 , and a logical one voltage level signal on its output 156 .

[0030] The gain control unit 172 , responsive to signals received at its inputs 160 , 162 , 166 , 168 , 170 , provides signals at its output 176 to control the preset/enable input 142 of the shift register 144 , and provides signals at its outputs 178 , 180 , 182 , 184 , 186 to control the respective amplification factors of the variable gain input stage associated with the first integrator, the variable gain output stage associated with the first integrator, the variable gain input stage associated with the second integrator, and the variable gain output stage associated with the second integrator. The outputs 178 , 180 , 182 , 184 , 186 of the gain control unit 172 are connected to the inputs 108 , 110 , 112 , 114 , 116 , respectively, of the main filter 106 . The output 176 of the gain control unit 172 is connected to the preset/enable input 142 of the shift register 144 .

[0031] The gain control unit 172 provides signals to the main filter 106 and the shift register 144 that allow the amplification factors of the amplifiers within the main filter 106 to vary without causing transients to appear on signals at the system output 190 of the signal processing system 100 . The gain control unit 172 begins the process of changing the amplification factors of the amplifiers of the main filter 106 by providing the preset/enable input 142 of the shift register 144 with a logical one voltage level signal to enable the shift register, which in turn provides a logical one voltage level signal to the input 128 of the switching unit 130 . Once the comparator 136 senses that the signal received at the input 124 is equal to the reference voltage, the shift register 144 shifts the signals at its outputs 146 , 148 , 150 , and causes a logical zero voltage level signal to be provided to the input 128 of the switching unit. This causes the gain control unit 172 to provide the main filter 106 with appropriate signals on its inputs 108 , 110 , 112 , 114 to change the amplification factors of the variable gain input stage and the variable gain output stage associated with the first integrator, and the variable gain input stage associated with the second integrator of main filter 106 to the desired values. The amplification factor of the variable gain input stage associated with the second integrator must be changed at this point to compensate for the amplification factor change of the variable gain input stage associated with the first integrator. Then, once the comparator 136 senses that the signal received at the input 124 is equal to the reference voltage again, the shift register 144 shifts the signals at its outputs 146 , 148 , 150 , causing the gain control unit 172 to provide the main filter 106 with the appropriate signals on its inputs 112 , 114 , 116 to change the amplification factors of the variable gain input stage and the variable gain output stage associated with the second integrator.

[0032] FIG. 3 illustrates the main filter 106 as shown in FIG. 2 . The main filter 106 is a second order filter, and includes two integrators, a first integrator and a second integrator. Each of the integrators is associated with a respective variable gain input stage and a respective variable gain output stage. The variable gain input stage associated with the first integrator consists of resistors 216 , 210 , 204 , 252 , switches 232 , 224 , a capacitor 246 , and an operational amplifier 240 . The first integrator consists of the operational amplifier 240 , the capacitor 246 and the resistor 252 . The variable gain output stage associated with the first integrator consists of an operational amplifier 376 , resistors 360 , 384 , 390 , 205 , and switches 213 , 398 . The variable gain input stage associated with the second integrator consists of resistors 258 , 264 , 278 , switches 272 , 286 , a capacitor 334 , and an operational amplifier 328 . The second integrator consists of the operational amplifier 328 , and the capacitor 334 . The variable gain output amplification stage associated with the second integrator includes resistors 252 , 292 , 298 , 312 , 340 , 354 , switches 306 , 320 , operational amplifiers 240 , 348 , and the capacitor 246 . A signal received at the input 104 is applied to a terminal 202 of the resistor 204 , a terminal 208 of the resistor 210 , and a terminal 214 of the resistor 216 ; a signal received at the input 108 is applied to a switch control terminal 230 of the switch 232 , and a switch control terminal 211 of the switch 213 ; a signal received at the input 110 is applied to a switch control terminal 222 of the switch 224 and switch control terminal 396 of switch 398 ; a signal received at the input 112 is applied to a switch control terminal 284 of the switch 286 ; a signal received at the input 114 is applied to a switch control terminal 304 of the switch 306 , and a switch control terminal 270 of the switch 272 ; and a signal received at the input 116 is applied to a switch control terminal 318 of the switch 320 . Switches 222 , 232 , 213 , 398 , 320 and 306 may each be implemented as a CMOS transmission gate, in which an NMOS transistor and a PMOS transistor are connected in parallel with each other, the gate of the PMOS transistor is connected to the output of an inverter, the input of the inverter and the gate of the NMOS transistor are connected to each other and serve as the switch control terminal, and the source and drain of each transistor serve as the switch terminals. When a CMOS transmission gate is closed, the NMOS transistor and the PMOS transistor are active, such that a signal received on one terminal of the CMOS transmission gate is conveyed to the other terminal of the CMOS transmission gate. When a CMOS transmission gate is open, the NMOS transistor and the PMOS transistor are not active, such that a signal received on one terminal of the CMOS transmission gate is not conveyed to the other terminal of the CMOS transmission gate.

[0033] The variable gain input stage associated with the first integrator may amplify the signal received at the input 104 by one of three amplification factors and produce an output signal at a node 217 . If the signals received at the inputs 108 and 110 are a logical zero voltage level (i.e., ground potential) and a logical zero voltage level, respectively, the variable gain input stage amplifies the signal received at the input 104 by a relatively low amplification factor. In the present embodiment, the relatively low amplification factor may be one-tenth. If the signals received at the inputs 108 and 110 are a logical zero voltage level and a logical one voltage level (i.e., 5V), respectively, the variable gain input stage amplifies the signal received at the input 104 by a relatively moderate amplification factor. In the present embodiment, the relatively moderate amplification factor is one. If the signals received at the inputs 108 and 110 are a logical one voltage level and a logical zero voltage level, respectively, the variable gain input stage amplifies the signal received at the input 104 by a relatively high amplification factor. In the present embodiment, the relatively high amplification factor is ten. In the present embodiment, the signals received at the inputs 108 and 110 should never both be a logical one voltage level.

[0034] The other terminal 206 of the resistor 204 is coupled to a terminal 226 of the switch 224 , a terminal 234 of the switch 232 , an inverted input 236 of the operational amplifier 240 , a terminal 244 of the capacitor 246 , a terminal 250 of the resistor 252 , a terminal 290 of the resistor 292 , a terminal 296 of the resistor 298 and a terminal 310 of the resistor 312 , all of which form a node 217 . In the present embodiment, the resistor 204 has a resistance of 200 kΩ.

[0035] The other terminal 212 of the resistor 210 is connected to a terminal 220 of the switch 224 . In the present embodiment, the resistor 210 has a resistance of 22.22 kΩ. The terminal 226 of the switch 224 is connected to the node 217 . The switch 224 closes to connect its terminal 220 to its other terminal 226 if the signal received at the switch control terminal 222 is a logical one voltage level. If the signal at the switch control terminal 222 is at a logical zero voltage level, the switch 224 opens to disconnect its other terminal 220 from its terminal 226 resulting in an open circuit between those terminals.

[0036] The other terminal 218 of the resistor 216 is connected to a terminal 228 of the switch 232 . In the present embodiment, the resistor 216 has a resistance of 2.02 kΩ. The terminal 234 of the switch 232 is connected to the node 217 . The switch 232 closes to connect its terminal 228 to its other terminal 234 if the signal received at its switch control terminal 230 is a logical one voltage level. If the signal at the switch control terminal 230 is a logical zero voltage level, the switch 232 opens to disconnect its terminal 228 from its other terminal 234 resulting in an open circuit between those terminals.

[0037] The first integrator filters the signal received at the node 217 and produces a signal at a node 219 , which is formed by the common connection of the other terminal 254 of the resistor 252 , an output 242 of the operational amplifier 240 , the other terminal 248 of the capacitor 246 , the terminal 256 of the resistor 258 , the terminal 262 of the resistor 264 , the terminal 276 of the resistor 278 , the terminal 358 of the resistor 360 and the output 118 . The other terminal 254 of the resistor 252 is connected to the node 219 . In the present embodiment, the resistor 254 has a resistance of 20 kΩ. The other terminal 248 of the capacitor 246 is connected to the node 219 . In the present embodiment, the capacitor 246 has a capacitance of 80 pF. In the present embodiment, the operational amplifier 240 is a model LF347 operational amplifier available from National Semiconductor Corporation of Santa Clara, Calif.

[0038] The variable gain output stage associated with the first integrator may amplify the signal received at the node 219 by one of three factors and produce an amplified signal at the output 122 . If the signals received at the inputs 108 and 110 are a logical zero voltage level and a logical zero voltage level, respectively, the variable gain output stage amplifies the signal received at the node 219 by a relatively high amplification factor. In the present embodiment, the relatively high amplification factor may be ten. If the signals received at the inputs 108 and 110 are a logical zero voltage level and a logical one voltage level, respectively, the variable gain output stage amplifies the signal received at the node 219 by a relatively moderate amplification factor. In the present embodiment, the relatively moderate amplification factor is one. If the signals received at the inputs 108 and 110 are a logical one and a logical zero voltage level, respectively, the variable output gain stage amplifies the signal received at the node 219 by a relatively low amplification factor. In the present embodiment, the relatively low amplification factor is one-tenth. In the present embodiment, the signals received at the inputs 108 and 110 should never both be a logical one voltage level.

[0039] The other terminal 370 of the resistor 360 is connected to an inverted input 374 of the operational amplifier 376 , a terminal 382 of the resistor 384 , a terminal 388 of the resistor 390 , and a terminal 203 of the resistor 205 . The common connection of the other terminal 370 of the resistor 360 , the inverted input 374 of the operational amplifier 376 , the terminal 382 of the resistor 384 , the terminal 388 of the resistor 390 , and the terminal 203 of the resistor 205 form a node 225 . In the present embodiment, the resistor 360 has a resistance of 20 kΩ. In the present embodiment, the operational amplifier 376 is a model LF347 operational amplifier available from National Semiconductor Corporation of Santa Clara, Calif. The other terminal 386 of the resistor 384 is connected to the output 122 of the main filter 106 . In the present embodiment, the resistor 384 has a resistance of 200 kΩ.

[0040] The other terminal 392 of the resistor 390 is connected to a terminal 394 of the switch 398 . In the present embodiment, the resistor 390 has a resistance of 22.22 kΩ. The other terminal 201 of the switch 398 is connected to the output 122 of the main filter 106 . The switch 398 closes to connect its terminal 394 to its other terminal 201 if the signal received at the switch control terminal 396 is a logical one voltage level. If the signal at the switch control terminal 396 is a logical zero voltage level, the switch 398 opens to disconnect its terminal 394 from its other terminal 201 resulting in an open circuit between those terminals.

[0041] The other terminal 207 of the resistor 205 is connected to a terminal 209 of the switch 213 . In the present embodiment, the resistor 205 has a resistance of 2.02 kΩ. The other terminal 215 of the switch 213 is connected to the output 122 of the main filter 106 . The switch 213 closes to connect its terminal 209 to its other terminal 215 if the signal received at the switch control terminal 211 is a logical one voltage level. If the signal at the switch control terminal 211 is a logical zero voltage level, the switch 213 opens to disconnect its terminal 209 from its other terminal 215 resulting in an open circuit between those terminals.

[0042] The variable gain input stage associated with the second integrator may amplify the signal received at the node 219 by one of three factors and produce an output signal at a node 221 , at which the other terminal 288 of the switch 286 , the other terminal 274 of the switch 272 , the other terminal 260 of resistor 258 , one terminal 332 of the capacitor 334 and the inverting impact of the operational amplifier 328 are commonly connected. If the signals received at the inputs 112 and 114 are a logical zero voltage level and a logical zero voltage level, respectively, the variable gain input stage amplifies the signal received at the node 221 by a relatively low amplification factor. In the present embodiment, the relatively low factor is one-tenth. If the signals received at the inputs 112 and 114 are a logical zero voltage level and a logical one voltage level, respectively, the variable gain input stage amplifies the signal received at the node 221 by a relatively moderate amplification factor. In the present embodiment, the relatively moderate amplification factor is one. If the signals received at the inputs 112 and 114 are a logical one voltage level and a logical zero voltage level, respectively, the variable gain input stage amplifies the signal received at the node 221 by a relatively high amplification factor. In the present embodiment, the relatively high amplification factor is ten. In the present embodiment, the signals received at the inputs 112 and 114 should never both be a logical one voltage level. The other terminal 260 of the resistor 258 is connected to node 221 . In the present embodiment, the resistor 258 has a resistance of 10 kΩ.

[0043] The other terminal 266 of the resistor 264 is connected to one terminal 268 of the switch 272 . In the present embodiment, the resistor 264 has a resistance of 1.11 kΩ. The other terminal 274 of the switch 272 is connected to the node 221 . The switch 272 closes to connect its terminal 268 to its other terminal 274 if the signal received at the switch control terminal 270 is a logical one voltage level. If the signal at the switch control terminal 270 is a logical zero voltage level, the switch 272 opens to disconnect its terminal 268 from its other terminal 274 resulting in an open circuit between those terminals.

[0044] The other terminal 280 of the resistor 278 is connected to one terminal 282 of the switch 286 . In the present embodiment, the resistor 278 has a resistance of 0.10 kΩ. The other terminal 288 of the switch 286 is connected to the node 221 . The switch 286 closes to connect its terminal 282 to its other terminal 288 if the signal received at the switch control terminal 284 is a logical one voltage level. If the signal at the switch control terminal 284 is a logical zero voltage level, the switch 286 opens to disconnect its terminal 282 from its other terminal 288 resulting in an open circuit between those terminals.

[0045] The second integrator filters the signal received at the node 221 and produces a filtered signal at the output 120 of the main filter 106 . The other terminal 336 of the capacitor 334 is connected to the output 120 . In the present embodiment, the capacitor 334 has a capacitance of 80 pF.

[0046] The output 330 of the operational amplifier 328 is connected to the output 120 of the main filter 106 . In the present embodiment, the operational amplifier 328 may be implemented using a model LF347 operational amplifier available from National Semiconductor Corporation of Santa Clara, Calif.

[0047] The variable gain output stage associated with the second integrator may amplify the signal received at terminal 338 of the resistor 340 by one of three factors and produce an amplified signal at the node 217 . If the signals received at the inputs 116 and 114 are a logical zero voltage level and a logical zero voltage level, respectively, the variable gain output stage amplifies the signal received at terminal 338 of the resistor 340 by a relatively low amplification factor. In the present embodiment, the relatively low amplification factor is one-tenth. If the signals received at the inputs 116 and 114 are a logical zero voltage level and a logical one voltage level, respectively, the variable gain output stage amplifies the signal received at terminal 338 of the resistor 340 by a relatively moderate amplification factor. In the present embodiment, the relatively moderate amplification factor is one. If the signals received at the inputs 116 and 114 are a logical one voltage level and a logical zero voltage level, respectively, the variable gain output stage amplifies the signal received at terminal 338 of the resistor 340 by a relatively high amplification factor. In the present embodiment, the relatively high amplification factor is ten. In the present embodiment, the signals received at the inputs 116 and 114 should never both be a logical one voltage level.

[0048] The terminal 338 of the resistor 340 is coupled to the output 120 . The other terminal 342 of the resistor 340 corresponds with an inverted input 344 of the operational amplifier 348 and the other terminal 352 of the resistor 354 . In the present embodiment, the resistor 340 has a resistance of 10 kΩ.

[0049] The terminal 356 of the resistor 354 is connected to the node 223 , at which the terminal 356 of resistor 354 , the output 350 of the operational amplifier 348 , the other terminal 394 of the resistor 292 , the other terminal 308 of the switch 306 and the other terminal 322 of the switch 320 are commonly connected. In the present embodiment, the resistor 354 has a resistance of 10 kΩ.

[0050] The output 350 of the operational amplifier 348 is connected to the node 223 . In the present embodiment, the operational amplifier 348 is implemented using the model LF347 operational amplifier available from National Semiconductor Corporation of Santa Clara, Calif. In the present embodiment, the resistor 292 has a resistance of 10 kΩ.

[0051] The other terminal 300 of the resistor 298 is connected to terminal 302 of the switch 306 . In the present embodiment, the resistor 298 has a resistance of 1.11 kΩ. The other terminal 308 of the switch 306 is connected to the node 223 . The switch 306 closes to connect its terminal 302 to its other terminal 308 if the signal received at the switch control terminal 304 is a logical one voltage level. If the signal at the switch control terminal 304 is a logical zero voltage level, the switch 306 opens to disconnect its terminal 302 from its other terminal 308 resulting in an open circuit between those terminals.

[0052] The other terminal 314 of the resistor 312 is connected to a terminal 316 of the switch 320 . In the present embodiment, the resistor 312 has a resistance of 0.10 kΩ. The other terminal 322 of the switch 320 is connected to the node 223 . The switch 320 closes to connect its terminal 316 to its other terminal 322 if the signal received at the switch control terminal 318 is a logical one voltage level. If the signal at the switch control terminal 318 is a logical zero voltage level, the switch 320 opens to disconnect its terminal 316 from its other terminal 322 resulting in an open circuit between those terminals.

[0053] FIG. 4 illustrates an exemplary embodiment of the switching unit 130 as shown in FIG. 2 . The switching unit 130 includes an input 124 , an input 126 , an input 128 , a first switch 406 , a second switch 416 and an output 132 . The switching unit 130 provides one of the signals received at the inputs 124 , 126 to the output 132 in response to a signal received at the input 128 .

[0054] A signal received at the input 124 is applied to one terminal 402 of the first switch 406 ; a signal received at the input 126 is applied to one terminal 412 of the second switch 416 ; and a signal received at the input 128 is applied to a switch control terminal 404 of the first switch 406 and an inverting switch control terminal 414 of the second switch 416 . The first switch 406 closes to connect its terminal 402 to its other terminal 408 if the signal received at the switch control terminal 404 is a logical one voltage level (i.e., 5 V). If the signal at the switch control terminal 404 is a logical zero voltage level (i.e., ground potential), the first switch 406 opens to disconnect its terminal 402 from its other terminal 408 resulting in an open circuit between those terminals. The other terminal 408 of the first switch 406 is connected to the output 132 of the switching unit 130 .

[0055] The second switch 416 closes to connect its terminal 412 to its other terminal 418 if the signal received at the inverting switch control terminal 414 is a logical one voltage level. If the signal at the inverting switch control terminal 414 is a logical zero voltage level, the second switch 416 opens to disconnect its terminal 412 from its other terminal 418 resulting in an open circuit between those terminals. The other terminal 418 of the first switch 416 is connected to the output 132 of the switching unit 130 .

[0056] FIG. 10 illustrates the comparator 136 . The comparator 136 includes an input 134 , an output 138 , a comparator circuit 1006 , and a reference voltage 1003 . The comparator circuit 1006 has an input 1002 , an input 1004 , and an output 1008 . In the present embodiment, the comparator 136 may be implemented using a model LM219 comparator available from National Semiconductor Corporation of Santa Clara, Calif. The input 1002 is connected to the input 134 , the input 1004 is connected to the reference voltage 1003 , and the output 1008 is connected to the output 138 . In the present embodiment, the reference voltage 1003 is ground. The comparator circuit 1006 measures a signal received at the input 1002 against the reference voltage 1003 received at the input 1004 . If the voltage of the signal received at the input 1002 is approximately equal to the reference voltage 1003 received at the input 1004 , the comparator circuit 1006 produces a logical one voltage level signal at the output 1008 . If the voltage of the signal received at the input 1002 is not approximately equal to the reference voltage 1003 , the comparator circuit 1006 produces a logical zero voltage level signal at the output 1008 . The output 138 of the comparator 136 is connected to the clock input 140 of the shift register 144 .

[0057] FIG. 5 illustrates an exemplary embodiment of the shift register 144 as shown in FIG. 2 . The shift register 144 includes an clock input 140 , an input 142 , a first positive edge triggered D-type flip flop 508 , a second positive edge triggered D-type flip flop 518 , a third positive edge triggered D-type fl