DETAILED DESCRIPTION OF THE INVENTION

[0023] Generally, the present invention includes methods of encapsulating intermediate conductive elements, such as bond wires, and semiconductor dice in assemblies and relatively thin-profile packages in which a carrier substrate is secured to the active surface of a semiconductor die, such as BOC-type assemblies and packages, including, without limitation, BGA configurations, tape BGA (TBGA) configurations, and micro tape BGA (MTBGA) configurations of such assemblies and packages. While the present invention is described in terms of certain specific, exemplary embodiments, the specific details of these embodiments are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, that the present invention may be practiced in various combinations of the specific exemplary embodiments presented herein.

[0024] It will be appreciated that the drawings described herein are not drawn to scale, but are for exemplary purposes only. Referring now to drawing FIG. 1 A, there is shown a cross-sectional view of an assembly generally at 10 that includes a solder mask 12 according to the present invention and a carrier substrate 15 upon which the solder mask 12 is carried. In the illustrated embodiment, the carrier substrate 15 is an interposer with opposite major surfaces 16 and 18 . A slot 17 or other opening is formed through the carrier substrate 15 , somewhat centrally in the depicted embodiment, and extends from upper surface 16 to lower surface 18 . As known to those of ordinary skill in the art, the carrier substrate 15 may be formed to a desired shape and thickness and with required features for use in forming a functional semiconductor package.

[0025] The material used to fabricate the carrier substrate 15 may comprise a relatively thin, flexible film of an electrically insulative material, such as an organic polymer resin (e.g., polyimide). If the carrier substrate 15 comprises an MTBGA substrate, the thickness othereof may be on the order of about 50 μm to about 75 μm. Alternatively, the carrier substrate 15 may comprise a somewhat rigid, substantially planar member, which may be fabricated from any known, suitable materials, including, but not limited to, insulator-coated silicon, a glass, a ceramic, an epoxy resin (e.g., FR-4, FR-5, etc.), bismaleimide-triazine (BT) resin, or any other material known in the art to be suitable for use as a carrier substrate. A BT resin substrate may have a thickness of about 125 μm. Although the illustrated embodiment depicts the carrier substrate 15 as being an interposer, a solder mask 12 incorporating teachings of the present invention may also be used with other types of carrier substrates, such as circuit boards, leads, and the like, without departing from the scope of the present invention.

[0026] As shown, the upper surface 16 of the carrier substrate 15 carries conductive traces 19 , first contact areas 21 located proximate the slot 17 , and second contact areas 22 located peripherally relative to the first contact areas 21 . As shown, the second contact areas 22 are arranged in an area array, although other arrangements of second contact areas are also within the scope of the present invention. It will be appreciated that the conductive traces 19 , first contact areas 21 , and second contact areas 22 may comprise, without limitation, conductively doped polysilicon, a conductive metal or metal alloy, conductive or conductor-filled elastomer, or any other conductive material used for electrical connections known to those of ordinary skill in the art.

[0027] The solder mask 12 is formed as a substantially planar member with a relatively large central opening 13 formed therethrough. In addition, the solder mask 12 includes smaller apertures 14 that are positioned so as to expose corresponding second contact areas 22 of the carrier substrate 15 and to facilitate the formation of solder balls or other discrete conductive elements 52 ( FIG. 1B ) on the second contact areas 22 . As illustrated in FIG. 1 A, the solder mask 12 , as configured, is superimposed over a substantial portion of the carrier substrate 15 (also shown in FIG. 2 ). The solder mask 12 has an upper surface 20 and a lower surface 23 (as oriented in FIGS. 1A and 1B ). In the illustrated embodiment, the lower surface 23 of the solder mask 12 is secured to the upper surface 16 of the carrier substrate 15 . As known in the art, an adhesive material may be used to attach the solder mask 12 to the upper surface 16 of the carrier substrate 15 . Alternatively, the material of the solder mask 12 may secure the solder mask 12 to the upper surface 16 of the carrier substrate 15 .

[0028] The solder mask 12 may be prefabricated and adhered to the carrier substrate 15 or it may be formed on the carrier substrate 15 , both processes that are known in the art. The material used for the solder mask 12 is an electrically insulative material and, if it is to remain on a functioning semiconductor die 24 ( FIG. 1B ), the material of the solder mask 12 may be selected to have a coefficient of thermal expansion (CTE) similar to that of the material used for the carrier substrate 15 . When the carrier substrate 15 and solder mask 12 have similar or substantially “matched” CTEs, the likelihood that these elements of a package will be mechanically stressed or that the solder mask 12 will delaminate from the carrier substrate during thermal cycling of a semiconductor die 24 ( FIG. 1B ), which may occur during testing or operation thereof, is reduced. Materials that may be used for the solder mask 12 include, but are not limited to, plastics, resins, acrylics, urethanes, and polyimides.

[0029] As an example of fabrication of the solder mask, known photolithography processes may be employed. When photolithograpy processes are used, a layer of dielectric photoimageable material, such as a photoresist, may be formed on the upper surface 16 of the carrier substrate 15 by known processes, such as by spin-on techniques. The photoimageable material may then be selectively exposed or patterned, then developed, followed by removal of unpolymerized portions thereof to form the solder mask 12 therefrom.

[0030] Another exemplary method for forming a solder mask includes screen printing a layer of dielectric material, such as a polyimide, onto selected regions of the upper surface 16 of the carrier substrate 15 .

[0031] In yet another exemplary method, a solder mask 12 may be formed as either a single layer or a plurality of contiguous, at least partially superimposed, mutually adhered layers of dielectric material by known stereolithography techniques. In such techniques, selected regions of a layer of at least partially unconsolidated material, such as an uncured photoimageable polymer, are selectively consolidated, such as by exposing the uncured photoimageable polymer in the selected regions to an energy beam comprising a curing wavelength of radiation. This process may be repeated until a structure of the desired height is formed.

[0032] Referring now to FIG. 1 B, there is shown a cross section of the assembly 10 of FIG. 1A that also includes a semiconductor die 24 . The semiconductor die 24 has an active surface 26 and an opposite back side 28 . As known to those of ordinary skill in the art, bond pads 30 are located on the active surface 26 of the semiconductor die 24 . The bond pads 30 facilitate the communication of electrical signals to and from various circuit elements, or “integrated circuits” (not shown), that may be present on or within the active surface 26 of the semiconductor die 24 . As illustrated, the semiconductor die 24 is attached to the carrier substrate 15 with an adhesive element 32 , as known in the art. The adhesive element 32 may comprise a film or tape which is at least partially coated with adhesive material or a quantity of adhesive material, such as a pressure sensitive adhesive or a curable adhesive (e.g., an epoxy). If the adhesive element 32 comprises a polymeric film or tape, the adhesive element may also include an opening 38 therethrough that corresponds to and aligns with the slot 17 in the carrier substrate 15 .

[0033] Alternatively, the adhesive element 32 may comprise a plurality of individual strips. If the adhesive element 32 comprises strips, any remaining spaces between superimposed portions of the semiconductor die 24 and the carrier substrate 15 may be filled with an underfill material of a type known in the art (e.g., a low viscosity silicone, epoxy, etc.).

[0034] Although FIG. 1B depicts the bond pads 30 (shown also in FIG. 2 ) aligned substantially linearly along the center of the active surface 26 of the semiconductor die 24 , it will be appreciated that other bond pad 30 arrangements are meant to be encompassed by the present invention. As depicted in FIG. 1 B, after the semiconductor die 24 , the adhesive element 32 , and the carrier substrate 15 have been properly positioned relative to one another and secured together to form the assembly 10 , each bond pad 30 of the semiconductor die 24 may be electrically connected to its corresponding first contact area 21 on the carrier substrate 15 . As depicted in FIG. 1 B, each such electrical connection may be accomplished with an intermediate conductive element 40 , such as a bond wire, a conductive TAB element carried upon a flexible dielectric film, a bonded lead, or the like, which extends between each bond pad 30 and its corresponding first contact area 21 , as well as through the slot 17 of the carrier substrate 15 .

[0035] Referring now to FIG. 2 , there is shown a perspective view of the assembly 10 shown in FIG. 1B . As illustrated, the solder mask 12 overlies the periphery of the carrier substrate 15 . The central opening 13 in the solder mask 12 exposes the intermediate conductive elements 40 , a portion of the upper surface 16 of the carrier substrate 15 , the first contact areas 21 of the carrier substrate 15 , and a portion of the active surface 26 of the semiconductor die 24 along which the bond pads 30 are located.

[0036] To seal the components from moisture, contamination and corrosion, and to protect against mechanical shock, the components exposed through the central opening 13 in the solder mask 12 are encapsulated. As known to those of ordinary skill in the art, an encapsulant material 46 (as shown in FIG. 4 ) may be applied from a top side 34 of an assembly 10 of the present invention or from a bottom side 36 of an inverted assembly 10 ′ that incorporates teachings of the present invention, as depicted in FIG. 3 . To apply the encapsulant material 46 from the bottom side 36 of the inverted assembly 10 ′, any openings therein from which the encapsulant material 46 may escape may be covered with a coverlet 47 .

[0037] A suitable, known type of dielectric encapsulant material 46 may be introduced into the central opening 13 of the solder mask 12 , as well as into the slot 17 of the carrier substrate 15 and around the intermediate conductive elements 40 that are laterally contained within the central opening 13 and slot 17 . As shown in FIG. 2 , the slot 17 does not extend beyond an outer periphery of the semiconductor die 24 . Thus, the semiconductor die 24 , the edges of opening 38 of the adhesive element 32 and of the slot 17 of the carrier substrate 15 , and the solder mask 12 together contain the encapsulant material 46 . In the illustrated embodiment, the encapsulant material 46 is introduced using an encapsulant dispenser needle 48 (as shown in FIG. 3 ). However, the encapsulant material 46 may be introduced using any suitable process known in the art. The solder mask 12 functions to laterally confine the encapsulant material 46 . The encapsulant material 46 is introduced until an upper surface of the encapsulant material 46 is substantially level with the upper surface 20 of the solder mask 12 if encapsulant material 46 is introduced while an assembly 10 is oriented as shown in FIGS. 1B and 2 .

[0038] The encapsulant material 46 may comprise a flowable, dielectric material with a CTE substantially the same as the CTEs of the materials from which the carrier substrate 15 and the solder mask 12 are formed. It will be appreciated that the encapsulant material 46 may comprise, but is not limited to, a thermoplastic resin, an epoxy, a polyester, a polyimide, a cyanoacrylate, a silicone, and a urethane. Depending on the type of encapsulant material 46 , curing or setting thereof (e.g., by application of heat and/or pressure, by exposure of photoimageable polymer encapsulant materials to an appropriate wavelength of radiation, by use of an appropriate catalyst, or in any other manner known to those of ordinary skill in the art) may be necessary.

[0039] Referring now to FIG. 3 , there is shown an inverted perspective view of a semiconductor device assembly 10 ′ that includes openings 17 ′ and 38 ′ in the carrier substrate 15 ′ and the adhesive element 32 ′, respectively, that extend beyond at least one outer peripheral edge of the semiconductor die 24 , leaving a space 44 uncovered by the semiconductor die 24 . A coverlet 47 , such as a film, tape, or other substantially planar member, is secured to the upper surface 20 (now inverted) of the solder mask 12 . The coverlet 47 may be at least partially coated with an adhesive material 50 to secure the same to the upper surface 20 of the solder mask 12 . The adhesive material 50 used on the coverlet 47 facilitates the ready removal of the coverlet 47 from the upper surface 20 of the solder mask 12 . The coverlet 47 may also have sufficient flexibility to conform to any irregularities or nonplanaraties of the upper surface 20 of the solder mask 12 .

[0040] An encapsulant material 46 may be introduced into the bottom side 36 of the assembly 10 ′ through the space 44 , which is continuous with the slot 17 ′ of the carrier substrate 15 ′ and the central opening 13 of the solder mask 12 , by way of an encapsulant dispenser needle 48 or otherwise, as known in the art. The coverlet 47 precludes loss of encapsulant material 46 during inversion of assembly 10 ′. Air may be displaced by encapsulant material 46 through the open space 44 at the end of the slot 17 ′, opposite that into which the encapsulant material 46 is introduced.

[0041] Referring now to FIG. 4 , there is shown the assembly 10 of FIG. 2 after the encapsulant 46 material has cured or set. As previously described, it is apparent that an upper surface 51 of the solidified encapsulant material 46 is substantially coplanar with the upper surface 20 of the solder, mask 12 . Referring again to FIG. 1 B, it will be apparent that the encapsulant 46 material substantially encapsulates the intermediate conductive elements 40 , the first contact areas 21 , and the bond pads 30 and adjacent regions of the active surface 26 of the semiconductor die 24 . The top of each intermediate conductive element 40 and the upper surface 51 of the encapsulant material 46 are separated by a distance which is sufficient to prevent electrical interference between signals passing through intermediate conductive elements 40 and conductive elements or components that are positioned adjacent to the upper surface 51 ( FIG. 1B ) of the encapsulant material 46 . The distance between the top of each intermediate conductive element 40 and the upper surface 51 of the encapsulant material 46 may, for example, be as much as 25 μm or greater.

[0042] Solder balls or other discrete conductive elements 52 ( FIG. 1B ) may then be formed by known processes, such as by immersing the assembly in a solder bath.

[0043] It will be appreciated that the thickness of the solder mask 12 from the upper surface 20 to the lower surface 23 may be varied depending on the height of the intermediate conductive elements 40 . It may be desirable to have a layer of encapsulant 46 that is approximately 25 μm between the upper surface of the intermediate conductive elements 40 and the upper surface 20 of the solder mask 12 . Therefore, the solder mask 12 is designed such that once the encapsulant 46 has been dispensed, the upper surface 51 of the encapsulant 46 and the upper surface 20 of the solder mask 12 is approximately 25 μm above the intermediate conductive elements 40 . It may also be desirable to design the solder mask 12 to be about half as thick as solder balls (not shown) to accommodate a subsequent solder ball formation process. Typically, the solder mask 12 of the present invention will be between about 50 μm and about 100 μm thick, as opposed to 25-50 μm thick for conventional solder masks.

[0044] Once the encapsulant material 46 has cured or set and solder balls or other discrete conductive elements 52 ( FIG. 1B ) have been formed in the apertures 14 of the solder mask 12 and on the second contact areas 22 of the carrier substrate 15 , it will be appreciated that the solder mask 12 may be left in place during subsequent use (e.g., packaging of the assembly 10 or assembly thereof with other semiconductor device components, such as circuit boards, or other electronic components), or the solder mask 12 may be removed from the assembly 10 . When left in place, the solder mask 12 may act as a spacer between the carrier substrate 15 and a higher-level package component or another electronic device (not shown).

[0045] Although the present invention has been shown and described with respect to illustrated embodiments, various additions, deletions and modifications that are obvious to a person of ordinary skill in the art to which the invention pertains, even if not shown or specifically described herein, are deemed to lie within the scope of the invention as encompassed by the following claims.