[0048] It is to be understood that the indicator “+” in the Figures indicates relatively heavy doping and the indicator “−” in the Figures indicates relatively light doping.
DETAILED DESCRIPTION OF THE EMBODIMENTS
[0049] In the following description specific details are set forth, such as specific materials, process and equipment in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known manufacturing materials, process and equipment are not set forth in detail in order not unnecessary obscure the present invention. Prepositions, such as “on”, “over”, “under”, and “beneath” are defined with respect to a planar surface of the substrate, regardless of the orientation in which the substrate is actually held. A layer is on another layer even if there are intervening layers.
1. First Embodiment
[0050] 1.1 Basic Configuration of First Embodiment:
[0051] FIG. 1 shows a basic configuration of a tunnel-injection device associated with a first embodiment of the present invention. FIG. 1 shows cross-sectional views of three adjacent unit cells in the multi-channel structure. In the multi-channel structure, a plurality of gate electrodes 40 and a plurality of source electrodes 80 are mutually arranged in parallel so as to implement an interdigital topology. The gate electrodes 40 and source electrodes 80 are respectively delineated in stripe geometries.
[0052] As shown in FIG. 1 , the basic configuration of the tunnel-injection device associated with the first embodiment of the present invention encompasses a reception layer 20 made of a first semiconductor and a plurality of barrier-forming layers 60 made of a second semiconductor having a bandgap-narrower than the first semiconductor. Each of the barrier-forming layer 60 metallurgical contacts with the reception layer 20 . Further, the tunnel-injection device encompasses a plurality of gate insulating films 30 disposed on the barrier-forming layer 60 and a plurality of gate electrodes 40 disposed on the corresponding gate insulating film 30 configured to control the width of the barrier generated at the interface between the reception layer 20 and the barrier-forming layer 60 so as to change the tunneling probability of carriers through the barrier. Here, the barrier is the band-edge discontinuity barrier ΔEc, which will be explained later with referring to the energy band diagrams shown in FIGS. 2A to 2 C.
[0053] Still further, the tunnel-injection device encompasses a carrier receiving region 10 being contact with the reception layer 20 , configured to receive the carriers injected by tunneling through the barrier and a plurality of carrier-supplying regions 18 being contact with the corresponding barrier-forming layers 60 . Each of the carrier-supplying regions 18 is connected to corresponding source electrodes 80 , and supplies the carriers to the barrier-forming layer 60 .
[0054] Although the cross-sectional view shows a plurality of separate gate electrodes 40 in FIG. 1 , these gate electrodes 40 can merge into a single piece at a rearward portion of the paper (not illustrated) or at the near side (not illustrated) of the paper so as to form a comb shape or a grid shape, for example, in an actual plan view. Similarly, although the cross-sectional view shows a plurality of separate source electrodes 80 in FIG. 1 , the source electrodes 80 can merge into single piece at a deep rearward portion of the paper (not illustrated) or at the near side of the paper so as to form a comb shape or a grid shape, for example, in an actual plan view. However, spatially isolated gate electrodes 40 and source electrodes 80 can also exist any way. The same argument can be applied to the following second to seventh embodiments, of course.
[0055] An n − type drift layer 20 laminated on an n + type SiC substrate serves as “the reception layer” in the first embodiment. Because the n − type drift layer 20 is made of SiC, as the first semiconductor, SiC is employed in the first embodiment. The n + type SiC substrate 10 serves as “the carrier receiving region”, or a drain region in the first embodiment. The drift layer 20 transports the carrier to the carrier receiving region 10 . As “the barrier-forming layers”, p − type lightly doped poly crystalline silicon (hereinafter called “polysilicon”) films 60 are laminated in predetermined regions on the drift layer 20 . Therefore, polysilicon corresponds to the second semiconductor in the first embodiment. Therefore, a p-n heterojunction is formed between the p − type lightly doped polysilicon film 60 and the drift layer 20 made of SiC.
[0056] On-predetermined regions on the n − drift layer 20 , a plurality of insulation film 70 are selectively formed. And, on the insulation films, n + type polysilicon films 18 serving as “the carrier-supplying regions” are disposed respectively. Each of the n + type polysilicon films 18 is connected to corresponding p − type lightly doped polysilicon film 60 , which serves as barrier-forming layers. And the gate insulation films 30 are formed on the top surface of the corresponding p-type lightly doped polysilicon film 60 . This gate insulation film 30 extends so as to cover regions over the drift layer 20 and the n + type polysilicon film 18 .
[0057] As the first semiconductor, various wide bandgap semiconductors other than SiC can be employed in the first embodiment. Historically, early stage in semiconductor industry, silicon (Si) material having a bandgap energy Eg=1.1 eV, or the gallium arsenide (GaAs) material having a bandgap energy Eg=1.4 eV has been firstly adopted for practical use. Compared with these preceding semiconductor materials, other semiconductor materials having wider bandgap energy Eg than these Si and GaAs are now referred as “wide bandgap semiconductor”. For example, zinc telluride (ZnTe) having a bandgap energy Eg=2.2 eV, cadmium sulfide (CdS) having a bandgap energy Eg=2.4 eV, zinc selenide (ZnSe) having a bandgap energy Eg=2.7 eV, a gallium nitride (GaN) having a bandgap energy Eg=3.4 eV, zinc sulphide (ZnS) having a bandgap energy Eg=3.7 eV and diamond having a bandgap energy Eg=5.5 eV are well known as the examples for the wide bandgap semiconductors.
[0058] SiC is one of the examples of wide bandgap semiconductor. And, various stacking sequence, or the polytypes of the SiC are known. Although, as the stacking sequence of the SiC, a hexagonal 4H polytype may be representative, a hexagonal 6H polytype, a cubic 3C polytype or any other polytypes can be used in the first embodiment. The bandgap energy Eg of 2.23 eV is reported for 3C—SiC, 2.93 eV is reported for 6H—SiC, and 3.26 eV is reported for 4H—SiC. If we use 4H—SiC as the first semiconductor, semiconductor materials having bandgap energy Eg narrower than 3.26 eV, such as 6H—SiC, ZnSe, CdS, 3C—SiC, ZnTe, GaAs, Si, germanium (Ge) can be used for the second semiconductor. If we use diamond as the first semiconductor, semiconductor materials having bandgap energy Eg narrower than 5.5 eV, such as ZnS, GaN, 6 H-SiC, ZnSe, CdS, 3 C-SiC, ZnTe, GaAs, Si, Ge can be used for the second semiconductor. If we use Si as the first semiconductor, semiconductor materials having bandgap energy Eg narrower than 1.1 eV, such as Ge, mercury cadmium telluride (HgCdTe) can be used for the second semiconductor. Exactly same argument can be hold in following second to seventh embodiments, of course.
[0059] For the condition that the reception layer 20 made of the first semiconductor can implement the p-n heterojunction with the first semiconductor so that the p-n heterojunction can serve as the constituent element of the switching device, it is necessary that a bandgap of the second semiconductor mating to the first semiconductor is narrower than the bandgap of the first semiconductor—the reason will be understood from the discussion bellows. On the contrary, if the bandgap of the second semiconductor for the p-n heterojunction is larger than the bandgap of the first semiconductor, it does not function as the switching device. Therefore, the bandgap of the second semiconductor configured to implement the p-n heterojunction must be narrower than the bandgap of the first semiconductor.
[0060] If SiC is adopted as the first semiconductor, the favorable examples for the second semiconductor, or the narrower bandgap semiconductor, single crystalline silicon, polysilicon, or amorphous silicon can be used, because the deposition of the single crystalline silicon, the amorphous silicon or the polysilicon on the SiC substrate 10 is easy. Furthermore, by employing the single crystalline silicon, the amorphous silicon or the polysilicon, the process of oxidations, photolithographic delineations, various selective etchings, or various selective dopings can be executed easily.
[0061] 1.2 Operation of Tunnel-Injection Device of First Embodiment:
[0062] By means of the energy band diagram shown in FIG. 2A to FIG. 2 C, the behavior of the p-n heterojunction between n − type SiC serving as the drift layer 20 and p − type polysilicon will be explained in detail. In each energy band diagram of FIG. 2A to FIG. 2 C, the energy band of the p type silicon is shown in the left, and the energy band diagram of the n − type SiC corresponding to the drift layer 20 is shown on the right side. In this explanation, in order that the behavior of the p-n heterojunction can be easily understood, an ideal energy band diagram is illustrated, in which there is no interface state in the p-n heterojunction interface.
[0063] The tunnel-injection device shown in FIG. 1 contains the junction interface between the p − type silicon and the n − type SiC. As shown in FIG. 2 , there is an energy barrier ΔEc ascribable to the difference of electron affinity of both silicon and SiC in the junction interface. The device operates under a bias condition such that the source electrode 80 is grounded and a positive voltage is applied to the drain electrode 90 . A characteristic of the element manifests a reverse bias characteristic of a p-n heterojunction diode, implemented by the p − type lightly doped polysilicon film 60 and the SiC drift layer 20 . In other words, in the drift layer 20 , a depletion layer extends depending on the drain voltage. On the other hand, the electrons, which are minority carriers, accumulate in the junction interface in the p − type lightly doped polysilicon film 60 , because the electrons do not have energy to surmount the energy barrier ΔEc, as shown in FIG. 2B . And electric field lines establishing the depletion layer extending in the drift layer 20 terminate at the accumulation layer of electrons, and the electric field is shielded in the p − type lightly doped polysilicon film 60 . Accordingly, the p − type lightly doped polysilicon film 60 does not cause the breakdown first, but current suddenly flows from the drain electrode 90 to the source electrode 80 when the drain voltage increases to a predetermined voltage. In addition, in a reverse bias characteristic of the p-n heterojunction diode, which has been explained above, even if the thickness of the p − type lightly doped polysilicon film 60 is thinned to around 20 nm, for example, it is confirmed experimentally that a withstanding voltage of more than 300V can be achieved. Accordingly, in the tunnel-injection device according to the configuration of the first embodiment, even if the thickness of the narrower bandgap semiconductor region is made thin, by the effect that the electric field is shielded in the p − type lightly doped polysilicon film 60 , there is no fear that punch through might happen.
[0064] Because the channel length can be shortened to the thickness of the narrower bandgap semiconductor region, or around 20 nm, for example, the channel resistance can be made remarkably small. On the other hand, when a positive voltage is applied to the gate electrode 40 , the p − type lightly doped polysilicon film 60 develops the strong inversion condition, and the n + type channel layer is formed on the top surface. Furthermore, the electric field affects on the p-n heterojunction interface between the p − type lightly doped polysilicon film 60 and the SiC drift layer 20 , the thickness of the energy barrier ΔEc implemented by the p-n heterojunction interface is thinned by the electric field concentration, as shown in FIG. 2C . The dotted line is an energy level before application of the gate voltage, and the solid line shows the energy level after the application of the gate voltage. As a result, even if the drain voltage is below the predetermined voltage, the tunneling phenomenon occurs, and current begins to flow. In other words, in the tunnel-injection device according to the first embodiment, under a bias condition that the drain voltage is kept below the breakdown voltage, by applying a positive voltage to the gate electrode 40 , the current flowing between the drain electrode 90 and the source electrode 80 is controlled.
[0065] In this tunnel-injection device, a switching device manifesting high-speed and high breakdown voltage is implemented by a simple configuration, using a p-n heterojunction composed of SiC and a narrower bandgap semiconductor than SiC. Because crystallographic defect levels are low in the junction interface of the narrower bandgap semiconductor region and the gate insulation film 30 , in which a channel is formed, carriers can be transported through the channel without being influenced by the interface states. Furthermore, because there is no fear of the occurrence of the punch through, even if the thickness of the narrower bandgap semiconductor region serving as the channel is reduced, the channel length can be shortened to 20 nm. Here, “the channel length” is defined as the length of the second conductivity type narrower bandgap semiconductor region, measured from the drift layer 20 to the first conductivity type narrower bandgap semiconductor region. Therefore, the channel resistance can be reduced remarkably. Furthermore, the impurity doping by the ion implantation of high energy is not required in manufacturing of the basic configuration of the tunnel-injection device. As a result, impurity-activation-annealing to be executed at temperature of more than 1500 degrees Celsius, which also serves as the recovery process of the crystallographic quality is unnecessary. The load of a fabrication-process can be reduced, in addition to the technical advantage that the deterioration of the surface morphology occurring in the high temperature anneal can be avoided.
[0066] In the device shown in Japanese Patent Laid-Open-no. 10-233503, because it is necessary to form a deep diffusion region in order to form the p type body region in the n type SiC drift layer, the impurity doping by the ion implantation of high energy is indispensable. When a high-energy ion implantation is executed, defects are generated in the SiC drift layer, which will cause the increase of leakage current. In addition, for impurities activation, serving as the recovery process of crystallographic quality, a high temperature anneal at temperature of more than 1500 degrees Celsius, for example, is necessary, which cause a problem in that the surface morphology becomes poor after the high temperature anneal. With the first embodiment of the present invention, the problem in the device shown in Japanese Patent Laid-Open-no. 10-233503 can be easily solved so that a voltage drive type, normally-off tunnel-injection device can be manufactured by a simple fabrication-process.
[0067] 1.3 Manufacturing Method of Tunnel-Injection Device of First Embodiment:
[0068] Next, an example of a manufacturing method of the tunnel-injection device of the first embodiment is explained by means of sectional views of FIG. 3A to FIG. 3H .
[0069] (a) At first, a base body ( 20 , 10 ) made of a first semiconductor is prepared. That is, as shown in FIG. 3 A, on a n + type SiC substrate 10 , an n − type SiC drift layer 20 having an impurity concentration of 10 14 -10 18 cm −3 , and thickness of 1-400 μm, is formed, for example. Then, by thermal oxidation, a sacrificial silicon oxide film is formed on the drift layer 20 .
[0070] (b) After removing the sacrificial silicon oxide film, a new silicon oxide film having a thickness of 0.01-10 μm is deposited by CVD method. By the photolithographic delineation of the new silicon oxide film, insulation films 70 are formed as shown in FIG. 3B . A polysilicon film 61 having a thickness of 0.1-10 μm is deposited on the insulation films 70 by reduced pressure CVD method, for example, as shown in FIG. 3C .
[0071] (c) Afterwards, desired impurities are doped into this polysilicon film 61 so as to form the p − type lightly doped polysilicon film 60 and the n + type polysilicon film 18 , respectively. As an example of this doping technology, a method when a heavily doped CVD film is deposited on top of the polysilicon film, and by annealing at temperature of 600-1000 degrees Celsius, impurities doped in the CVD film thermally diffuse into the polysilicon film may be employed. Or, boron ions ( 31 B+) may be selectively implanted through the implantation mask 52 into the polysilicon film 61 so as to form the p − type lightly doped polysilicon film 60 as shown FIG. 3D . Furthermore, phosphorous ions ( 31 P + ) may be selectively implanted through the implantation mask 53 into the polysilicon film 61 so as to form the n + type polysilicon film 18 as shown FIG. 3E . Actually, after the activation-annealing, the p − type lightly doped polysilicon film 60 and the n + type polysilicon film 18 , are formed as shown FIG. 3F . In addition, in order to improve the carrier mobility in the polysilicon film 61 , the polysilicon film 61 may be annealed so as to achieve single crystallization or to increase the grain size of the polysilicon. Furthermore, the polysilicon film 61 may be single crystallized by laser light irradiation.
[0072] (d) As shown in FIG. 3G, a gate insulation film 30 is formed, for example, by CVD method. On the gate insulation film 30 , a new polysilicon film 40 having a thickness of 0.1 to 10 μm is deposited by means of the reduced pressure CVD (RPCVD) method. Desired impurities are doped in this polysilicon film 40 afterwards. And by the photolithographic delineation of the polysilicon film, a plurality of gate electrodes 40 are cut.
[0073] (e) As shown in FIG. 3 H, source electrodes 80 are formed so as to contact with the n + type polysilicon film 18 . A metallic film is deposited as a drain electrode 90 on the back surface of the SiC substrate 10 . By annealing at a temperature of around 600-1300 degrees Celsius, for example, the source electrodes 80 and the drain electrode 90 becomes ohmic electrodes. In this way the tunnel-injection device shown in FIG. 1 is completed.
[0074] 1.4 First Modification of First Embodiment:
[0075] FIG. 4 shows a tunnel-injection device associated with a first modification of the first embodiment. The difference from the configuration shown in FIG. 1 lies in the configuration such that an n + type heavily doped SiC region 19 is sandwiched in between a portion of the p − type lightly doped polysilicon film 60 and the n − type drift layer 20 , the portion being adjacent to the gate insulation film 30 . That is, in first modification of the first embodiment, the reception layer 20 embraces the heavily doped region 19 being metallurgical contacting with the barrier-forming layer 60 and the drift layer 20 having impurity-doping level lower than the heavily doped region 19 , being in metallurgical contact with the heavily doped region 19 .
[0076] In other word, the n + type heavily doped SiC region 19 is also sandwiched in between a portion of the gate insulation film 30 and the n − type drift layer 20 . When the p − type lightly doped polysilicon film 60 contacts to the n + type SiC region so as to implement the p-n heterojunction, in addition to the effectiveness in that there are many carriers in the n + type SiC region, because the width of the depletion layer extending in the n + type SiC region narrows, the thickness of the energy barrier ΔEc shown in FIGS. 2 A- 2 C becomes thinner. As a result, because the tunneling current can-penetrate the barrier at lower gate voltage, the control of the main current by the gate voltage becomes easy. In other words, the tunnel-injection device according to the first modification of the first embodiment achieves, in addition to the technical advantage achieved by the basic configuration shown in FIG. 1, a further technical advantage such that the control performance of the main current of the tunnel-injection device by the gate voltage is improved. Although the breakdown voltage between the p − type lightly doped polysilicon film 60 and the n + type SiC region 19 is low, by a field plate effect, because the depletion layer extends into the n − type drift layer 20 from the bottom surface of the insulation films 70 , and because the electric field applied across the junction between the p − type lightly doped polysilicon film 60 and the n + type SiC region 19 is shielded by the depletion layer, the decrease of the drain breakdown voltage can be prevented.
[0077] Other structure and materials are similar to the structure and materials already explained by the basic configuration shown in FIG. 1 , and overlapping or redundant description may be omitted in the first modification of the first embodiment.
[0078] 1.5 Second Modification of First Embodiment:
[0079] FIG. 5 shows a tunnel-injection device associated with a second modification of the first embodiment. The difference from FIG. 4 lies in the configuration such that in a part of the SiC drift layer 20 just under the n + type polysilicon film 18 , p + type SiC buffering regions 22 connected to source electrodes 80 are buried. In the second modification of the first embodiment, the depletion layer can be extended from the p + type SiC buffering regions 22 into the n type drift layer 20 . The width of the depletion layer is wider than the depletion layer associated with the field-plate effect manifested by the first modification of the first embodiment. Because the electric field across the junction between the p − type lightly doped polysilicon film 60 and the n + type SiC region 19 is shield by the depletion layer, the decrease of the drain breakdown voltage can be prevented.
[0080] Further, because the electric field applied to the gate insulation film 30 is relaxed, the reliability of the gate insulation film 30 improves. As explained above, in the second modification of the first embodiment, in the surface of the first conductivity type drift layer 20 facing the gate electrode 40 through the gate insulation film 30 , the second conductivity type buffering regions 22 are formed. By the second conductivity type buffering regions 22 , the breakdown voltage of the tunnel-injection device can be prescribed by the reverse breakdown voltage of the diodes implemented by the buffering regions 22 and the drift layer 20 , the tunnel-injection device having a high breakdown voltage can be provided.
[0081] Although, the example in which the p + type SiC buffering regions 22 are connected to the source electrodes 80 is explained in the second modification of the first embodiment, the buffering regions 22 are not always required to be connected to the source electrodes 80 .
[0082] Other structure and materials are similar to the structure and materials already explained by the basic configuration shown in FIG. 1 , and overlapping or redundant description may be omitted in the second modification of the first embodiment.
[0083] 1.6 Third Modification of First Embodiment:
[0084] FIG. 6 shows a tunnel-injection device associated with a third modification of the first embodiment. The difference from FIG. 5 lies in a configuration in which dielectric films 21 are buried in the SiC drift layer 20 , at portions just under the n + type polysilicon film 18 .
[0085] By adopting the configuration of the third modification of the first embodiment, the depletion layers are extended in the n + type SiC region 19 at deeper position so that an electric field across the junction between the p − type lightly doped polysilicon film 60 and the n + type SiC region 19 can be shielded easily. As a result, a decrease of a drain breakdown voltage can be prevented effectively. In addition, the reliability of the gate insulation film 30 improves as the electric field applied to the gate insulation film 30 is relaxed.
[0086] The manufacturing method for the tunnel-injection device of the third modification of the first embodiment differs from the second modification of the first embodiment in that the impurity doping by the high-energy ion implantation is not required. As a result, activation-annealing of impurity ions at temperature of more than 1500 degrees Celsius that served as the recovery process of crystallographic quality is unnecessary, the load of the fabrication-process is reduced and the deterioration of the surface morphology occurring in the high temperature anneal can be avoided.
[0087] Other structure and materials are similar to the structure and materials already explained by the basic configuration shown in FIG. 1 , and overlapping or redundant description may be omitted in the third modification of the first embodiment.
2. Second Embodiment
[0088] 2.1 Basic Configuration of Second Embodiment:
[0089] As shown in FIG. 7 a tunnel-injection device associated with a second embodiment of the present invention encompasses a reception layer 20 having a periodic recessed structure at the top surface and a plurality of barrier-forming layers 60 , each being in metallurgical contact with the reception layer 20 at the protruding potion of the recessed structure. Similar to the first embodiment, the reception layer 20 is made of a first semiconductor and barrier-forming layer 60 is made of a second semiconductor having a bandgap narrower than the first semiconductor. Here, p − type lightly doped polysilicon film 60 serves as the barrier-forming layer because the reception layer 20 is made of SiC, for example.
[0090] As shown in FIG. 7, a plurality of gate insulating films 30 are disposed on the barrier-forming layer 60 at the peripheral edge of the gate insulating films, respectively. The gate insulating films 30 are also disposed in the periodic grooves of the recessed structure. And a plurality of gate electrodes 40 are embedded in the grooves so that each of the gate electrodes 40 can control the width of the band-edge discontinuity barrier generated at the interface between the reception layer 20 and the barrier-forming layer 60 so as to change the tunneling probability of carriers through the barrier. The gate electrodes 40 are embedded, to a depth lower than the bottom surface of the barrier-forming layer 60 , in predetermined regions of the recessed drift layer 20 . Therefore, Each of the p − type lightly doped polysilicon films 60 is sandwiched by the gate electrodes 40 through the gate insulating film 30 .
[0091] FIG. 7 shows cross-sectional views of adjacent two unit cells in the multi-channel structure. In the multi-channel structure, the embedded gate electrodes 40 and the sandwiching source electrodes 80 are mutually arranged in parallel so as to implement an interdigital topology. The gate electrodes 40 and source electrodes 80 are respectively delineated in stripe geometries in a plan view.
[0092] In the second embodiment of the present invention, a plurality of carrier-supplying regions 18 are stacked on the corresponding barrier-forming layers 60 , and supply the carriers to the barrier-forming layer 60 . Each of the carrier-supplying regions 18 is made of n + type polysilicon films. And a plurality of source electrodes 80 are stacked on the carriers to the barrier-forming layer 60 , so that the n + type polysilicon films 18 can be connected to the corresponding source electrodes 80 .
[0093] Then, a plurality of p-n heterojunctions are implemented by the p − type lightly doped polysilicon films 60 and the SiC drift layer 20 , respectively. Each of the p-n heterojunctions generates the energy barrier ΔEc at the junction interface as shown in the energy band diagram of FIG. 2A .
[0094] Other structure and materials are similar to the structure and materials already explained in the first embodiment, and overlapping or redundant description may be omitted in the second embodiment.
[0095] In addition to the technical advantage as stated in the first embodiment, the area efficiency of the tunnel-injection device is raised by the recessed-gate structure, and the reduction of the on-state resistance and the miniaturization of the tunnel-injection device are possible. Because the second conductivity type narrower bandgap semiconductor region 60 and the first conductivity type narrower bandgap semiconductor region 18 can be laminated, it is easy to make the second conductivity type narrower bandgap semiconductor region 60 thinner so as to implement a structure being effective in shortening the channel length. Furthermore, by a topology in which the gate insulation film 30 is formed perpendicular to the p-n heterojunction interface, the length of the electric field lines from the gate electrode 40 to the p-n heterojunction interface can be shortened. Therefore, the control of thickness of the energy barrier ΔEc by the electric field from the gate electrode 40 can be further improved. As a result, tunneling current penetrating the barrier can be injected at lower gate voltage, and control of the main current by the gate voltage becomes easy.
[0096] 2.2 Operation of Tunnel-Injection Device of Second Embodiment:
[0097] The operation of this tunnel-injection device is basically similar to the first embodiment shown in FIG. 1 . In other words, the tunnel-injection device operates under a bias condition such that the source electrodes 80 are grounded and a positive voltage is applied to the drain electrode 90 . And when the gate electrodes 40 are grounded, the characteristic of the tunnel-injection device becomes a reverse bias characteristic of the p-n heterojunction diode implemented by the p − type lightly doped polysilicon film 60 and the SiC drift layer 20 . On the other hand, when a positive voltage is applied to the gate electrodes 40 , the p − type lightly doped polysilicon films 60 develop a strong inversion condition, and n + type layers are formed in the top surfaces of the p − type lightly doped polysilicon films 60 .
[0098] Furthermore, as the electric field acts on the p-n heterojunction interface between the p − type lightly doped polysilicon films 60 and the SiC drift layer 20 , the thickness of the energy barrier A Ec implemented by the p-n heterojunction interface is thinned by the electric field concentration. As a result, even if the drain voltage is less than the predetermined voltage, the tunneling process occurs so that current begins to flow.
[0099] There are two structural differences between the first embodiment shown in FIG. 1 and the second embodiment shown in FIG. 7 . Firstly, the p − type lightly doped polysilicon films 60 and the n + type polysilicon films 18 are laminated. Secondly, grooves penetrating through the p − type lightly doped polysilicon films 60 and the n + type polysilicon films 18 in the depth direction are facilitated so that the recessed-gate structure implemented by the gate electrodes 40 in the groove can be established. By the application of the recessed-gate structure explained in the second embodiment, the area efficiency of the tunnel-injection device is raised, and the reduction of the on-state resistance and the miniaturization of the tunnel-injection device are possible.
[0100] In addition, because the p − type lightly doped polysilicon films 60 and the n + type polysilicon films 18 can be laminated, it is easy to make the thickness of the p − type lightly doped polysilicon films 60 thin so as to implement the structure effective in shortening the channel length. Furthermore, by the topology in which the gate insulation film 30 is perpendicular to the p-n heterojunction interface direction, the length of the electric field lines from the gate electrodes 40 to the p-n heterojunction interface can be shortened. Therefore, the control performance of the thickness of the energy barrier ΔEc by the electric field from the gate electrodes 40 can be further improved. As a result, current tunneling through the barrier can be injected at lower gate voltage, and the control of the main current by the gate voltage becomes easy.
[0101] 2.3 Manufacturing Method of Tunnel-Injection Device of Second Embodiment:
[0102] Next, an example of the manufacturing method of the tunnel-injection device of the second embodiment will be explained with sectional views of FIG. 8A to FIG. 8E .
[0103] (a) At first, as shown in FIG. 8 A, on an n + type SiC substrate 10 , an n − type SiC drift layer 20 having an impurity concentration of, for example, 10 14 -10 18 cm −3 , a thickness of 1-100 μm is formed.
[0104] (b) By thermal oxidation, a sacrificial silicon oxide film is formed on the drift layer 20 . After removing the sacrificial silicon oxide film, a polysilicon film having a thickness of 0.1-10 μm, for example is deposited by means of a RPCVD method, and desired impurities are doped in this polysilicon film, so as to produce the p − type lightly doped polysilicon films 60 as shown in FIG. 8B .
[0105] (c) Next, by the RPCVD method, another polysilicon film 18 having a thickness of 0.1-10 μm, for example, is laminated on the p − type lightly doped polysilicon films 60 . By impurity doping in the polysilicon film, the n + type polysilicon film 18 is formed as shown in FIG. 8B . As a method for doping desired impurities in the polysilicon film, a heavily doped CVD film is deposited on the top of the polysilicon film so that the impurities in the CVD film are thermally diffused into the polysilicon film by an anneal of around 600-1000 degrees Celsius. Or, by ion implantation, the polysilicon film can be doped directly with impurities. In order to improve carrier mobility in the polysilicon film, an annealing of the polysilicon film may be executed, for example, so that the single crystallization can be achieved or so that the grain size of polysilicon can be enlarged. Furthermore, by irradiating laser light on the polysilicon film, the crystallization can be facilitated.
[0106] (d) As shown in FIG. 8C, a plurality of grooves 120 j−1 , 120 j , 120 j+1 , . . . each having depth of 0.1-10 μm are formed along the depth direction, for example, penetrating the n + type polysilicon film 18 and the p − type lightly doped polysilicon films 60 until the n − type drift layer 20 is reached.
[0107] (e) As shown in FIG. 8D, a gate insulation film 30 is formed by, for example, CVD method, and on the gate insulation film 30 , a new polysilicon film 40 having a thickness of, for example, 0.1-10 micrometer, is deposited by means of the RPCVD method.
[0108] (f) Desired impurities are doped in this polysilicon film 40 afterwards. By the photolithographic delineation of this polysilicon film, a plurality of gate electrodes 40 are formed in the grooves 120 j−1 , 120 j , 120 j+1 , . . . .
[0109] (g) As shown in FIG. 8 E, source electrodes 80 are formed so as to contact with the n + type polysilicon films 18 . A metallic film is deposited as a drain electrode 90 on the back surface of a SiC substrate 10 . By annealing at temperature of around 600-1300 degrees Celsius, for example, ohmic electrodes serving as the source electrodes 80 and the drain electrode 90 are established. In this way the tunnel-injection device shown in FIG. 7 is completed.
[0110] 2.4 First Modification of Second Embodiment:
[0111] FIG. 9 shows a tunnel-injection device associated with a first modification of the second embodiment. The difference from FIG. 7 lies in a configuration, in which a plurality of n + type SiC regions 19 are formed in parts of the SiC drift layer 20 just under the p − type lightly doped polysilicon films 60 . That is, in first modification of the second embodiment, the recessed reception layer 20 embraces the heavily doped region 19 being metallurgical contacting with the barrier-forming layer 60 .
[0112] By the structure that the drift layer 20 having impurity-doping level lower than the heavily doped region 19 , is in metallurgical contact with the heavily doped region 19 so that the n + type SiC regions l 9 can implement the p-n heterojunctions with the p − type lightly doped polysilicon films 60 , in addition to the behavior whereby a large number of carriers exist in the n + type SiC regions 19 , because the width of the depletion layer extending in the n + type SiC regions 19 is reduced, the thickness of the energy barrier ΔEc is made thinner. As a result, since the tunneling current can-penetrate the barrier at lower gate voltage, the control of the main current by the gate voltage becomes easy. In other words, by the tunnel-injection device of the first modification of the second embodiment, in addition to the technical advantage as explained in the basic configuration of the second embodiment, a technical advantage such that the control performance of main current of the tunnel-injection device by the gate voltage improves is achieved.
[0113] Although the breakdown voltage of the p − type lightly doped polysilicon films 60 and the n + type SiC regions 19 is low, because depletion layers extend from portions just under the gate insulation film 30 into the n − type drift layer 20 by the field-plate effect, the electric field across the junction between the p − type lightly doped polysilicon films 60 and the n + type SiC region 19 is shielded, and the decrease of the drain breakdown voltage can be prevented.
[0114] Other structure and materials are similar to the structure and materials already explained by the basic configuration shown in FIG. 7 , and overlapping or redundant description may be omitted in the first modification of the second embodiment.
[0115] 2.5 Second Modification of Second Embodiment:
[0116] FIG. 10 shows a tunnel-injection device associated with a second modification of the second embodiment. The difference from FIG. 9 lies in a configuration such that in parts of the SiC drift layer 20 just under the gate insulation film 30 disposed at the bottom of the groove, a plurality of p + type SiC buffering regions 22 are buried. In the second modification of the second embodiment, in comparison with the electric field shield effect by the field-plate effect explained in the first modification of the second embodiment, depletion layers can be extended respectively from the p + type SiC buffering regions 22 into the n − type drift layer 20 even further. Because the electric field across the junction between the p − type lightly doped polysilicon films 60 and the n + type SiC regions 19 is shielded, the decrease of the drain breakdown voltage can be prevented. In addition, because the electric field applied to the gate insulation film 30 disposed at the bottom of the groove is relaxed, the reliability of the gate insulation film 30 improves.
[0117] In addition, in the second modification of the second embodiment, the p + type SiC buffering regions 22 can be connected to the source electrodes 80 in the depth direction of the paper that is not illustrated.
[0118] Other structure and materials are similar to the structure and materials already explained by the basic configuration shown in FIG. 7 , and overlapping or redundant description may be omitted in the second modification of the second embodiment.
3. Third Embodiment
[0119] 3.1 Basic Configuration of Third Embodiment:
[0120] As shown in FIG. 11, a tunnel-injection device associated with a third embodiment of present invention encompasses a reception layer 20 and a barrier-forming layer 60 buried in the reception layer 20 at the top surface of the reception layer 20 . Similar to the first and second embodiments, reception layer 20 is made of a first semiconductor, and the barrier-forming layer 60 is a second semiconductor having a bandgap narrower than the first semiconductor. Each of the buried barrier-forming layer 60 is metallurgical contact with the reception layer 20
[0121] Further as shown in FIG. 11, a plurality of carrier-supplying regions 18 buried in corresponding barrier-forming layers 60 so that each of the carrier-supplying regions 18 can contact with the barrier-forming layer 60 , and they supply the carriers to the corresponding barrier-forming layer 60 . And a gate insulating film 30 is disposed on the barrier-forming layer 60 . The gate insulating film 30 extends over the carrier-supplying regions 18 . A gate electrode 40 is disposed on the gate insulating film 30 . Both of the peripheral edges of the gate electrode 40 lies above the portion of the barrier-forming layer 60 sandwiched by the reception layer 20 and the carrier-supplying region 18 so that the gate electrode 40 can control the width of the band-edge discontinuity barrier generated at the interface between the reception layer 20 and the barrier-forming layer 60 . Then the gate electrode 40 can change the tunneling probability of carriers through the band-edge discontinuity barrier.
[0122] In the third embodiment of present invention, since the reception layer 20 is made of n − type SiC, the barrier-forming layer 60 buried in the reception layer 20 is made of p-type lightly doped polysilicon films. The n − type SiC reception layer may be assigned as an n − type drift layer 20 . Therefore, the buried p − type lightly doped polysilicon films 60 and the n − type SiC drift layer 20 can implement the p-n heterojunction, and there is an energy barrier ΔEc in the junction interface as shown in the energy band diagram of FIG. 2A . As the carrier-supplying region 18 , n + type polysilicon film is employed, so that the n + type polysilicon films 18 can be buried in the p − type lightly doped polysilicon film 60 . On the carrier-supplying regions 18 , or on the n + type polysilicon films 18 , corresponding source electrodes 80 are disposed respectively. FIG. 11 shows cross-sectional views of adjacent two unit cells in the multi-channel structure. In the multi-channel structure, the gate electrodes 40 and the source electrodes 80 are mutually arranged in parallel so as to implement an interdigital topology. The gate electrodes 40 and source electrodes 80 can be respectively delineated in stripe geometries in a plan view. A drain electrode 90 is formed on a back surface of the n + type SiC substrate 10 .
[0123] Other structure and materials are similar to the structure and materials already explained by first and second embodiments, and overlapping or redundant description may be omitted in the third embodiment. However, in addition to the technical advantage as explained in the first and second embodiments, because the electric field applied to the gate insulation film 30 is relaxed by the narrower bandgap semiconductor region 60 in the groove, the reliability of the gate insulation film 30 improves. In addition, by the topology in which the gate insulation film 30 is perpendicular to the p-n heterojunction interface, the length of the electric field lines from the gate electrodes 40 to the p-n heterojunction interface can be shortened. Therefore, the control performance of thickness of the energy barrier ΔEc by the electric field applied from the gate electrodes 40 can be improved even further. As a result, tunneling current penetrating the barrier can be injected at lower gate voltage so that the control of the main current by the gate voltage becomes easy.
[0124] 3.2 Operation of Tunnel-Injection Device of Third Embodiment:
[0125] The operation of this tunnel-injection device is basically similar to the tunnel-injection device explained in the first embodiment shown in FIG. 1 . In other words, the tunnel-injection device operates under a bias condition such that the source electrodes 80 are grounded, and a positive voltage is applied to the drain electrode 90 . And, under a bias condition, when the gate electrode 40 is grounded, the behavior of the tunnel-injection device becomes the reverse bias characteristic of the p-n heterojunction diode implemented by the p − type lightly doped polysilicon films 60 and the SiC drift layer 20 . On the other hand, when a positive voltage is applied to the gate electrode 40 , the p − type lightly doped polysilicon films 60 develop a strong inversion condition so that the n + type layer is formed in the top surface of the p − type lightly doped polysilicon films 60 . Furthermore, because the electric field ascribable to the gate voltage acts on the p-n heterojunction interface between the p − type lightly doped polysilicon films 60 and the SiC drift layer 20 , the thickness of the energy barrier ΔEc implemented by the p-n heterojunction interface is thinned by the electric field concentration. As a result, even if the drain voltage is less than a predetermined voltage, the tunneling process occurs so that current begins to flow.
[0126] Structural difference of the third embodiment shown in FIG. 11 from the first embodiment shown in FIG. 1 lies in that the p − type lightly doped polysilicon films 60 are buried at the top surface of drift layer 20 . By the application of the device structure explained in the third embodiment, since the narrower bandgap semiconductor regions 60 buried at the top surface of drift layer 20 relax the electric field applied to the gate insulation film 30 , the reliability of the gate insulation film 30 improves. In addition, by making the gate insulation film 30 perpendicular to the p-n heterojunction interface direction, the length of the electric field lines from the gate electrodes 40 to the p-n heterojunction interface can be shortened. Therefore, the control performance of thickness of the energy barrier ΔEc by the electric field applied from the gate electrodes 40 can be further improved. As a result, the tunneling current flowing through the barrier can be injected at lower gate voltage so that the control of the main current by the gate voltage becomes easy.
[0127] Other structure and materials are similar to the structure and materials already explained in the first embodiment, and overlapping or redundant description may be omitted in the third embodiment.
[0128] 3.3 Manufacturing Method of Tunnel-Injection Device of Third Embodiment:
[0129] Next, an example of the manufacturing method for the tunnel-injection device of the third embodiment will be explained by means of sectional views of FIG. 12A to FIG. 12H .
[0130] (a) At first, as shown in FIG. 12 A, on the n + type SiC substrate 10 , an n − type SiC drift layer 20 having an impurity concentration of, for example, 10 14 -10 18 cm −3 , and a thickness of 1-10 μm is formed.
[0131] (b) As shown in FIG. 12B, a plurality of grooves 120 j−1 , 120 j , . . . each having a depth of a 0.1-10 micrometer, for example, are dug. And, a thermal oxidation is executed so as to form a sacrificial silicon oxide film on the drift layer 20 .
[0132] (c) After removing the sacrificial silicon oxide film, a polysilicon film having a thickness of, for example, 0.1-10 micrometer is deposited by means of RPCVD method. Then, desired impurities are doped in this polysilicon film so as to implement a p − type lightly doped polysilicon films 60 as shown in FIG. 12C . On the top of the polysilicon film, a heavily doped CVD film is deposited so that, by an annealing of around 600-1000 degrees Celsius, impurities in the CVD film thermally diffused in the polysilicon film. Or, impurities may be doped directly by ion implantation. In addition, in order to improve the carrier mobility in the polysilicon film, by annealing of the polysilicon film, for example, the single crystallization can be achieved, or the grain size of polysilicon may be enlarged. Furthermore, the polysilicon film may be single crystallized by irradiation of laser light.
[0133] (d) Next, by the chemical mechanical polish (CMP) method, the top surface of the polysilicon film is planarized so as to leave the polysilicon films in the grooves respectively as shown in FIG. 12D .
[0134] (e) Next, in predetermined regions of the p − type lightly doped polysilicon films 60 , phosphorous ions ( 31 P + ) may be selectively implanted through the implantation mask 54 as shown in FIG. 12E .
[0135] (f) Actually, after the activation-annealing, as shown in FIG. 12 G, the n + type polysilicon films 18 are formed in the p − type lightly doped polysilicon films 60 at a predetermined depth. Then, a gate insulation film 30 is formed by CVD method. On the gate insulation film 30 , a new polysilicon film having a thickness of, for example, 0.1-10 micrometer degree is deposited by means of the RPCVD method. Desired impurities are doped in the new polysilicon film afterwards. By the photolithographic delineation of the polysilicon film, the gate electrodes 40 are formed.
[0136] (g) As shown in FIG. 12H, a plurality of source electrodes 80 are formed so as to contact with the n + type polysilicon films 18 , respectively. A metallic film is deposited as a drain electrode 90 on the back surface of the SiC substrate 10 . By annealing at a temperature of around 600-1300 degrees Celsius, for example, the source electrodes 80 and the drain electrode 90 become ohmic electrodes respectively. In this way the tunnel-injection device shown in FIG. 11 is completed.
[0137] 3.4 Modification of Third Embodiment:
[0138] FIG. 13 shows a tunnel-injection device associated with the modification of the third embodiment. The difference from the basic configuration shown in FIG. 11 lies in a configuration such that in a part of the SiC drift layer 20 just under the gate insulation film 30 , an n + type heavily doped SiC region 19 is disposed.
[0139] When the n + type SiC region 19 implements the p-n heterojunction with the p − type polysilicon, in addition to the behavior that a large number of carriers are formed in the n + type SiC region 19 , because the width of the depletion layer extending in the n + type SiC region 19 becomes small, the thickness of the energy barrier ΔEc is formed thinner. As a result, since tunneling current through the barrier can be injected at lower gate voltage, the control of the main current by the gate voltage becomes easy. In other words, by the tunnel-injection device of the modification of the third embodiment, in addition to the technical advantage as explained in the third embodiment, a technical advantage in which the control performance of the main current of the tunnel-injection device by the gate voltage improves is achieved. Then, although the breakdown voltage of the junction between the p-type lightly doped polysilicon films 60 and the n + type SiC region 19 is low, the depletion layers extend into the n − type drift layer 20 from the junction interfaces between the p − type lightly doped polysilicon films 60 and the n type drift layer 20 . Therefore, since the electric field across the junction between the p − type lightly doped polysilicon films 60 and the n + type SiC region 19 is shielded, the decrease of the drain breakdown voltage can be prevented.
[0140] Other structure and materials are similar to the structure and materials already explained by the basic configuration shown in FIG. 11 , and overlapping or redundant description may be omitted in the modification of the third embodiment.
4. Fourth Embodiment
[0141] 4.1 Basic Configuration of Fourth Embodiment:
[0142] FIG. 14 shows a tunnel-injection device associated with a fourth embodiment of the present invention. FIG. 14 shows cross-sectional views of adjacent two unit cells in the multi-channel structure. In the multi-channel structure, a plurality of gate electrodes 40 and a plurality of source electrodes 80 are mutually arranged in parallel so as to implement an interdigital topology. The gate electrodes 40 and source electrodes 80 are respectively delineated in stripe geometries.
[0143] As the SiC which implements the n + type SiC substrate 10 region, for example, 4H polytype can be used among α-SiC. The drift layer 20 on the n + type SiC substrate 10 may be formed by epitaxial growth method. The source region 13 is made by an n type polysilicon. Therefore, metallurgical junction between the drift layer 20 and the source region 13 implements the n-n heterojunction. The n-n heterojunction embraces SiC and polysilicon, the bandgap of SiC differs from the polysilicon. The bandgap of the source region 13 is set to be smaller than the drift layer 20 . In the interface of the n-n heterojunction, there is an energy barrier ΔEc as shown in FIGS. 15 A- 15 C.
[0144] For example, after thermally oxidizing the top surface of the source region 13 so as to form a thermal oxidation film, the thermal oxidation film is selectively etched to leave a predetermined region so as to form the gate insulation film 30 . For example, the gate electrode 40 on the gate insulation film 30 is made of same materials as the source electrodes 80 . The gate electrode 40 is defined by the same process stage of the source electrodes 80 through the photolithographic delineation, being separated from the source electrodes 80 .
[0145] 4.2 Operation of Tunnel-Injection Device of Fourth Embodiment:
[0146] Next, the operation of the tunnel-injection device is explained. In the fourth embodiment, the tunnel-injection device operates under a bias condition such that the source electrodes 80 are grounded, and a positive potential is applied to the drain electrode 90 . When the gate electrode 40 is applied with the ground potential, the current blocking state is maintained, because in the n-n heterojunction interface between the source region 13 and the drift layer 20 , an energy barrier ΔEc against the conduction electrons is formed.
[0147] By means of energy band diagram shown in FIG. 15A to FIG. 15 C, the behavior of the n-n heterojunction between n − type SiC serving as the drift layer 20 and n − type polysilicon serving as the source region 13 will be explained in detail. In each energy band diagram of FIG. 15A to FIG. 15 C, the energy band of the n − type silicon corresponding to the source region 13 is shown in the left, and the energy band diagram of the n − type SiC corresponding to the drift layer 20 is shown in the right side. Although in the tunnel-injection device structure described above, the source region 13 was explained as made of polysilicon, in FIG. 15A to FIG. 15 C, the energy band diagram of silicon is employed. In this explanation, in order that the behavior of the n-n heterojunction can be easily understood, it illustrates an ideal energy band diagram, in which there is no interface state in the n-n heterojunction interface.
[0148] In the junction interface between silicon and SiC, there is an energy barrier ΔEc ascribable to the difference of electron affinity of both silicon and SiC.
[0149] Regarding the tunnel-injection device related to the fourth embodiment shown in FIG. 14 , the energy band diagram of the junction interface between the source region 13 just under the gate electrode 40 and the drift layer 20 is illustrated in FIG. 15A to FIG. 15C . The energy band diagram is taken on line A in FIG. 14 . FIG. 15A is the energy band diagram in so-called thermal equilibrium state, in which none of the gate electrode 40 , the source electrodes 80 and the drain electrode 90 are biased. FIG. 15B corresponds to a bias condition in which the gate electrode 40 and the source electrodes 80 are both grounded, but a predetermined positive potential is applied to the drain electrode 90 . As shown in FIG. 15B, a depletion layer broadens in the drift layer 20 of the n-n heterojunction interface, depending on the applied drain-potential. Because conduction electrons in the source region 13 cannot surmount the energy barrier ΔEc, conduction electrons accumulate in the junction interface. Therefore, electric field lines establishing the depletion layer extending in the SiC side terminate in the junction interface. The drain electric field is shielded in the source region 13 . Then, even if the polysilicon implementing the source region 13 has very thin geometry, or the thickness is around 20 nm, for example, it is possible to maintain the current blocking state so as to establish a predetermined breakdown voltage.
[0150] Next, so as to transit from the current blocking state to conducting state, as positive potential is applied to the gate electrode 40 , under the condition that the polysilicon film serving as the source region 13 is made thin, the gate electric field extends through the gate insulation film 30 to the n-n heterojuncti
