DETAILED DESCRIPTION OF THE INVENTION

[0024] The present invention will be understood from the exemplary embodiments described herein.

[0025] The present invention provides a field shield integration configuration that offers simultaneously enhanced recombination centers for positive-charge carriers (holes) and negative-charge carriers (electrons), and an effective drift field for holes (not required for electrons due to their inherent high mobility). The effective drift field and the enhanced recombination centers facilitate the rapid recombination of the charge carriers, leading to a very small recombination time constant. The present invention, therefore, overcomes the conventional slow thermal recombination mechanism or the diffusion time constant associated with hole recombination at the body contact.

[0026] FIG. 2 is a partial cross-sectional view of a structure 100 constructed in accordance with one embodiment of the present invention. Structure 100 can be, for example, a structure such as a semiconductor wafer. Structure 100 comprises a silicon substrate 150 ; an oxide insulation layer 140 disposed above the silicon substrate 150 ; a silicon body layer 130 disposed above the oxide insulation layer 140 ; and a field shield gate 110 disposed above a portion of the silicon body layer 130 . The field shield gate 110 includes a conductor portion 115 , and an alumina insulation layer 120 disposed beneath the conductor portion 115 . Structure 100 also includes body contact 170 . The silicon body layer 130 includes at least one channel stop region 131 and at least one recombination center 132 for the recombination of positive- and negative-charge carriers. The at least one channel stop region 131 and the at least one recombination center 132 are laterally located beneath the field shield gate 110 . The conductor portion 115 of field shield gate 110 comprises a material that functions electrically like a metal because it is heavily doped, i.e., a degenerate semiconductor. The conductor portion 115 comprises a material that is capable of being accommodated by the process of fabricating the structure 100 . Thus, for purposes of process integration, the conductor portion 115 is typically polysilicon. The silicon body layer 130 may comprise either p- or n-conductivity type silicon.

[0027] In an active device region 160 , the oxide insulation layer 140 includes a channel stop region 141 and a recombination center 142 for the recombination of positive- and negative-charge carriers. Since the channel stop region 141 and the recombination center 142 are both embedded inside the oxide insulation layer 140 in the active device region 160 , they do not affect the device profiles, and consequently device characteristics. The channel stop region 141 and the recombination center 142 can also be present in the oxide insulation layer 140 beneath body contact 170 .

[0028] The method of fabricating structure 100 comprises providing the oxide insulation layer 140 on the silicon substrate 150 ; providing on the oxide insulation layer 140 a shallow trench isolation configuration of the silicon body layer 130 ; providing on a portion of the silicon body layer 130 the alumina insulation layer 120 of the field shield gate 110 ; providing on the alumina insulation layer 120 the conductor portion 115 of the field shield gate 110 ; and providing, through ion implantation, the channel stop regions 131 and 141 and the recombination centers 132 and 142 in each of the silicon body layer 130 and the oxide insulation layer 140 .

[0029] The presence of the channel stop region 141 and the recombination center 142 is a consequence of the formation of the channel stop region 131 and the recombination center 132 . The channel stop region 141 and the recombination center 142 have no electrical consequence, however, since channel stop region 141 and recombination center 142 are embedded in the buried oxide layer 140 . After the ion implantation step, the method of fabrication further comprises standard device processing, such as, for example, active NFET and PFET device processing, body contact and other contact processing, and interconnect and back-end-of-line processing, as is well known in the art.

[0030] In the present invention, two factors determine the ability of the holes to recombine with a small recombination time constant. The first factor is the presence of an effective drift field, and the second factor is the presence of the enhanced recombination center 132 . The first factor, an effective drift field, is realized through use of the field shield gate 110 , which unlike a standard gate oxide, includes a layer 120 of alumina (Al ₂ O ₃ ) insulation. The alumina insulation layer 120 , which may be deposited by chemical vapor deposition (CVD) or atomic layer deposition (ALD), is deposited over the native hydrated oxide surface of the silicon body layer 130 (in a pre-gate insulator standard clean process). By conducting the oxidation in a moist environment, a highly controlled negative interface charge of approximately 3E ¹³ /cm ² can be achieved at an alumina insulation layer 120 -silicon body layer 130 interface 121 . It is this negative interface charge which provides the effective drift field. As used herein, the term “moist” means an environment in which the partial pressure of the hydroxyl ion during oxidation is at least one millitorr.

[0031] The second factor, the presence of the enhanced recombination center 132 , is based on the following. As depicted in FIG. 1 (from Physics of Semiconductor Devices, S. M. Sze, John Wiley & Sons, New York, 1981, p. 21), different ionization energy levels can be achieved by implanting different impurities in silicon. Species such as silicon (Si), nickel (Ni), and cobalt (Co) create a deep level of energy states, and therefore, deep-trap levels within the bandgap of silicon. Therefore, implanting any of silicon (i.e., intrinsic silicon), nickel, and cobalt within the body of p-type or n-type silicon will create a deep recombination center to facilitate the recombination of positive- and negative-charge carriers.

[0032] The presence of the enhanced deep recombination center 132 is achieved as follows. The deep recombination center 132 is produced in the silicon body layer 130 , below the field shield gate 110 , near the silicon body layer 130 -oxide insulation layer 140 interface 133 . The deep recombination center 132 is produced by ion implanting one of Si, Ni, or Co at an appropriate dose, typically about 1E ¹⁵ /cm ² , i.e., at an implantation energy sufficient to provide the desired depth of implantation. These species (Si, Ni, and Co), when implanted into silicon, provide both hole and electron recombination centers by generating deep states inside the silicon band gap. As used herein in conjunction with recombination center 132 , the term “near” means the following. Producing the deep recombination center 132 in the silicon body layer 130 near the silicon body layer 130 -oxide insulation layer 140 interface 133 means producing the deep recombination center 132 in the approximately lower one-third portion of the silicon body layer 130 (i.e., one-third the distance from interface 133 to interface 121 ). For example, in a silicon body layer 130 having a thickness of 1000 Å, the deep recombination center 132 would be located in the approximately lower 300 Å of the silicon body layer 130 nearest the interface 133 .

[0033] The ion implantation to produce the recombination center 132 is performed through the field shield gate 110 , and is performed concurrently with the implantation of the self-aligned channel stop region 131 . The channel stop implantation employs a p-type impurity, such as, for example, boron or other p-type impurities, for a p-type silicon body layer 130 . The channel stop implantation employs an n-type impurity, such as, for example, phosphorous or other n-type impurities, for an n-type silicon body layer 130 . As shown in FIG. 2 , the channel stop region 131 implantation is located near the alumina insulation layer 120 -silicon body layer 130 interface 121 (i.e., the peak or maximum concentration point of the implantation is located near the alumina insulation layer 120 -silicon body layer 130 interface 121 ). The purpose of the channel stop region 131 implantation is to adjust the equivalent threshold of the field shield gate 110 . As used herein in conjunction with channel stop region 131 , the term “near” means the following. Producing the channel stop region 131 in the silicon body layer 130 near the alumina insulation layer 120 -silicon body layer 130 interface 121 means producing the channel stop region 131 in the approximately upper one-tenth portion of the silicon body layer 130 (i.e., one-tenth the distance from interface 121 to interface 133 ). The implantation energy that is employed to provide the channel stop region 131 implantation is that which is sufficient to provide the desired depth of implantation.

[0034] The recombination center 132 implantation is located near the silicon body layer 130 -oxide insulation layer 140 interface 133 . The purpose of the recombination center 132 implantation is to create deep recombination regions for electrons and holes.

[0035] The ability of the charge carriers to recombine with a small recombination time constant is attributable to the interaction between the negative interface charge at the alumina insulation layer 120 -silicon body layer 130 interface 121 , and the deep recombination center 132 . The drift field generated by the negative charges near the interface 121 attracts holes, which are then recombined at the recombination center 132 . (See FIG. 3 .)

[0036] As indicated above, in the active device region 160 and beneath the body contact 170 , the oxide insulation layer 140 includes the channel stop region 141 and the recombination center 142 for the recombination of positive- and negative-charge carriers. The presence of the channel stop region 141 and the recombination center 142 is a consequence of the formation of the channel stop region 131 and the recombination center 132 . The channel stop region 141 and the recombination center 142 have no electrical consequence, however, and thus do not affect the device profiles, since channel stop region 141 and recombination center 142 are embedded in the buried oxide layer 140 .

[0037] FIG. 3 is a partial cross-sectional view of an SOI-NFET active device embodiment 200 of the structure 100 depicted in FIG. 2 . In addition to the features depicted in FIG. 2 , active device 200 includes an NFET active layer 210 of n+polysilicon and active device gate 215 . As indicated above, the drift field generated by the negative charges near the interface 121 attracts holes, such as those schematically depicted beneath the active device gate 215 , which are then recombined at the recombination center 132 .

[0038] FIG. 4 is a plan view of the layout of an SOI-NMOSFET active device embodiment 300 of the structure depicted in FIG. 2 . FIG. 5 is a partial cross-sectional view through the channel of the layout depicted in FIG. 4 . In addition to the features depicted in FIG. 2 , active device 300 , which provides shallow trench isolation, includes active gate 310 ; active gate contact 311 ; n+source 320 ; source contact 340 ; n+drain 330 ; drain contact 350 , and body contact 131 .

[0039] FIG. 6 is a partial cross-sectional view of an SOI-CMOS active device embodiment 400 of the structure depicted in FIG. 2 . In addition to the features depicted in FIG. 2 , active device 400 , which also provides shallow trench isolation, includes a silicon body layer 410 of a second conductivity type, such as an n-type, the silicon body layer 410 having a channel stop region 411 and a recombination center 412 ; an n-body contact 420 ; an NFET active device 430 ; and a PFET active device 440 .

[0040] A chip produced from the structure 100 (or any of the above-described various embodiments thereof depicted in FIGS. 3 - 6 ) may be incorporated in any fabricated semiconductor device, including various processor system components, such as for example, a central processing unit (CPU) or in any of the various types of memory devices, such as for example, RAM, ROM, and others. It may also be used in any type of integrated circuit controller for a floppy disk, a hard disk, a ZIP, or a CD-ROM disk.

[0041] FIG. 7 is a block diagram of a system 500 utilizing a chip produced from the structure 100 . System 500 typically comprises a CPU 510 . The system 500 may be a computer system, a process control system, or any other system employing a processor and associated memory, and may employ one or more buses and/or bridges which allow the CPU 510 to internally communicate with I/O devices 520 , 530 , random access memory (RAM) devices and read-only memory (ROM) devices 540 , and peripheral devices such as a floppy disk drive 550 and a compact disk CD-ROM drive 560 that also communicate with CPU 510 over the bus 570 , as is well known in the art. Any of the CPU 510 , the memory devices, and controller elements or other illustrated electrical components may include a chip produced from the structure 100 (or any of the above-described various embodiments thereof depicted in FIGS. 3 - 6 ) in accordance with the claimed invention.

[0042] In still another embodiment of the invention, a chip produced from the structure 100 can be employed in a digital, telecommunication, and internet system, and associated device applications. The system comprises a digital processor; an analog device; a radio frequency device; and a memory device having memory such as RAM, ROM, NVRAM (non-volatile RAM), or flash. Any combination of the aforementioned devices and functions can be integrated into a chip produced using the structure 100 .

[0043] The present invention, therefore, provides a structure capable of facilitating the enhanced recombination of charge carriers, which results in a recombination time constant that is substantially smaller than that associated with conventional structures and methods. By virtue of the features described herein, the invention provides scalability, performance and circuit designability over a wide range of application frequencies and power supplies. The invention also facilitates mixed signal circuit design (e.g., phase-locked loop), and can be used for memory and logic applications.

[0044] Although the invention has been described and illustrated as being suitable for use in a processor applications, for example, computer control systems, the invention is not limited to these embodiments. Rather, the invention could be employed in any system in which a small recombination time constant is desirable.

[0045] Accordingly, the above description and accompanying drawings are only illustrative of exemplary embodiments that can achieve the features and advantages of the present invention. It is not intended that the invention be limited to the embodiments shown and described in detail herein. The invention is limited only by the scope of the following claims.