DETAILED DESCRIPTION OF THE INVENTION

[0035] FIG. 1 shows a membrane 1 , for example a polymide membrane, overlying a circuit 2 to be tuned. The circuit 2 is placed over a substrate 3 . Lateral portions 20 , 21 support the membrane 1 . The membrane 1 carries a metal film 4 , placed on the bottom portion of the membrane 1 , that acts as the tuning element. Tuning of the circuit 2 is achieved via capacitive coupling between the metal film 4 and the circuit 2 . In particular, a parallel plate capacitor is formed between the metal film 4 and the circuit 2 . Since the capacitance for a parallel plate capacitor varies inversely with the size of the gap between the upper plate and the lower plate of the capacitor, the circuit 2 can be tuned by controlling the deflection of the membrane 1 .

[0036] Deflection and control of the position of the membrane 1 is obtained through piezoelectric actuators 5 disposed on the top portion of the membrane 1 . The actuators 5 allow the membrane 1 , and correspondingly the metal film 4 , to be moved either upwards or downwards. In the preferred embodiment, each actuator 5 comprises two layers 10 , 11 . The layers 10 , 11 will bend upwards or downwards according to the sign of the voltage applied to the layers. A first embodiment of the invention provides that both layers are made of a piezoelectric material, i.e. that both layers are ‘active’ layers. A second embodiment of the invention provides that only one of the two layers is an active layer. In the second embodiment, the active layer can either be the top layer 10 or the bottom layer 11 .

[0037] It is preferable to dispose the actuators so as to avoid mass loading of the membrane. Mass loading of the membrane 1 would slow down the response time of the tuning device. FIG. 1 shows a first way of disposing the actuators 5 , namely along the width periphery of the membrane 1 . Disposition of the actuators 5 along the periphery of the membrane 1 allows a portion of the actuators 5 to be supported by the horizontal component of the lateral portions 20 , 21 .

[0038] In particular, the layers 10 , 11 of the actuators 5 are so positioned over the membrane 1 and the lateral portions 20 , 21 that a first portion of each layer 10 , 11 will lie both over the membrane 1 and the lateral portion 20 or 21 , and a second portion of each layer 10 , 11 will lie over the membrane 1 only. Upon application of a voltage, the first portion will provide the required support without mass loading the membrane, and the second portion will provide the upward/downward bending required for moving the membrane 1 .

[0039] Additionally, upon application of a voltage, the shape of the membrane 1 will remain substantially parallel to the base of the substrate 3 . In particular, the section of the membrane 1 placed above the tuning or conductive element 4 will undergo a movement parallel to the substrate, thereby forming a well-defined and substantially uniform gap between the membrane and the substrate, wherein the term ‘uniform’ is intended to mean that all regions of the conductive element 4 will be, at any time, substantially at the same distance from the circuit to be tuned. Deflection, force and response time of the tuning arrangement are a function of the dimension of the actuators 5 . Therefore, deflection, force and response time of the arrangement can be optimized through patterning of the actuators 5 .

[0040] According to the present invention, multi-layered structures having more than two actuation layers are also possible, but not preferred, given that their presence complicates the fabrication process without giving too much advantage in terms of membrane deflection.

[0041] Electrical connections to the actuators are not shown, for clarity purposes. FIG. 5 , described later, will show one example of electrically connecting the actuators.

[0042] According to the preferred embodiment of the present invention, the layers 10 and 11 are each about 20 micrometers thick, the membrane 1 is about 10 micrometers thick and the distance between the membrane 1 and circuit 2 is about 50 micrometers.

[0043] FIG. 2 shows a top plan view of the membrane 1 and the actuators 5 with reference to the embodiment of FIG. 1 , to better illustrate the preferred position of the actuators 5 with reference to the membrane 1 . The membrane 1 can be about 10 mm long and about 6 mm wide, while the actuators can be about 4 mm long and about 3 mm wide.

[0044] FIGS. 3 and 4 correspond to FIGS. 1 and 2 and show an alternative embodiment of the actuators, wherein the actuators 105 , although being positioned on a region of the membrane different from the periphery of the membrane, nevertheless allow preventing mass loading of the membrane 101 . In particular, also in this embodiment, a first portion of each actuator lies both over the membrane 101 and the lateral portion of the substrate, and a second portion of each actuator lies over the membrane only.

[0045] FIGS. 2 and 4 show actuators 5 , 105 having a substantially rectangular shape when viewed from the top. This shape, although preferred, has been shown for explanatory purposes only. Other shapes are also possible, so long as mass loading of the membrane is reduced or prevented.

[0046] FIGS. 5 ( a ) to 5 ( c ) show schematic views of a two-layered piezoelectric actuator with parallel polarization directions to be used in accordance with the present invention. The polarization directions are shown by the small arrows depicted within each layer. The actuator shown in FIGS. 5 ( a )- 5 ( c ) comprises an upper layer 10 and a lower layer 11 . Electrodes 12 , 13 , and 14 are alternated with layers 10 and 11 . Layers 10 and 11 deflect on applying voltages between the electrodes 12 , 13 and 14 . On choosing the proper polarities for the voltage, a tensile force T 1 or thrusting force T 2 can be generated in the plane of the layers 10 , 11 . The forces T 1 , T 2 will create a deflection in the middle section of the layers 10 , 11 . For a given piezoelectric material such as PZT or PLZT, the amount of deflection and force depends on the dimension of the layers, which can be adjusted to meet the requirements of the particular application.

[0047] When no voltage is applied, the actuator does not cause the membrane to be deflected, as shown in FIG. 5 ( a ). When voltage having a first polarity is applied, for example a positive polarity, the actuator causes the membrane to be deflected in a first direction, for example upwards, as shown in FIG. 5 ( b ). When voltage having a second polarity, opposite to the first polarity, is applied, for example a negative polarity, the actuator causes the membrane to be deflected in a second direction, for example downwards, as shown in FIG. 5 ( c ).

[0048] The present invention also discloses a process for combining a piezoelectric actuator, like for example the actuator 5 shown in FIGS. 1 - 5 , with a polymide membrane.

[0049] According to a first embodiment of the process, the actuator is purchased commercially and then combined with the membrane. Combination of the commercially available actuator (for example a PI Ceramic PL-122.251 actuator, about 0.5 mm thick) with the membrane can be obtained by means of a thin layer of adhesive, about 1 micron thick. The use of the thin layer of adhesive will be described in better detail with reference to FIG. 6 ( c )(1).

[0050] According to a second embodiment of the process, the actuator is made in-house and integrated with the membrane during the fabrication process. Note that the actuating assembly shown in FIGS. 1 - 4 may be fabricated by processes other than those depicted in the following figures. Further, while the following figures depict multiple separate fabrication steps, alternative fabrication processes may allow several separate steps to be combined into fewer steps. Finally, alternative fabrication processes may use a difference sequence of steps.

[0051] FIGS. 6 ( a )- 6 ( e ) show a process according to the first embodiment of the present invention, where a commercial piezoelectric actuator is assembled with a membrane. In each step of the process, generally known microfabrication techniques, such as masking, etching, deposition, and lift-off are used.

[0052] FIG. 6 ( a ) shows a first step, where a trench 41 having a trench depth is patterned into the silicon wafer substrate 3 . The trench depth is equal to the height of the air gap (for example between about 10 and about 100 microns) between the membrane (like the membrane 1 of FIG. 1 ) and the circuit to be tuned (like the circuit 2 of FIG. 1 ).

[0053] FIG. 6 ( b ) shows a second step, where the metal circuit 2 is deposited and patterned in the trench.

[0054] FIG. 6 ( c )(1) shows a third step, where a thin layer 44 , about 1 micron thick, of polymide, for example PIX-1400, is spinned onto the wafer 3 and the metal circuit 2 . The polymide layer 44 will act as an adhesive to bond the base substrate (the substrate comprising the circuit), and the carrier substrate (the substrate carrying the membrane and the actuator), together.

[0055] FIG. 6 ( c )(2) shows a third step alternative to the third step shown in FIG. 6 ( c )(1), where a polymide layer 44 is spinned onto a separate test wafer (not shown in the figures) and then the layer is transferred onto the base substrate 3 by pressing the base substrate 3 onto the test wafer and then lifting or sliding it off. Alternatively to the polymide layer 44 , a thin layer of gold, e.g. a layer having a thickness of 1 μm, can be deposited on the substrate 3 .

[0056] If the step of FIG. 6 ( c )(1) is followed, the thin layer of adhesive over the circuit does not pose a problem regarding the device performance. In the following steps it will be assumed that the third step of FIG. 6 ( c )(2) has been followed.

[0057] FIG. 6 ( d ) shows a fourth step, where a carrier substrate 45 carrying the membrane 1 and the metal film 4 is aligned and pressed onto the base substrate 3 . Bonding between the carrier substrate 45 and the base substrate 3 is obtained, for example, by pre-baking at about 100° C. for about 120 seconds, followed by a hard bake at about 120° C. for about 1 hour. In case a layer of gold is used, as disclosed above, such layer can be present either on the substrate 3 , or on the substrate 45 , or on both of them. Once gold is used, the bonding process preferably requires a first step of pressing the substrates 3 and 45 together and a second step of heating at a temperature preferably comprised between 200° C. and 400° C.

[0058] FIG. 6 ( e ) shows a fifth step, where the two-layered actuators 5 are connected to the membrane 1 .

[0059] The connection is obtained by spinning or transferring a thin layer of polymide on the commercial piezoelectric actuators 5 . The actuators 5 are then aligned and gently pressed onto the border of the membrane 1 , followed by hard baking at about 120° C. for about 1 hour to strengthen the bond. The actuators 5 are thus anchored on the membrane. As already explained with reference to FIGS. 1 - 4 , a first, inner, portion of the actuators 5 is supported by the membrane only, while a second, outer, portion of the actuators 5 is supported by the membrane and the substrate.

[0060] FIGS. 7 ( a )- 7 ( f ) and FIGS. 8 ( a )- 8 ( f ) show a process according to the second embodiment of the present invention, where a thin film home-made piezoelectric actuator is assembled with the polymide membrane during the fabrication process. The process according to the second embodiment is preferred, because a thin film piezoelectric actuator provides more flexibility in optimizing the thickness and lateral dimensions of the actuator as compared to a commercially available one. In each step of the process, generally known microfabrication, techniques such as masking, etching, deposition, and lift-off are used.

[0061] FIGS. 7 ( a )- 7 ( f ) show a first series of steps of the process according to the second embodiment.

[0062] FIG. 7 ( a ) shows a first step, where a silicon wafer 51 having a protective layer 52 (for example a SiN layer) deposited on the bottom side and etched trenches 53 on the top side is provided. The layer 52 is, for example, 0.5 microns thick. The depth of the trenches 53 is substantially equal to the thickness of the thin film piezoelectric actuator later obtained.

[0063] FIG. 7 ( b ) shows a second step, where a protective layer 54 (for example a SiN layer) of about 0.5 microns and a 0.5 microns Ti—Pt metal film 55 are deposited on the top side of the silicon wafer 51 .

[0064] FIG. 7 ( c ) shows a third step, where the Ti—Pt film 55 is patterned into rectangular pads 56 .

[0065] FIG. 7 ( d ) shows a fourth step, where the protective layer 52 on the bottom side of the wafer is patterned to form a mask 57 for the silicon etch. The window formed by means of the mask 57 is carefully aligned to the metal pads on the top side using an infrared mask aligner. Infrared aligners are known per se to the person skilled in the art, and will not be described in detail in the present application.

[0066] FIG. 7 ( e ) shows a fifth step, where the two-layered piezoelectric actuating structure 5 is formed. The piezoelectric structure comprises, for example, two layers of piezoelectric film intertwined with three layers of metal electrodes. For example, in case both layers are active, i.e. made of a piezoelectric material, the bottom electrode can be made of Ti—Pt, the middle electrode can be made of Ti—Pt, and the top electrode can be made of any metal. The metal electrodes are not shown in FIG. 7 ( e ), for clarity purposes. For a schematic representation of the metal electrodes, reference can be made, for example, to the elements 12 to 14 of FIGS. 5 ( a ) to 5 ( c ). The metal electrodes can have arms, not shown in FIG. 7 ( e ) for clarity purposes, extending out of the trench to allow access to them.

[0067] FIG. 7 ( f ) shows a sixth step, where a polymide layer 59 (forming the membrane 1 shown in FIG. 1 ) is spinned to achieve the desired thickness (usually about 4 to 30 microns). Additionally, the polymide layer 59 is cured at a temperature between about 200° C. and 400° C., preferably about 300° C., to firmly embed the piezoelectric actuating structure in the polymide.

[0068] FIGS. 8 ( a )- 8 ( f ) show a second series of steps of the process according to the second embodiment.

[0069] FIG. 8 ( a ) shows a seventh step, following the sixth step of FIG. 7 ( f ), where a metal film 60 , for example a Ti—Au film, is deposited on the cured polymide 59 . The metal film 60 will eventually be patterned into a tuning electrode like the metal film 4 of FIG. 1 .

[0070] FIG. 8 ( b ) shows an eighth step, where photoresist 61 is spinned, patterned and hard baked on the film 60 to act as a protective layer against the metal etchants used in the following tenth step.

[0071] FIG. 8 ( c ) shows a ninth step, where silicon is etched from the backside of the wafer by mounting the wafer in a customized wafer holder and immersing the holder in a KOH solution at about 100° C. The wafer holder, not shown in the figure but well known per se to the person skilled in the art, seals the polymide side from the KOH solution.

[0072] In this way, an opening 62 etched in the silicon substrate is formed. Preferably, the lateral dimensions of the metal pads 56 are just smaller (about 100 microns) than the lateral dimensions of the opening 62 . The lateral dimensions are the length and the width of the rectangular (when looking from the top) Ti—Pt film pad 56 . The lateral dimensions of the pads 56 are preferably smaller than the lateral dimensions of the opening 62 to possibly enable removal of the Ti—Pt pad. The use of a Ti—Pt pad is preferred, to make the fabrication process for the polymide membranes on silicon wafers more reliable. Embodiments where the Ti—Pt pad is not removed are also possible. In such embodiments, the Ti—Pt pad will form one of the electrodes.

[0073] FIG. 8 ( d ) shows a tenth step, where a portion of protective layer 54 , a portion of the Ti—Au layer 60 , and the rectangular pads 56 , are etched away, for example by successively immersing the wafer in buffered oxide etchant (BOE) solution together with a metal etchant solution and by dry etching. As a consequence of this step, the metal film 4 of FIG. 1 is formed. Alternatively, the rectangular pads 56 can be kept, to be used as a portion of the bottom electrode.

[0074] FIG. 8 ( e ) shows an eleventh step, where the residual photoresist 61 is removed, for example by spraying with acetone and spin drying. In this way, a carrier substrate containing a polymide membrane 59 , a metal film 4 , and actuators 5 is obtained.

[0075] FIG. 8 ( f ) shows a step where the carrier substrate obtained through the process described in FIGS. 7 ( a ) to 8 ( e ) is bonded to a base substrate like the one disclosed in FIG. 6 ( c )(2) to form the tunable device according to the present invention. As also disclosed in the embodiment fo FIG. 6 d , gold can be used to bond the two substrates.

[0076] With reference to FIG. 6 ( e ) and FIG. 8 ( f ), they both show a two-layered global structure, where the first layer comprises a wafer with membrane and actuator, and the second layer comprises a wafer with a circuit pattern or component. Given that the structure only contains two layers, such structure can be miniaturized using standard cleanroom processing techniques.

[0077] While several illustrative embodiments of the invention have been shown and described, numerous variations and alternative embodiments will occur to those skilled in the art. Such variations and alternative embodiments are contemplated, and can be made without departing from the scope of the invention as defined in the appended claims.