DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0094] Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

[0095] Embodiment 1

[0096] An electronic device according to a first specific preferred embodiment of the present invention is an infrared sensor including a plurality of infrared detectors (i.e., bolometers).

[0097] First, referring to FIGS. 1A and 1B , illustrated are a cross-sectional view and a plan view showing the process step of forming a cavity defining sacrificial layer. In the process step shown in FIGS. 1A and 1B , a selected surface area of a semiconductor substrate 10 is locally oxidized thermally by a known LOCOS process. The semiconductor substrate 10 for use in this preferred embodiment is preferably a single crystalline silicon wafer. Thus, a cavity defining insulating film 11 of silicon dioxide is formed as a thermal oxide as a result of this thermal oxidation process.

[0098] In the accompanying drawings, the cavity defining insulating film 11 is illustrated as being located in just one surface area of the semiconductor substrate 10 . However, the cavity defining insulating film 11 may be naturally formed in multiple surface areas of the same semiconductor substrate 10 at the same time. In the following description of preferred embodiments, a method of forming just one cavity on the semiconductor substrate 10 will be described for the sake of simplicity. However, a method of forming multiple cavities on the same substrate at the same time should be readily understandable to those skilled in the art by reference to the disclosure of the present application.

[0099] In a preferred embodiment of the present invention, various types of circuits (e.g., control circuits) are preferably provided on other non-illustrated areas of the semiconductor substrate 10 for the purpose of operating the sensor normally. Those circuits may be formed on the semiconductor substrate 10 by known semiconductor integrated circuit technologies. If an integrated circuit including transistors as its circuit components is formed on the semiconductor substrate 10 , then the respective MISFETs of the integrated circuit need to be electrically isolated from each other. Such electrical isolation is achieved by forming an isolation film on the semiconductor substrate 10 . To reduce the number of manufacturing process steps required, the process step of forming the isolation film is preferably carried out as the process step of forming the cavity defining insulating film 11 .

[0100] In this preferred embodiment, the cavity defining insulating film 11 preferably has a thickness of about 0.4 μm to about 1 μm and preferably has a rectangular planar shape of approximately 30 μm square to approximately 100 μm square. It should be noted, however, that the planar layout of the cavity defining insulating film 11 does not have to be rectangular but may also be any other shape.

[0101] Also, the cavity defining insulating film 11 does not have to be formed by the LOCOS process but may be formed by any other process. For example, a trench isolation process may also be adopted. In that case, trenches are preferably formed in advance on the surface of the semiconductor substrate 10 , and then filled with an insulating film to be deposited by a thin film deposition process such as a CVD process, for example.

[0102] Next, referring to FIGS. 2A and 2B , illustrated are a cross-sectional view and a plan view showing the process step of forming a silicon nitride layer, functioning as an etch stop layer, on the semiconductor substrate 10 .

[0103] In the process step shown in FIGS. 2A and 2B , a silicon nitride layer 12 is preferably deposited by a CVD process to a thickness of about 200 nm to about 400 nm on the semiconductor substrate 10 and the cavity defining insulating film 11 . This process step is preferably carried out with the substrate 10 heated to, and maintained at, about 760° C.

[0104] FIG. 3B is a plan view showing the process step of forming cavity defining openings (i.e., the first opening) and FIG. 3A is a cross-sectional view thereof as taken on the plane IIIa-IIIa shown in FIG. 3B .

[0105] In the process step shown in FIGS. 3A and 3B , first, a resist mask (not shown) is preferably defined by a photolithographic process on the silicon nitride layer 12 . This resist mask preferably has a pattern that defines the cavity defining openings 15 to extend through the silicon nitride layer 12 and the cavity defining insulating film 11 . The cavity defining openings 15 preferably have the arrangement pattern shown in FIG. 3 B and reach the surface of the silicon substrate 10 . Such cavity forming openings 15 may be formed by removing the exposed portions of the silicon nitride layer 12 , which are not covered with the resist mask, and then removing the exposed portions of the cavity defining insulating film 11 which are not covered with the resist mask. These etching process steps are preferably carried out by a dry etching technique that achieves sufficient anisotropy. These openings 15 may have a diameter of about 0.3 μm, for example.

[0106] As can be seen from FIG. 3 B, the pitch between adjacent openings 15 increases at four locations. At these four locations, the cavity defining insulating film 11 will not be removed completely but left partially in the next process step of forming provisional cavities.

[0107] FIG. 4B is a plan view showing the process step of forming the provisional cavities, and FIG. 4A is a cross-sectional view thereof as taken on the plane IVa-IVa shown in FIG. 4B . In this process step, the cavity defining insulating film 11 is preferably wet-etched with buffered hydrofluoric acid, thereby forming the provisional cavities 16 x and defining a supporting portion by the etch residues of the cavity defining insulating film 11 . This supporting portion is preferably made up of walls 11 a surrounding the provisional cavities 16 x and four columns 11 b , which are located among the provisional cavities 16 x . The ceiling of the provisional cavities 16 x (i.e., the etch stop layer) is supported by the walls 11 a and the columns 16 b , thereby preventing pieces of the silicon nitride layer 12 from dropping down and other unfavorable situations.

[0108] In the process step of forming the provisional cavities, an etchant for use to etch the cavity defining insulating film 11 isotropically is preferably supplied through the openings 15 , which are arranged as shown in FIG. 3 B, to the cavity defining insulating film 11 . Since the etching action advances isotropically, not only portions of the cavity defining insulating film 11 , which are located under the openings 15 , but also other intermediate portions thereof, which are located between adjacent openings 15 , are etched away. In the four locations at which the openings 15 are arranged at the increased pitch, the lateral etching action advances insufficiently from under the openings 15 . As a result, the etch residues are left, thereby defining the columns 11 b . In this preferred embodiment, if this etching process of forming the provisional cavities is carried out for too long a time, then the columns 11 b will lose much of its thickness and disappear in the end. For that reason, the arrangement pitch of the openings 15 and the etching time need to be adjusted appropriately.

[0109] It should be noted that the number and locations of the columns 11 b are not limited to those adopted in this preferred embodiment. Rather, a supporting portion having an arbitrary size or shape may be formed by changing the shape, size and planar layout of the openings 15 appropriately.

[0110] Next, the process step of temporarily closing up the openings 15 that were provided to form the provisional cavities is carried out. FIG. 5B is a plan view illustrating that process step, and FIG. 5A is a cross-sectional view thereof as taken on the plane Va-Va shown in FIG. 5B . In this process step, a silicon dioxide layer 20 is deposited by a CVD process to a thickness of about 350 nm over the semiconductor substrate 10 . The silicon dioxide layer 20 is preferably formed by supplying a TEOS source gas.

[0111] As a result, the cavity defining openings 15 , which the silicon nitride layer 12 as the ceiling of the provisional cavities 16 x has had until the previous process step, are closed up with the silicon dioxide layer 20 deposited. The silicon dioxide layer 20 is deposited by heating the substrate to about 680° C., which is much lower than the temperature of the substrate (e.g., about 900° C.) when the polysilicon film is thermally oxidized.

[0112] For a certain period of time after the process step of depositing the silicon dioxide layer 20 has been started, those openings 15 are still not closed entirely. Thus, an additional oxide layer is deposited on the bottom of the provisional cavities 16 x . Such an oxide layer will be referred to herein as a “bottom oxide layer 20 a”.

[0113] Subsequently, as shown in FIGS. 6A and 6B , the process step of depositing a resistor for the bolometer on the silicon dioxide layer 20 is carried out. FIG. 6B is a plan view illustrating the layout of a patterned resistor for the bolometer, and FIG. 6A is a cross-sectional view thereof as taken on the plane Via-Via shown in FIG. 6B .

[0114] In this process step, a polysilicon film is deposited to a thickness of about 500 nm over the semiconductor substrate 10 and then patterned by photolithographic and etching techniques. By patterning the polysilicon film, an approximately S-shaped resistor 21 may be defined for the bolometer, for example. This resistor 21 will eventually function as an infrared detector for the resultant infrared sensor. The resistor 21 is preferably provided so as not to overlap with the columns 11 b among the provisional cavities 16 x . In other words, no columns 11 b should be located right under the resistor 21 for the bolometer.

[0115] Next, as shown in FIGS. 7A and 7B , the process step of forming an interlevel dielectric film is carried out. FIG. 7B is a plan view, and FIG. 7A is a cross-sectional view thereof as taken on the plane VIIa-VIIa shown in FIG. 7B . In this process step, an interlevel dielectric film 24 of BPSG (boro phospho silicate glass) is deposited to a thickness of about 700 nm to about 1 μm over the silicon dioxide layer 20 and the resistor 21 for the bolometer. This interlevel dielectric film 24 will eventually function as an infrared radiation absorbing film.

[0116] Subsequently, as shown in FIGS. 8A and 8B , the process step of forming interconnects for the bolometer is carried out. FIG. 8B is a plan view illustrating a layout for the interconnects, and FIG. 8A is a cross-sectional view thereof as taken on the plane VIIIa-VIIIa shown in FIG. 8B .

[0117] In this process step, first, two holes are opened by photolithographic and dry etching processes so as to extend vertically through the interlevel dielectric film 24 and reach both terminals of the resistor 21 for the bolometer. Thereafter, these two holes are filled with tungsten (W), thereby forming two plugs 26 that are respectively connected to the two terminals of the resistor 21 for the bolometer. Furthermore, an Al alloy film is deposited on the interlevel dielectric film 24 and then patterned, thereby defining two interconnects 25 that are connected to the two plugs 26 , respectively. These interconnects 25 will be used to electrically connect a pixel region in which the bolometer is provided to a peripheral circuit. As will be described later, the resistor 21 changes its electrical resistance depending on whether the resistor 21 is exposed to infrared radiation or not. Accordingly, by sensing the variation in the electrical resistance of the resistor 21 by the amount of current flowing through the interconnects 25 , the infrared exposure dose of the infrared sensor can be detected.

[0118] Thereafter, the process step of forming a passivation film is carried out. FIG. 9B is a plan view illustrating a structure already including the passivation film, and FIG. 9A is a cross-sectional view thereof as taken on the plane IXa-IXa shown in FIG. 9B . In this process step, a passivation film 27 of silicon nitride is preferably deposited over the interlevel dielectric film 24 and the interconnects 25 . The passivation film 27 functions not only as a protective insulating film but also as an infrared radiation absorbing layer. The passivation film 27 may be deposited at about 400° C., for example.

[0119] Finally, the process step of defining a final cavity is carried out. FIG. 10B is a plan view illustrating a structure in which the final cavity has already been defined, and FIG. 10A is a cross-sectional view thereof as taken on the plane Xa-Xa shown in FIG. 10B . In this process step, portions of the passivation film 27 , interlevel dielectric film 24 , silicon dioxide layer 20 and silicon nitride layer 12 , which have been located over the columns 11 b , are removed by photolithographic and dry etching techniques, thereby forming holes (i.e., the second openings) 28 . Thereafter, the columns 11 b , located among the provisional cavities 16 x , are also etched away through the holes 28 . As a result of this process step, at least the upper half of the columns 11 b is removed, thereby defining a final cavity 16 A, which has a greater inner volume than the total inner volume of the provisional cavities. In the example illustrated in FIG. 10 A, the columns 11 b are removed completely and the bottom oxide layer 20 a is also removed partially.

[0120] In the preferred embodiment described above, the columns 11 b are formed in the process step shown in FIGS. 4A and 4B . Alternatively, walls may be laid out as a supporting portion so as not to be overlapped by the resistor 21 for the bolometer. If such walls are provided, the holes 28 should be opened over those walls, and the walls should be removed at least partially (preferably entirely) by an etching process, in the process step shown in FIGS. 10A and 10B .

[0121] In the manufacturing process of this preferred embodiment, the supporting portion, including the columns and walls, is removed at least partially from inside of the final cavity 16 A. As a result, the supporting portion is removed entirely, or at least the connections between the supporting portion and the etch stop layer are cut off, thus reducing a thermal conductance to be created between the resistor 21 for the bolometer and the silicon substrate. Consequently, the infrared spectral responsivity or resolution can be improved.

[0122] In the preferred embodiment described above, the cavity defining openings 15 of the silicon nitride layer 12 , functioning as the etch stop layer, are closed up with the CVD oxide layer. If the openings 15 are closed up by oxidizing a polysilicon film, then a high-temperature process must be carried out, the respective members of the ceiling may be deformed excessively, and the ceiling itself may collapse. According to this preferred embodiment, however, no such high-temperature processes are required. This is advantageous particularly when transistors, for example, need to be provided on the semiconductor substrate 10 separately from the infrared detectors, because the characteristics of the transistors might be affected by such high-temperature processes.

[0123] In the preferred embodiment described above, a LOCOS film is used as the cavity defining insulating film 11 . Alternatively, the LOCOS film may be replaced with a trench isolation film such as a shallow trench isolation (STI) film.

[0124] Also, the resistor 21 for the bolometer may also be made of Ti, TiO, Pt or VO _x , not just polysilicon. Each of these alternative materials also changes its electrical resistance when its temperature rises responsive to the incident infrared radiation. Thus, these materials may also be used for variable-resistance infrared detectors (i.e., bolometers).

[0125] In the infrared sensor of this preferred embodiment, the total thickness of the passivation film 27 and interlevel dielectric film 24 is preferably about 1 μm to about 2 μm (e.g., about 1.6 μm). The reason is as follows. Specifically, if the total thickness of these films is about 1 μm or more, then the infrared absorption coefficient can be kept sufficiently high. And if the total thickness of these films is about 2 μm or less, then these films will not have an excessive heat capacity.

[0126] Generally speaking, if a silicon process is adopted to form bolometers as infrared detectors, then high-temperature treatment must be carried out in a number of process steps, thus creating an internal stress due to a difference in thermal expansion coefficient (or shrinkage coefficient) among respective members of the bolometers. Thus, the conventional method of fabricating an infrared sensor by utilizing a silicon process has the following drawbacks:

[0127] If the number or the transversal cross-sectional area of the columns to support the ceiling of the cavities is decreased, then the ceiling of the cavities will have a decreased mechanical strength. In that case, the cavities might be blocked with the ceiling collapsed during the manufacturing process of the infrared sensor; but

[0128] If the number or the transversal cross-sectional area of the columns to support the ceiling of the cavities is increased, then the infrared detectors (i.e., bolometers) cannot be thermally insulated from the substrate sufficiently, thus decreasing the responsivity of the infrared sensor.

[0129] Hereinafter, it will be described in detail exactly how such problems are caused by a tensile stress to be applied to a silicon nitride layer grown. FIGS. 11A through 11D are perspective views showing the problems of a conventional infrared sensor manufacturing process to be compared with the process of this preferred embodiment. On the other hand, FIGS. 12A through 12C are perspective views showing the advantages of the infrared sensor manufacturing process of this preferred embodiment.

[0130] In the conventional manufacturing process, first, a silicon nitride layer is deposited by a CVD process on a cavity defining insulating film as shown in FIG. 11A . Thereafter, when the temperature of the substrate is decreased to its normal temperature, the substrate will be warped upward, thus creating a tensile stress in the silicon nitride layer. The situation shown in FIG. 11A corresponds to the process step shown in FIGS. 2A and 2B . Such a stress is created due to a difference in thermal expansion coefficient (or shrinkage coefficient) between the silicon nitride layer and the silicon substrate or due to structural defects that produce depending on the growth conditions. According to a document entitled “Applied Physics Data Book” (published by Maruzen Co., Ltd., p. 528), when a silicon nitride layer is deposited on a silicon substrate, a huge tensile stress of about 10 ⁻¹⁰ dyn/cm ² is applied to the silicon nitride layer in such a situation.

[0131] Next, when holes are formed by a dry etching process so as to extend through the silicon nitride layer and the cavity defining insulating film as shown in FIG. 11 B, an even greater tensile stress is applied to the silicon nitride layer. The situation shown in FIG. 11B corresponds to the process step shown in FIGS. 3A and 3B .

[0132] Suppose a final cavity is defined after that by a wet etching process with no columns or walls left as shown in FIG. 11C for the purpose of increasing the responsivity of the infrared sensor. In that case, if the final cavity is defined by removing the cavity defining insulating film of silicon dioxide completely, then the stress will be concentrated on the silicon nitride layer, thus partially cracking the silicon nitride layer. As a result, pieces of the silicon nitride layer might drop down into the final cavity as shown in FIG. 11D .

[0133] On the other hand, in the manufacturing process of this preferred embodiment, after the holes have been defined as shown in FIG. 11 B, provisional cavities are once defined by a wet etching process with columns left as shown in FIG. 12A (corresponding to the process step shown in FIGS. 4A and 4B ) unlike the conventional process step shown in FIG. 11C . At this point in time, the silicon nitride layer is still supported by the columns. Thus, it is possible to prevent the silicon nitride layer from being cracked or collapsed as shown in FIG. 11D .

[0134] Thereafter, as shown in FIG. 12 B, the openings of the ceiling for the provisional cavities are closed up with a TEOS film, and then an interlevel dielectric film and a passivation film are deposited thereon in this order (in the process step shown in FIGS. 5A and 5B and in the process step shown in FIGS. 6A and 6B ). At this point in time, the silicon nitride layer has been reinforced with the TEOS film, interlevel dielectric film and passivation film. In the manufacturing process of this preferred embodiment, a resistor for a bolometer is actually provided between the TEOS film and the interlevel dielectric film. However, the illustration of such a resistor is omitted from FIG. 12B for the sake of simplicity.

[0135] Subsequently, as shown in FIG. 12 C, the columns between the provisional cavities are removed to define a final cavity (in the process step shown in FIGS. 10A and 10B ). In the manufacturing process of this preferred embodiment, interconnects are actually formed on the interlevel dielectric film. However, the illustration of the interconnects is omitted from FIG. 12C for the sake of simplicity.

[0136] Thus, according to the manufacturing process of this preferred embodiment, an infrared sensor with a sufficiently high infrared spectral responsivity or resolution can be provided while preventing the silicon nitride layer, which functions not only as an etch stop layer but also as a framework for the ceiling of the cavities, from being cracked or collapsed.

[0137] Embodiment 2

[0138] Hereinafter, a method for fabricating an infrared sensor according to a second specific preferred embodiment of the present invention will be described. In the manufacturing process of this second preferred embodiment, the respective process steps of the first preferred embodiment described above are also carried out as shown in FIGS. 1A through 10B until the final cavity is defined.

[0139] FIG. 13B is a plan view illustrating a structure in which the final cavity of this second preferred embodiment has just been defined, and FIG. 13A is a cross-sectional view thereof taken on the plane XIIIa-XIIIa shown in FIG. 13B .

[0140] In this second preferred embodiment, the locations and shape of a second group of openings to be defined by photolithographic and dry etching processes through the passivation film 27 , interlevel dielectric film 24 and silicon nitride layer 12 are different from those of the counterparts of the first preferred embodiment described above. More specifically, in this second preferred embodiment, the holes 30 are defined as the second group of openings on a sidewall 11 a that surrounds the provisional cavities 16 x . Then, at least a portion of the sidewall 11 a is etched away through the holes 30 , thereby expanding the provisional cavities into a final cavity.

[0141] As a result of this etching process, the columns 11 b are not etched but left, while the sidewall 11 a is partially etched downward to be a sidewall 11 c with a narrower width. Consequently, a final cavity 16 B is defined so as to have a greater transversal sectional area than the total one of the provisional cavities. Also, as a result of the etching process, the bottom oxide layer 20 a on the bottom of the final cavity 16 B is also etched partially.

[0142] In the first preferred embodiment described above, all of the columns 11 b are removed entirely from inside of the final cavity 16 A. However, if the final cavity 16 A has a relatively large transversal sectional area, then the members that make up the ceiling of the final cavity 16 A might be cracked or collapsed. Thus, in this second preferred embodiment, the columns 11 b are left and the sidewall 11 a is partially removed, thereby improving the infrared spectral responsivity and resolution.

[0143] In this second preferred embodiment, the cavity defining openings 15 of the silicon nitride layer 12 are also closed up with the silicon dioxide layer 20 that has been deposited by a CVD process. Thus, as in the first preferred embodiment described above, the manufacturing process can be advanced without placing any excessive thermal strain onto the ceiling of the cavities. As a result, the effects of the first preferred embodiment are also achieved by this second preferred embodiment.

[0144] If the final cavity 16 B has a transversal sectional area of about 1,000 gm ² or more, then two to ten columns, each having a transversal sectional area of at least about 10 μm ² , are preferably left inside of the final cavity 16 B. Then, the ceiling of the cavity 16 B will not be cracked.

[0145] Conversely, when it is unlikely that the ceiling should collapse even if the columns 11 b are removed, the holes 28 of the first preferred embodiment described above, as well as the holes 30 , may be defined and then not just the sidewall 11 a but the columns 11 b may be etched either partially or entirely.

[0146] Embodiment 3

[0147] Hereinafter, a third specific preferred embodiment of the present invention will be described. In this preferred embodiment, a silicon substrate is used as the cavity defining layer (i.e., the cavity defining sacrificial layer).

[0148] First, as shown in FIGS. 14A and 14B , the process step of forming a silicon nitride layer on a substrate 40 is carried out. FIG. 14B is a plan view illustrating the substrate 40 on which the silicon nitride layer 42 has been deposited, and FIG. 14A is a cross-sectional view thereof.

[0149] In this process step, the silicon nitride layer 42 is deposited by a CVD process to a thickness of about 200 nm to about 400 nm on the silicon substrate 40 that has been heated to, and maintained at, about 760° C. The silicon nitride layer 42 will function as an etch stop layer.

[0150] Next, as shown in FIGS. 15A and 15B , the process step of forming openings 45 through the silicon nitride layer 42 is carried out. FIG. 15B is a plan view illustrating an exemplary arrangement of the openings 45 , and FIG. 15A is a cross-sectional view thereof taken on the plane XVa-XVa shown in FIG. 15B .

[0151] In this process step, the silicon nitride layer 42 is dry-etched with a resist mask (not shown), which has been defined by a photolithographic process, thereby forming cavity defining openings 45 through the silicon nitride layer 42 . In the example illustrated in FIG. 15 B, nine openings 45 are arranged in three columns and three rows. The pitch of three horizontally arranged openings 45 that make up each row is greater than that of three vertically arranged openings 45 that make up each column.

[0152] Then, as shown in FIGS. 16A and 16B , the process step of defining provisional cavities is carried out. FIG. 16B is a plan view illustrating a structure in which the provisional cavities have been defined, and FIG. 16A is a cross-sectional view thereof taken on the plane XVIa-XVIa shown in FIG. 16B .

[0153] In this process step, portions of the silicon substrate 40 are wet-etched with an alkaline etchant such as KOH or hydrazine. This etching action advances isotropically from portions of the silicon substrate 40 , which are exposed inside of the openings 45 . The isotropic wet etching action advances not only vertically but also laterally. Accordingly, a portion of the silicon substrate 40 , which is located between two horizontally adjacent cavity defining openings 45 , is etched from both sides. Thus, as shown in FIG. 16 B, two concave portions formed by the etching process may be linked together where two adjacent openings 45 are arranged at a relatively narrow pitch, but etch residues may be left where two adjacent openings 45 are arranged at a relatively wide pitch.

[0154] In this manner, a number of provisional cavities 46 x are defined and walls 40 a are also defined by the residues of the silicon substrate 40 between those provisional cavities 46 x as shown in FIGS. 16A and 16B .

[0155] In the example illustrated in FIG. 16 B, each set of three adjacent provisional cavities 46 x arranged in the column direction are linked together, while each set of three adjacent provisional cavities 46 x arranged in the row direction are still separated from each other. However, the arrangement of the provisional cavities 46 x is not limited to such an arrangement. Alternatively, the provisional cavities 46 x may be all isolated from each other, some of them linked together, or even all of them combined together. In any case, the provisional cavities 46 x can be freely designed based on the shape, size and arrangement of the cavity defining openings 45 . The provisional cavities 46 x are also changeable with the wet etching conditions.

[0156] In this preferred embodiment, it is important to leave the walls 40 a that function as a supporting portion for the etch stop layer and prevent the provisional cavities from being blocked. For that reason, in performing the wet etching process to define the provisional cavities 46 x , the etching conditions need to be adjusted such that no single continuous big cavity, free of columns or walls, will be defined.

[0157] Subsequently, the process step of closing up the openings 45 is carried out. FIG. 17B is a plan view illustrating a structure in which a silicon dioxide layer 50 has just been deposited, and FIG. 17A is a cross-sectional view thereof taken on the plane XVIIa-XVIIa shown in FIG. 17B . In this process step, the silicon dioxide layer 50 of TEOS is deposited by a CVD process to a thickness of about 350 nm over the substrate 40 , thereby closing up the cavity defining openings 45 of the silicon nitride layer 42 that functions as the ceiling of the provisional cavities 46 x . Meanwhile, a bottom oxide layer 50 a is also deposited on the bottom of the provisional cavities 46 x.

[0158] FIG. 18B is a plan view illustrating a structure in which a second group of openings have been formed through the silicon dioxide layer 50 , and FIG. 18A is a cross-sectional view thereof taken on the plane XVIIIa-XVIIIa shown in FIG. 18B . In this process step, first, holes 58 are defined by removing portions of the silicon dioxide layer 50 by photolithographic and dry etching techniques so as to be located over the walls 40 a between the provisional cavities 46 x . Then, the walls 40 a are etched downward through those holes 58 . As a result of this etching process, a final cavity 46 is defined. Thus, according to this third preferred embodiment, cavities can be formed directly on the silicon substrate 40 without using any insulating film such as the LOCOS film.

[0159] It should be noted that before the final cavity 46 is defined, the resistor for the bolometer may be formed as in the first and second preferred embodiments described above. In that case, a patterned resistor for the bolometer is provided in an S shape as indicated by the dashed lines in FIG. 18B . Although not shown, after the resistor has been formed, an interlevel dielectric film and a passivation film are deposited in this order over the resistor and then the holes 58 are defined so as to extend these films.

[0160] Embodiment 4

[0161] Hereinafter, preferred embodiments of an infrared sensor including the resistor for bolometer of any of the first, second and third preferred embodiments of the present invention will be described.

[0162] FIGS. 19A and 19B are respectively a cross-sectional view and an electric circuit diagram of an infrared sensor according to a fourth specific preferred embodiment of the present invention. The infrared sensor to be described below is supposed to include the infrared detector of the third preferred embodiment shown in FIGS. 18A and 18B . Alternatively, the infrared sensor may also include the infrared detectors of the first or second preferred embodiment described above.

[0163] As shown in FIG. 19 A, the infrared sensor of this preferred embodiment preferably includes: a silicon substrate 110 with a thickness of about 700 μm; a resistive element (or bolometer) 120 provided on the silicon substrate 110 ; a switching transistor 130 , which is also provided on the silicon substrate 110 and which turns ON and OFF the current to be supplied to the resistive element 120 ; and a cap member 140 for use to maintain a reduced pressure atmosphere around the resistor 120 . This infrared sensor may have an overall size of about several millimeters. On the silicon substrate 110 , provided are a resistor 111 with a winding pattern, a silicon nitride layer 112 and a silicon dioxide layer (e.g., a TEOS film) 113 that support the resistor 111 thereon, and an interlevel dielectric film (e.g., BPSG film) 116 and a passivation film (e.g., silicon nitride layer) 117 that cover the resistor 111 . The winding resistor 111 , silicon dioxide layer 113 , interlevel dielectric film 116 and passivation film 117 are vertically sandwiched between a pair of cavities 119 and 143 in which a vacuum has been created. These cavities 119 and 143 are linked together via holes Het that extend through the silicon nitride layer 112 , silicon dioxide layer 113 and interlevel dielectric film 116 .

[0164] The resistor 111 may be made of Ti, TiO, polysilicon or Pt.

[0165] A ringlike film 118 of a soft metallic material (e.g., aluminum) is provided on a portion of the passivation film 117 , which is located under the cylinder portion 142 of the cap member 140 . Another ringlike film 144 of a soft metallic material such as aluminum is also provided at the bottom of the cylinder portion 142 . The ringlike bonding portion 115 to be defined between these two ringlike films 118 and 144 maintains the reduced pressure atmosphere (or vacuum) in the cavity 143 between the cap member 140 and the silicon substrate 110 and in the cavity 119 in the silicon substrate 110 . That is to say, due to the presence of these cavities 143 and 119 , the resistor 111 is thermally insulated from the silicon substrate 110 such that the temperature rises efficiently responsive to incident infrared radiation.

[0166] The cap member 140 includes a substrate portion 141 , which is obtained by epitaxially growing a Ge layer to a thickness of about 3 μm and an Si layer to a thickness of about 1 μm on a silicon substrate with a thickness of about 700 μm. A Fresnel lens is preferably provided on the surface of the Si layer. The cavity 143 with a depth of at least several μm is defined by the cylinder portion 142 of the cap member 140 . It should be noted that a portion to be a window portion may be thinned by an etching technique, for example.

[0167] The switching transistor 130 includes a source region 131 , a drain region 132 and a gate electrode 133 . The source region 131 is defined under the cylinder portion 142 of the cap member 140 . That is to say, the source region 131 is provided as a signal line to electrically connect the resistor 111 , encapsulated in the vacuum, to an external member.

[0168] Although not shown in FIG. 19A, a Peltier device is preferably attached to the lower surface of the silicon substrate 110 for the purpose of cooling the resistive element. The Peltier device utilizes the absorption of heat that occurs when carriers move across a Schottky contact. In this preferred embodiment, any of various types of Peltier devices with a known structure may be used.

[0169] As shown in FIG. 19 B, one terminal of the resistor 111 is connected to a line 135 that provides a supply voltage Vdd, while the other terminal thereof is connected to the drain region 132 of the switching transistor 130 . A switching signal is input to the gate of the switching transistor 130 by way of a line 136 . The source of the switching transistor 130 is connected to an infrared detector (not shown) for detecting the infrared exposure dose of the resistor 111 by way of a line 138 that has a standard resistor at the other end thereof. The substrate region of the switching transistor 130 is connected to a ground terminal, which supplies a ground voltage Vss, by way of a line 137 . In this configuration, when infrared radiation is incident onto the resistor 111 , the resistor 111 increases its temperature in accordance with the exposure dose thereof, thus also changing the electrical resistance thereof. Then, the potential level on the line 138 also changes. Accordingly, the infrared exposure dose can be detected based on the magnitude of this potential variation.

[0170] In a discrete infrared sensor, an operational amplifier for amplifying the output of the bolometer may also be provided on the same substrate. In that case, the operational amplifier, as well as the bolometer and switching transistor of this preferred embodiment, may be encapsulated by the cap member.

[0171] Hereinafter, a method of making a cap member for use in the electronic device of this preferred embodiment will be described with reference to FIGS. 20A through 20E .

[0172] First, as shown in FIG. 20A, a cap prototype wafer 150 is prepared by epitaxially growing a Ge layer and an Si layer in this order on a silicon wafer. The Ge layer may be epitaxially grown to a thickness of about 3 μm on the silicon wafer in the following manner. Specifically, an Si _1-x Ge _x layer is epitaxially grown on the silicon wafer such that the Ge mole fraction x changes from 0 to 1 and then the Ge layer is epitaxially grown to the thickness of about 3 μm. Thereafter, another Si _1-x Ge _x layer is epitaxially grown on the Ge layer such that the Ge mole fraction x changes from 1 to 0 and the Si layer is epitaxially grown to a thickness of about 1 μm. Subsequently, a Fresnel lens, which will be divided into multiple convex lenses for use to focus an infrared ray onto each infrared sensor, is formed on the surface of the Si layer.

[0173] Next, with the Fresnel lens on the cap prototype wafer 150 facing downward, an Al film 151 is deposited by an evaporation, sputtering or any other suitable process to a thickness of about 600 nm on the other side of the cap prototype wafer 150 (i.e., so as to face the Ge and Si layers with the silicon wafer interposed between them).

[0174] Subsequently, the Al film 151 is etched by using a resist pattern (not shown) defined thereon as a mask, thereby forming a plurality of ringlike films 144 as shown in FIG. 20B .

[0175] Thereafter, by using either the ringlike films 144 as a hard mask or the resist pattern left as it is, the cap prototype wafer 150 is subjected to a dry etching process (e.g., a reactive ion etching (RIE) process). In this manner, a plurality of cylinder members 142 , each defining a cavity for an infrared sensor, are made of the cap prototype wafer 150 as shown in FIG. 20C . As a result, the cap prototype wafer 150 now consists of a wafer portion 141 including the residues of the silicon wafer, the Ge layer, the Si layer and the Fresnel lens, and the cylinder members 142 . The height of the cylinder members 142 (i.e., the depth of the concave portions) may be at least several μm.

[0176] Alternatively, the cap members may also be formed by using not such a bulk silicon wafer but an SOI wafer including an oxide insulating layer (e.g., a so-called “BOX layer”). In that case, the silicon wafer can be etched such that a high etch selectivity is achieved between the insulating layer and the silicon wafer. Thus, the concave portions can be formed just as intended, i.e., no farther than the bottom of the insulating layer.

[0177] Next, as shown in FIG. 20 D, the wafer portion 141 of the cap prototype wafer 150 is turned over so as to face upward and then subjected to a dry etching process (e.g., an ICP-RIE process), thereby forming notches 152 to make the wafer portion 141 easily dividable into respective cap members for infrared sensors. Meanwhile, a body wafer 100 having the structure shown in FIG. 19A is also prepared, and a plurality of ringlike films 118 of Al are formed on the body wafer 100 .

[0178] Thereafter, as shown in FIG. 20 E, the cap prototype wafer 150 is mounted onto the body wafer 100 on which the infrared detectors have been formed by the manufacturing process of the third preferred embodiment described above, for example. Then, these two wafers 150 and 100 are pressed against each other and bonded together with the two groups of ring-like films 118 and 144 aligned and bonded with each other. In this manner, the ringlike bonding portions 115 such as that shown in FIG. 19A are defined.

[0179] Finally, as shown at the bottom of FIG. 20 E, the cap prototype wafer 150 , as well as the infrared sensors, is divided along the notches 152 , while the body wafer 100 is also diced into a number of chips for the respective infrared sensors. As a result, a plurality of discrete infrared sensors, each including a silicon substrate 110 and a cap member 140 , are completed.

[0180] FIG. 21 is a cross-sectional view schematically illustrating a configuration for a pressure bonding apparatus. As shown in FIG. 21, a supporting member 161 for applying a pressure for the pressure bonding purposes, a broad band rotary pump 162 for maintaining a vacuum inside a chamber 160 , and Ar irradiators 163 and 164 are attached to the chamber 160 . Into this apparatus, the body wafer 100 and the cap prototype wafer 150 are loaded such that the body wafer 100 is located over the cap prototype wafer 150 . Then, the respective ringlike films 118 and 144 (see FIG. 20D ) are exposed to Ar atom beams that have been irradiated from the Ar irradiators 163 and 164 . As a result of this Ar beam exposure, contaminants and oxide layers are removed from the surface of Al of the ringlike films 118 and 144 . Thereafter, with a vacuum of about 10 ⁻⁴ Pa maintained inside the chamber 160 , a pressure of about 0.5 MPa to about 20 MPa is applied to between the two groups of ringlike films 118 and 144 at a normal temperature of about 30° C., for example, thereby bonding these two groups of ringlike films 118 and 144 together. Optionally, to remove Ar from the surface of the ringlike films 118 and 144 , the ringlike films 118 and 144 may be pre-heated to about 150° C. before the pressure bonding process is carried out.

[0181] Alternatively, O atoms or any other neutral atoms may be irradiated instead of the Ar atoms. Even so, similar effects are also achievable because dangling bonds can also be exposed on the surface of the metal (i.e., Al in this case) as in this preferred embodiment.

[0182] The metals to be bonded together may be Al or any of various other metals (including alloys thereof). Among other things, In, Cu, Au, Ag and an Al—Cu alloy having low melting points are particularly preferred because such a metal or alloy can be bonded at a normal temperature or at least around a normal temperature. These metals to be bonded together may be either the same as each other or different from each other. For example, if In films are deposited by an evaporation process, patterned into ringlike films, and then subjected to a pressure, the surface of the In films will break down, a natural oxide layer disappears from the surface portions of the In films, and the In films can be bonded together. The pressure bonding process may also be carried out in this manner.

[0183] Furthermore, the bonding process does not have to be carried out as such a thermal pressure bonding process but may also be an ultrasonic bonding process, a bonding process to be performed at a normal temperature by modifying the compositions, or any other method. As another alternative, the bonding process may also be carried out as hydrogen bonding between Si and Si, between Si and an oxide, or between two oxides.

[0184] Specifically, the bonding process is preferably carried out at a vacuum of about 10 ⁻² Pa to about 10 ⁻⁴ Pa. In that case, the infrared sensor can always exhibit sufficiently high performance while maintaining a high vacuum inside and yet various inconveniences, which are normally caused to maintain such a high vacuum, can be avoided. As a result, a practical bonding process can be carried out easily, thus contributing to mass production significantly.

[0185] In this preferred embodiment, not the overall array of cells such as sensors or radiators is maintained in a vacuum. A wafer including a great number of infrared sensors thereon is once prepared, but is divided into multiple chips, each of which is then encapsulated in a vacuum to define an infrared sensor chip. Accordingly, this preferred embodiment can also be used effectively even in a discrete device. This preferred embodiment is applicable for actual use particularly effectively, because a normal electronic device manufacturing process (e.g., a CMOS process, in particular) can be used as it is.

[0186] In this preferred embodiment, the sealing portions are not soldered up as in the prior art, but bonded together by subjecting a pair of soft metals such as aluminum to a pressure bonding process. Thus, this preferred embodiment is also effective in reducing the size of infrared sensors and other types of electronic devices.

[0187] According to the manufacturing process of this preferred embodiment, even when a great number of discrete infrared sensors are formed on a wafer, the cap members can be bonded for the respective infrared sensors individually. Particularly when the notches 152 are provided for the wafer portion 141 as shown in FIG. 20 D, the stresses to be applied to the bonding portions of the respective cells can be uniformized. In that case, no excessive stress will be applied locally to the portions being bonded together. As a result, the bonding portions can be bonded together with high reliability.

[0188] Embodiment 5