DETAILED DESCRIPTION

[0037] For a thorough understanding of the subject invention, refer to the following Detailed Description, including the appended Claims, in connection with the above-described Drawings.

[0038] Although the present invention is described in connection with several embodiments, the invention is not intended to be limited to the specific forms set forth herein. On the contrary, it is intended to cover such alternatives, modifications, and equivalents as can be reasonably included within the scope of the invention as defined by the appended Claims.

[0039] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the invention. It will be apparent, however, to one skilled in the art that the invention can be practiced without these specific details.

[0040] References in the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Moreover, various features are described which may be exhibited by some embodiments and not by others. Similarly, various requirements are described which may be requirements for some embodiments but not other embodiments.

Introduction

[0041] The present invention includes an algorithm that performs the constraints-based global routing step in the physical design of integrated circuits. The algorithm is based on finding routes for the entire circuit based on constraints being satisfied for the entire design. Initially, for each net, a set of possible routing solutions is determined based on applicable constraints. The possible solutions for the nets are combined to create a highly-connected “intersection graph,” showing nets which “intersect,” indicating that the nets share a node. Weights, based on constraints, are added to the edges of the intersection graph. Using these weights, the intersection graph is “pruned” to eliminate edges, producing a sparse graph. The intersection graph is partitioned based on constraints and performance criteria. An optimal solution is determined for each partition. The optimal solutions for the partitions are then combined to produce a global routing solution. The global routing solution is provided to a detailed router, which completes the routing for the design.

[0042] The present invention produces solutions which meet timing constraints and have overall less congestion than other possible solutions. During routing, a static two-dimensional parasitic extraction and timing analysis is performed to minimize resistance and capacitance while meeting timing constraints. In one embodiment, a 3D parasitic extraction module can be used in conjunction with the present invention to enable three-dimensional parasitic extraction between layers of the circuit design.

[0043] FIG. 1 is a flow diagram of the automated integrated circuit design process. Initially Place Circuit Components step 110 indicates that most routing tools used for cell-based designs begin with the placement of circuit elements, cells and/or cell blocks. Placement can be manual or automated, and typically attempts to make intelligent decisions about where connectors to the circuit elements, cells and/or cell blocks should be located, as well as how cells and/or blocks should be oriented and positioned relative to one another. Such decisions can be driven by considerations of circuit compaction, number of interconnect lines running between the blocks, and so on. With gate array designs, there is no placement step because placement has been pre-determined by the manufacturer.

[0044] Global Routing step 120 shows that the next step in completing the circuit design is typically a global routing step, which logically determines the paths for each interconnection. These decisions are made based on the available avenues formed by the current placement of circuit elements and/or blocks, and are assigned in consideration of various costs (e.g., the shortest total amount of interconnect lines between the connectors).

[0045] Once the global router has assigned the general flow of interconnect lines, in Detailed Routing step 130 , a detailed router takes over and attempts to make the interconnect lines fit the assignments made by the global router. The detailed router uses the number of tracks provided for each metal layer to assign a track for eachnode through which the net, provided as input by the Global Routing step 120 , must be routed. As shown in Output Representative of Routed Circuit Design step 140 , the output of the detailed router represents the complete routed circuit design.

[0046] FIG. 2 shows a flowchart of an algorithm to perform the constraints-based global routing step in the physical design of VLSI circuits. This flowchart shows an embodiment of Global Routing step 120 according to the present invention. In Provide Floorplan Design and Constraints step 205 , constraints and the output from Initially Place Circuit Components step 110 are provided to the global routing tool. The output from Initially Place Circuit Components step 110 includes a floorplan that initially places circuit components, obstructions and connectors or pins within the design. Examples of obstructions include power grids, blocks, and charge pumps. The present invention allows for routing around obstructions of any rectilinear shape, including designs having 45° and/or diagonal lines.

[0047] In 3D Graph Creation step 210 , a three-dimensional graph representing the circuit design is created. In Develop Feasible Solution Set for Each Net step 220 , a feasible solution set for each net is developed. In Create Intersection Graph with Weights step 230 , a graph is created including the intersections of the solution sets for each net. Weights are assigned to the edges in the intersection graph to represent the constraints. In one embodiment, the intersection graph can be “pruned” to convert the highly-connected intersection graph into a more sparsely-connected graph.

[0048] In Partition Intersection Graph step 240 , the intersection graph is divided into partitions. In Develop Solution for Each Partition step 250 , an optimal solution for each partition is determined using, for example, linear programming techniques. When the partitions are solved one at a time, optimal solutions for each partition can be merged with previously-obtained optimal solutions for partitions. The output of Develop Solution for Each Partition step 250 , with a solution for each partition, is used as input for the detailed router, as shown in Provide Output as Input for Detailed Router step 260 .

[0049] One of skill in the art will recognize that each of the steps of the flowchart of FIG. 2 can be performed by a module of a global routing tool, also referred to as a global router, or by a stand-alone module working in conjunction with the global routing tool. For example, Provide Floorplan Design and Constraints step 205 can be performed by a Floor Planning and Constraint Determination module. 3D Graph Creation step 210 can be performed by a 3D Graph Creation module, Develop Feasible Solution Set for Each Net step 220 can be performed by a Net Solution Set Generation module, and Create Intersection Graph with Weights step 230 can be performed by an Intersection Graph Creation module. Partition Intersection Graph step 240 can be performed by a Graph Partition module, and Develop Solution for Each Partition step 250 can be performed by an Optimization module, also referred to as an LP solver for embodiments using linear programming techniques. Provide Output as Input for Detailed Router step 260 can be performed by an Output Provider module. The global routing tool may receive input from a user via a User Interface module, or the global routing tool may be completely automated. Each of these modules may reside on the same computer system, or the modules may be distributed across nodes of a distributed software system.

[0050] It is within the scope of the invention that at least some of these modules may be run in parallel. For example, the development of feasible solutions for each net performed by Develop Feasible Solution Set for Each Net step 220 can be performed in parallel. In an example environment having 10 computer systems available for calculating solutions sets, a design having 1,000 nets may be divided into sets of 100 nets for each computer system. The ten computer systems can find the solutions in parallel, and the resulting feasible solution sets can be passed to Create Intersection Graph with Weights step 230 . If Develop Feasible Solution Set for Each Net step 220 is performed in parallel, the design can be divided such that nets that have noise between them are placed in the same set to be solved by the same computer system. In this way, noise avoidance is taken into account in developing the feasible solution sets.

[0051] In one embodiment, the solutions for each partition are placed in order of priority and solved one at a time in Develop Solution for Each Partition step 250 . The previous solutions for the partitions are then used to develop solutions for subsequent partitions.

[0052] Alternatively, Develop Solution for Each Partition step 250 may be performed in parallel. A parallel approach can identify partitions that do not interact with each other, also referred to as “zero interaction cliques,” for separate simultaneous solution.

Provide Floorplan Design and Constraints

[0053] The constraints for the global routing tool of the present invention are determined by design requirements. Examples of the types of constraints that can be used are listed below.

[0054] Timing Constraints. In at least one embodiment, the maximum path delay allowed for the routed net can be specified, for example, by a user of the global routing tool. In one embodiment, the maximum path delay is specified using the standard delay format. Standard Delay Format (SDF) is set forth in Standard Delay Format Specification, Version 3.0 (May 1995, Open Verilog International), which is incorporated by reference in its entirety. An SDF file is an ASCII text file containing a header section followed by one or more cell entries describing cells of the design. The header section contains information relevant to the entire file, such as the design name, tool used to generate the SDF file, parameters used to identify the design, and operating conditions. Each cell entry identifies part of the design (a “region” or “scope”) and contains data for delays, timing checks, constraints, and the timing environment. For example, the launch time and edge rate at the driver pins of the nets and the required arrival time and edge rate at each sink pin of a net can be specified as timing constraints.

[0055] Noise Constraints. In at least one embodiment, the user can specify nets that should be avoided and the amount of spacing to be allowed between nets. The user can also specify whether a specified percentage of a particular net is to be routed along a power or ground signal.

[0056] Shielding Constraints. In at least one embodiment, the user can specify the shielding requirements of a net while routing. The shielding width, spacing and percentage of the net to be shielded can be specified. For example, 50% of a particular net may need to be shielded, and two tracks can be allocated along 50% of the length of that net to provide the necessary shielding.

[0057] Cell Insertion Constraints. In at least one embodiment, cell insertion constraints can be specified by the user along with the original timing constraints. Limits can be specified for a maximum transition time or maximum delay allowed such that a repeater or latch can be inserted to overcome the limit. For example, in a path from a driver D 1 to a sink S 1 , a repeater R 1 can be inserted between D 1 and S 1 such that there is a topological breakpoint in the path from D 1 to S 1 . The path from D 1 to S 1 includes two sub-paths: a sub-path from D 1 to R 1 and a sub-path from R 1 to S 1 . In such a case, noise constraints must be considered independently for the sub-path from D 1 to R 1 and the sub-path from R 1 to S 1 .

[0058] FIGS. 3 a and 3 b show constraints that are taken into account by the global routing tool of the present invention. For example, to avoid noise between nets, a minimum spacing between nets can be established to ensure that no noise is transferred generally or to one or more specific nets, as shown in FIG. 3 a . Furthermore, a given net, such as Net A 320 , may need to be routed outside a given width of an adjacent power or ground rail, referred to as “shielding,” for inductance prevention.

[0059] FIG. 3 b shows a circuit resulting from the insertion of repeater cell R 1 into a path from driver D ₁ to sink S ₁ . The original path from driver D ₁ to sink S ₁ is divided into two portions, A and A′. For example, a cell may be inserted to speed up timing to achieve a certain rise time to drive capacitance. The added cell R 1 must be routed around during the routing process.

3D Graph Creation

[0060] To create a three-dimensional graph of the design, the entire design area is divided into a grid, and each grid section is assigned a “gtile.” Gtiles are usually square and one node, also referred to herein as a gNode, of a gtile exists in a given area per layer.

[0061] FIG. 4 a is a diagram of a single metal layer of an integrated circuit design divided into gNodes. Five gNodes labeled g 1 - 2 , g- 2 , g- 3 , g- 4 and g- 5 are shown. A given gNode, such as gNode g 1 - 2 , is considered to be connected to each of its neighbors. GNode g 1 - 2 is connected to each of neighbors g- 2 through g- 5 .

[0062] FIG. 4 b shows three layers of an integrated circuit design and relationships between gNodes in the three layers. The five gNodes of FIG. 4 a are shown as part of metal layer M 2 in FIG. 4 b . In addition, FIG. 4 b shows gNode g 1 - 1 in metal layer M 1 and gNode g 1 - 3 in metal layer M 3 . A collection of gNodes in a vertical relationship between metal layers of the circuit is referred to herein as a “gtile,” and the shaded portions of FIG. 4 b correspond to a gtile g- 1 . Each gtile has a gNode for each of its metal layers; for example, gtile g- 1 includes gNode 1 - 1 in metal layer M 1 , gNode 1 - 2 in metal layer M 2 , and gNode 1 - 3 in metal layer M 3 . All the gNodes of a gtile are connected to each other by a neighbor relationship.

[0063] In the three-dimensional graph shown in FIG. 4 b , vertical neighbors are gNodes of the same gtile, and horizontal neighbors are gNodes of the same metal layer but adjoining gtiles. The graph is referred to herein as a global routing graph or gGraph. A gNode has a maximum of six neighbors, four horizontal neighbors and two vertical neighbors.

[0064] 3D Graph Creation step 210 also adds obstructions, which may be of various rectilinear shapes, into the design that must be routed around in forming interconnections between circuit components. These obstructions may represent power grids, blocks, and charge pumps. The three-dimensional graph enables modeling of congestion of the interconnect lines between connectors, taking into account these obstructions.

Develop Feasible Solution Set for Each Net

[0065] For each gtile, the number of routing tracks available through the gtile is calculated. The calculation takes into account previously routed nets and design-wide obstructions. If a neighbor is obstructed completely, no connection to that neighbor is made in the final circuit design. Pins from the netlist, if located in a certain gNode, are attached to that particular gNode. If a net will require more than one track to be routed on a particular metal layer, the number of tracks is taken into account when routing the net.

[0066] The global route for a net is defined by mapping the net onto a set of gtiles. The present invention is used to produce a unique gtile map, together with width and spacing, for the nets such that all the global and individual net constraints are met.

[0067] As earlier described with regard to FIG. 1, a floor planning module places circuit blocks of the design into sections. The floor planning module also identifies where the drivers and sinks are located by gNode. A global router identifies through which of the sections the gNodes and sinks will be connected; in other words, the global router develops a map at a coarse level. A detailed router uses information about the number of tracks for each metal layer to assign a track for each gNode through which the net must be routed (as determined by the global router). In some embodiments, the floor planning module is a third-party module provided by a vendor independent of the global routing tool vendor, and in other embodiments, the floor planning module can be a component of the global routing tool provided by the same vendor.

[0068] FIG. 5 shows an example of a floorplan that is output from the floor planning component This example floorplan includes two paths having multiple nodes of two metal layers. A first path includes a driver D ₁ and a sink S ₁ as pins in metal layer 3 . A second path includes driver D ₂ and a sink S _2b as pins in metal layer 2 , and sink S _2a in metal layer 3 . Obstruction O ₁ appears in metal layer 2 and obstruction O ₂ appears in metal layer 3 .

[0069] An obstruction, such as obstruction O ₁ or O ₂ , indicates that tracks in the gtile map are “removed,” or considered to be unavailable, such that a net should not be routed through the corresponding gNode of the gtile. As mentioned earlier, examples of obstructions include power grids, blocks, and charge pumps. The present invention allows for obstructions in the form of any rectilinear shape.

[0070] FIG. 6 shows an example of a rectilinear obstruction 610 that can be routed around when using the global routing tool of the present invention. Unlike currently available global routing tools, the present invention enables obstructions of any rectilinear shape to be routed around, including obstructions having diagonal lines such as obstruction 610 .

[0071] FIG. 7 a shows an example of a gNode map for a given metal layer. The gtile map is produced by the global routing tool of the present invention. Ultimately, the global routing tool produces a unique gtile map for each net that meets all constraints and for which routing is both feasible and minimal. The width of the net is taken into account for global routing purposes.

[0072] FIG. 7 a shows a solution for a route between driver D ₁ and sink S ₁ of the gtile map shown in FIG. 5 . The route begins at driver D ₁ in row 3 column 1 of the gtile map and proceeds to row 3 column 2 . The route then proceeds from row 3 column 2 to row 2 column 2 . The route then proceeds through row 2 column 3 to row 2 column 4 , which includes sink S ₁ .

[0073] As mentioned above, an obstruction, such as obstruction 702 , indicates that tracks in the gtile map are “removed,” or considered to be unavailable, such that a net should not be routed through the corresponding gNode of the gtile. Any route excluding row 4 , column 4 , which contains obstruction 702 , can be taken between driver D ₁ and sink S ₁ .

[0074] In creating a feasible solution set for a net, each route placed into the solution set should be feasible and meet applicable constraints. If no solutions exist for routing the net, a design flaw exists and the floorplan must be changed. If one solution exists, that solution corresponds to the solution set. If several solutions exist, a subset of the solutions can be selected to form the solution set; for example, a maximum of three solutions may be selected to form the solution set based on, for example, metrics for timing quality and length.

[0075] In FIG. 7 b , driver D ₂ of FIG. 5 is shown, with two sinks S _2a and S _2b . A solution for a route between D ₂ and S _2a is determined independently of the solution for a route between D ₂ and S _2b . Three solutions are illustrated for the path from D ₂ to S _2a , respectively labeled S _2a ( 1 ), S _2a ( 2 ) and S _2a ( 3 ). Similarly, three solutions are illustrated for the path from D ₂ to S _2b , respectively labeled S _2b ( 1 ), S _2b ( 2 ) and S _2b ( 3 ). These solutions are then combined to provide the following 9 possible solutions for nets including D ₂ , S _2a and S _2b : 1

[0076] A set of global route solutions for each net is generated. In one embodiment, Mikami Line Search Algorithm is used for finding these solutions. For more information regarding Mikami Line Search algorithm, see K. Mikami & K. Tabuchi, A Computer Program for Optimal Routing of Printed Circuit Connectors , IFIPS Proceedings, H47:1475-1478, 1968, which is incorporated herein by reference.

[0077] The Mikami Line Search algorithm searches across obstacles and multiple metal layers to find routing paths. For each net, each of its sink pins is paired with the driver pin to form (driver, sink) pairs for each path. Each path is routed using the Mikami Algorithm and multiple solutions are generated per path. After all solutions have been found for each (driver, sink) pair, the solutions are merged to give solutions for the entire net. For example, if a net had two paths, then two (driver, sink) pairs are formed. If the search algorithm generated three possible solutions for the first pair and two possible solutions for the second pair, then six global route solutions are possible for the net. The delay and actual length for each path solution is computed and stored for further analysis in the routing process.

[0078] Mikami Tabuchi algorithm, a line probe algorithm, is designed to perform better than maze routing algorithms, both in terms of route search time and quality. Maze routing algorithms search grid nodes in a breadth-first fashion, whereas a line probe algorithm searches line segments available within the three-dimensional gmap. The time and space complexity of Mikami Tabuchi algorithm is O(L), where L is the number of line segments produced to complete the route search. Mikami Tabuchi algorithm finds a path between driver and sink, if such a path exists, and assures that the path found is the shortest path available on the given floorplan. Initially, the line probes are drawn from both driver and sink in mutually perpendicular directions. These lines extend until reaching the floorplan boundary or an obstacle on that metal layer. If these lines do not intersect, then at each grid point on these lines, perpendicular lines are drawn until they reach the boundary of the floorplan or hit an obstacle. This process is continued recursively until an intersection point is found between the list of lines belonging to the driver and sink.

[0079] To enable multi-layer routing, the lines drawn from points on a previous line can be on multiple layers, thereby reducing the overall search time. In practice, new lines are not drawn from every grid point on the previous line. A spacing factor between grid points is used to reduce the exponential growth in number of lines generated during a complicated search.

[0080] More sophisticated algorithms, such as Steiner Tree-based approaches, can be used to determine routes more suitable for multi-terminal nets. For more information about Steiner trees, see C. Chieng, M. Sarrafzadeh & C. K. Wong, A Powerful Global Router Based on Steiner Min-Max Trees , Proceedings of IEEE International Conference on Computer-Aided Design, pp. 2-5, Nov. 7-10, 1989, which is herein incorporated by reference.

[0081] Steiner Tree-based approaches are based on first finding the minimum spanning tree for the given set of pins on a net. A minimum spanning tree is a minimum-weight tree in a weighted graph which contains all of the graph's vertices (here, all the pins). From the minimal spanning tree, a rectilinear Steiner Tree is produced. A Steiner Tree is a tree resulting when, given a set of vertices S in an undirected weighted graph, a minimal weight spanning tree of S∪Q is produced for some added Steiner vertices Q in the graph. A Steiner tree differs from the minimum spanning tree in that the set of Steiner vertices must be identified. That is, additional vertices may be used. A Steiner Tree is based on rectilinear projections of the edges of this minimum spanning tree.

[0082] Once a set of solutions for each net is produced, the solutions for each net can be pruned according to delay and length constraints. In one embodiment, Elmore Delay is computed for each path of the net. For more information about Elmore Delay, see W. C. Elmore, The Transient Analysis ofDamped Linear Networks with Particular Regard to Wideband Amplifiers , Journal of Applied Physics, vol. 19(1), 1948; and J. Rubenstein, P. Penfield, Jr., & M. A. Horowitz, Signal Delay in RC Tree Networks, IEEE Transactions On Computer Aided Design, CAD-2:202-211, 1983, each of which is incorporated herein by reference.

[0083] The Elmore Delay model is the most commonly used delay model in works on interconnect design when inductance and distributed resistance and capacitance (RC) effects don't dominate. Under the Elmore delay model, the signal delay from the driver s 0 to a given node i in an RC tree is calculated as follows:

t ( s 0 , i )=Sum_over_all_nodes _— k ( R ( k _i )* C ( k ))

[0084] where

[0085] C(k) is the downstream capacitance from node i

[0086] R(k ₁ ) is the resistance at node i

[0087] All nodes and sinks in the RC tree have a different delay. In general, the Elmore delay of a sink in an RC tree is a (loose) upper bound on the actual 50% delay of the sink under step input.

[0088] Elmore delay provides a simple closed-form expression with greatly improved accuracy for measuring delay, when compared to other RC models. Furthermore, the Elmore delay calculation can be done in linear time. The Elmore delay model is not the most accurate delay model available, but the Elmore delay model has a high degree of fidelity: an optimal or near-optimal solution according to the estimator is also nearly optimal actual delay for routing constructions and wire-sizing optimization. Other delay models which are more accurate can be used, but run-time for these models is usually greater than that of the Elmore delay model.

[0089] Using the arrival time constraints, the delay violation for each path solution is computed using the following formula:

Delay Violation=Actual Delay−Arrival Time Constraint

[0090] A value of 0 for the delay violation indicates that the arrival time constraint is met. A positive value indicates that the arrival time constraint is not met, and a negative value means that slack is available for optimization of other nets. The net solutions where all the paths of the net meet the constraint (delay) are retained, and the rest of the solutions are omitted from further consideration for inclusion in the final global routing solution. This “pruning” of the solutions guarantees that the ultimate global routing solution meets the timing constraint.

[0091] In one embodiment, feasible solutions sets are determined in order of priority. Consider a design having twenty nets. When the solution for the first net is developed, multiple solutions are available. After the first ten nets' solutions are developed, available tracks for routing the eleventh net are limited. Assume that the eleventh net interacts with eight other nets, four of which have already been routed as part of the first ten nets. Noise should be avoided between the interacting nets, and the topology of the previously routed nets can be considered to be an obstruction for the route of the eleventh net.

[0092] In the example, assume that the eleventh net needs to be a distance of four tracks from the previously routed tenth net. A temporary obstruction can be constructed determined by the topology of the tenth net. The eleventh net can be routed to automatically avoid the temporary obstruction. When the routing for the eleventh net is complete, the temporary obstruction can be removed for routing of subsequent nets. This approach of routing nets in order of priority and using temporary obstructions enables spacing constraints and noise to be taken into account.

[0093] FIG. 8 shows an example of a design including three drivers and three sinks in a single metal layer. The method of the present invention will be applied to the example design of FIG. 8 in the following sections.

[0094] FIG. 8 includes three nets: N 1 , beginning at driver D ₁₁ and ending at sink S ₁₁ ; N 2 , beginning at driver D ₂₁ ; and ending at sink S ₂₁ ; and N 3 beginning at driver D ₃₁ and ending at sink S ₃₁ . Three obstructions 810 , 820 and 830 are also present. Note that tracks are free in rows 6 and 8 and columns 7 and 8 such that paths can be routed through the gNodes of rows 6 and 8 and columns 7 and 8 despite obstructions 810 and 830 . Obstruction 820 completely obstructs column 6 rows 2 - 7 and row 7 columns 2 - 6 , and no path can be routed in column 6 rows 2 - 7 or row 7 columns 2 - 6 . Taking these obstructions into account, feasible paths can be identified using algorithms such as those described above.

[0095] For net N 1 , three possible paths include path t ₁₁ (also referred to as topology ₁₁ ), t ₁₂ and t ₁₃ . For net N 2 , two possible paths include t ₂₁ and t ₂₂ . For net N 3 , two possible paths include paths t ₃₁ and t ₃₂ . Note that paths t ₁₁ , t ₁₂ and t ₁₃ meet at sink S ₁₁ . For the design to include all three paths, a separate track must be available for each path.

[0096] The result of steps Create 3D Graph step 210 and Develop Feasible Solution for Each Net step 220 of FIG. 2 is summarized below.

[0097] 3 nets: N 1 , N 2 and N 3

[0098] Number of solutions for each net: N 1 has 3, N 2 has 2, N 3 has 2.

Create Intersection Graph with Weights

[0099] In Create Intersection Graph with Weights step 230 of FIG. 2 , finding a best solution from one point to another can be performed using known techniques. In most global routing tools, a single best solution is considered for each net. Using the best solution for each net, the netlist is updated and a new net is identified from the set of solutions including only one best solution for each net.

[0100] In contrast, the present invention considers a set of solutions, rather than the single best solution, for each net. Each solution for a given net is determined independently of other nets that do not have noise interaction with the given net. As an initial condition, the set of feasible solutions is constrained by the total number of tracks available in view of obstructions, but not by other feasible solutions for other nets that may need to use those tracks. The best set of feasible solutions is determined to include only solutions that are feasible for the entire set of nets.

[0101] Based on these sets of solutions for each net, an intersection graph for the entire netlist is created. Each net is represented as an intersection graph node. If the gNodes forming the solutions intersect with solutions of another net, an undirected edge is formed between the two intersection graph nodes. These edges are weighted based on the interactions between the intersection graph nodes. In order to distinguish the nodes of gmap from intersection graph nodes, the term “gNode” or “node” is used for gmap nodes, and the term “intersection graph node” is used for the nodes of the intersection graph.

[0102] FIG. 9 shows an example of an intersection graph in which nets N 1 , N 2 and N 3 of FIG. 8 are included. An edge is placed between intersection graph nodes of the intersection graph N 1 and N 2 because nets N 1 and N 2 share the gNodes including driver D ₂₁ and sink S ₁₁ , as well as the gNodes in row 6 columns 3 and 4 and colunm 5 rows 1 through 6 . An edge is placed between nodes of the intersection graph N 1 and N 3 because nets N 1 and N 3 share the gNodes including driver D ₁₁ and D ₃₁ , as well as the gNodes including column 1 rows 1 through 6 and row 1 columns 1 through 4 . sink S ₁₁ . An edge is placed between nodes of the intersection graph N 2 and N 3 because nets N 2 and N 3 share the gNodes including row 8 columns 1 through 7 .

[0103] In one embodiment, the edges are weighted by the percentage of solutions of two nets that intersect and the average probable congestion over intersecting gNodes. For example, the weight on the edge between two nodes (representing 2 different nets in the design) can be a function of the number of intersecting solutions and congestion, as shown in the formula below: 1 $=y*\left(A_{\mathrm{NaNb}}\right)+\left(1-y\right)*B_{\mathrm{NaNb}}$

[0104] where

A _NaNb (representing Intersecting Solutions)=(#solutions intersecting between N _a & N _b )*(Avg. over all intersecting pairs of the % of gNodes intersecting)

B _NaNb (representing Congestion)=(#nodesSharedAndCongested/#nodesShared between all solutions for N _a & N _b )*Average Congestion on nodesSharedAndCongested

[0105] 2 $\mathrm{where}\mathrm{congestion}=\left(\frac{\#\mathrm{tracks}\mathrm{used}}{\#\mathrm{tracks}\mathrm{Available}}\right)$

[0106] Assume that one or more obstructions in a particular gNode of the grnap of FIG. 8 consume all but one track running through each gNode including the obstructions. Therefore, a gNode of FIG. 8 including one or more obstructions has only one track available for routing.

[0107] Typically, a path running through a gNode needs one track. However, a path may be wider, requiring two or more tracks, for example, to avoid noise. A gNode is considered to be congested when the value of congestion, as calculated above, is greater than one. Therefore, when a given gNode of FIG. 8 has one or more obstructions and more than one path is routed through the given gNode, the given gNode is considered to be congested.

[0108] Using the percentage of solutions of two nets that intersect and the average probable congestion over intersecting gNodes, a single weight for each edge is determined. Calculations of weights for the intersection graph of FIG. 9 , representing the design shown in FIG. 8 , are shown below.

[0109] Referring to FIG. 8 and the paths for nets N 1 and N 2 , all three paths for net N 1 intersect with path t ₂₁ from net N 2 . For example, path t ₁₁ , having a length of ten gNodes, intersects with path t ₂₁ , having a length of 19 gNodes. The intersection shares the six gNodes in column 5 rows 1 through 6 . The percentage of gNodes intersecting between path t ₁₁ and path t ₂₁ is calculated below: 3 $\left(t_{11}\mathrm{with}t_{21}\right)=\frac{1}{2}*\left(\frac{6}{10}+\frac{6}{19}\right)=0.46$

[0110] Similarly, path t ₁₂ , having a length of ten gNodes, intersects with path t ₂₁ , having a length of 19 gNodes, with the intersection including the three gNodes in column 5 rows 4 through 6 . The percentage of gNodes intersecting between path t ₁₂ and path t ₂₁ is calculated below: 4 $\left(t_{12}\mathrm{with}t_{21}\right)=\frac{1}{2}*\left(\frac{3}{10}+\frac{3}{19}\right)=0.23$

[0111] Path t ₁₃ , having a length of ten gNodes, intersects with path t ₂₁ , having a length of 19 gNodes, with the intersection including the five gNodes in row 6 columns 1 through 5 . The percentage of gNodes intersecting between path t ₁₃ and path t ₂₁ is calculated below: 5 $\left(t_{13}\mathrm{with}t_{21}\right)=\frac{1}{2}*\left(\frac{5}{10}+\frac{5}{19}\right)=0.38$

[0112] Using these calculations, the average over the three intersecting pairs of the percentage of gNodes intersecting is calculated below: 6 $\frac{1}{3}\left[0.46+0.23+0.38\right]=0.36$

[0113] This average is used as part of the formula for A _NaNb , representing intersecting solutions, to assign weights to the edges between the nodes of the graph of FIG. 9 . The weight assigned to the edge between nets N 1 and N 2 is calculated as shown below:

w ₁ ( N 1 ⇄ N 2 )= y*A _N1N2 +(1 −y )* B _N1N2

A _N1N2 =number of solution pairs intersecting*Avg. over all intersecting pairs of the percentage of gNodes intersecting 3*(0.36)=1.08

[0114] In the formula for A _N1N2 , representing congestion, the number of congested gNodes is used as part of the calculation. Recall that when a gNode has one or more obstructions, the obstructions are considered to occupy all but one track running through the corresponding gNode. As a result, gNodes with two paths and one or more obstructions in FIG. 8 are congested, including the gNodes in column 5 , rows 2 through 6 ; row 6 , columns 2 through 5 ; and row 8 , columns 2 through 6 .

B _NaNb (representing Congestion)=(#nodesSharedAndCongested/#gnodesShared between all solutions for N _a & N _b )*Average Congestion on nodesSharedAndCongested

[0115] 7 $\mathrm{where}\mathrm{congestion}=\left(\frac{\#\mathrm{tracks}\mathrm{used}}{\#\mathrm{tracks}\mathrm{Available}}\right)$

[0116] Ten gNodes are shared between nets N 1 and N 2 , including the six gNodes in column 5 , rows 1 through 6 , and the four gNnodes in row 6 , columns 1 through 4 . (Note that the gNode of row 6 , column 5 , was already counted in the five gNodes for column 5 .) Of the ten gNodes shared by nets N 1 and N 2 , the five gNodes of column 5 , rows 2 through 6 , are congested. Each of the five congested gNodes has a value for congestion=2 tracks used/1 track available=2. The average congestion for gNodes shared and congestion is therefore (5*2)/5=2.

[0117] Therefore, A _N1N2 is calculated as shown below: 8 $\frac{5}{10}*\left(\left(5*2\right)/5\right)=1.0$

[0118] Using this result, the weight for the intersection graph edge between N 1 and N 2 is calculated as shown below: 9 $\begin{array}{c}{w}_1\left({\mathrm{N1}}_1\leftrightarrow \mathrm{N2}\right)=y*A_{\mathrm{N1N2}}+\left(1-y\right)B_{\mathrm{N1N2}}\\ \begin{array}{c}{w}_1\left({\mathrm{N1}}_1\leftrightarrow \mathrm{N2}\right)=\left(y=\mathrm{.4}\right)*\left(A_{\mathrm{N1N2}}=1.08\right)+\\ \left(\left(1-y\right)=\mathrm{.6}\right)*\left(B_{\mathrm{N1N2}}=1.0\right)\\ =\mathrm{.4}*1.08+\mathrm{.6}\end{array}\\ w_1\left(\mathrm{N1}\leftrightarrow \mathrm{N2}\right)=1.032\end{array}$

[0119] As shown in FIG. 10 , the weight of the edge between nets N 1 and N 2 has a value of 1.032.

[0120] To calculate the weight for the edge between nets N 1 and N 3 , the calculations below are used:

w ₂ ( N 1 ₁ ⇄N 3 )= y*A _N1N3 +(1 −y )* B _N1N3

[0121] Between nets N 1 and N 3 , path t ₃₁ intersects with path t ₁₁ at the five gNodes in row 1 columns 1 through 5 . Path t ₃₁ has fifteen gNodes, and path t ₁₁ has ten gNodes. 10 $\left(t_{31}\mathrm{with}t_{11}\right)=\frac{1}{2}\left(\frac{5}{15}+\frac{5}{10}\right)=0.42$

[0122] Between nets N 1 and N 3 , path t ₃₂ intersects with path t ₁₂ at the four nodes in column 1 rows 1 - 4 . Path t ₃₂ has fifteen gNodes, and path t ₁₂ has ten gNodes. 11 $\left(t_{32}\mathrm{with}t_{12}\right)=\frac{1}{2}\left(\frac{4}{15}+\frac{4}{10}\right)=0.33$

[0123] Between nets N 1 and N 3 , path t ₃₂ intersects with path t ₁₃ at the six gNodes in column 1 rows 1 - 6 . Path t ₃₂ has fifteen gNodes, and path t ₁₃ has ten gNodes. 12 $\left(t_{32}\mathrm{with}t_{13}\right)=\frac{1}{2}(\frac{6}{15}+\frac{6}{}$