BACKGROUND OF THE INVENTION

[0001] The present invention relates to the characterization of transient behavior of digital signals.

[0002] Characterizing the transient behavior of digital signals, i.e. the transition from logical zero to logical one, and vice versa, has become increasing important for designing as well as manufacturing such digital circuits, and is disclosed e.g. in the European Patent application No. 01106632.1, the teaching thereof shall be incorporated herein be reference. For testing a device under test (DUT), usually one or multiple stimulus signals are applied to the DUT and one or multiple response signals onto the stimulus signals are detected and analyzed (e.g. by comparing the detected response signal with an expected response signal).

[0003] A standard characterization of digital circuits requires determining the so-called Bit Error Rate (BER), i.e. the ratio of erroneous digital signals (Bits) to the total number of regarded digital signals. Bit Error Rate Testers (BERTs), such as the Agilent® 81250 ParBERT Platform with and Agilent® E4875A User Software and Measurement Software both by the applicant Agilent Technologies, are provided to determine a so-called BER eye diagram as a two-dimensional graphical representation generated using a sweep over delay and threshold of an analyzer. The result is an eye pattern with a BER value dependent on the sampling point for a plurality of sampling points.

[0004] Each sampling point is determined by a relative (e.g. delay) time with respect to corresponding transition of a clock signal (usually the system clock for generating the stimulus signals or a clock signal derived therefrom or from the response signal) and a threshold value for comparing the response signal with.

[0005] The maximum number of sampling points is usually dependent on the resolution of the analyzer. In order to decrease measurement time, the number of sampling points is usually kept as low as possible. The BER eye diagram gives information which BER value can be expected depending on the position of the sampling point within the eye. Parameters like jitter, level noise, phase margin, and quality factor (Q-factor) can be calculated from the BER eye diagram.

SUMMARY OF THE INVENTION

[0006] It is an object of the present invention to provide an improved transient testing. The object is solved by the independent claims. Preferred embodiments are shown by the dependent claims.

[0007] According to the present invention, a signal-analyzing unit for analyzing a digital test signal (as provided e.g. from a DUT) comprises a sampling path and a reference path, both receiving the test signal, and an analysis unit adapted for receiving and jointly analyzing the output of both of the sampling and reference path.

[0008] The sampling path comprises a first comparator for comparing the test signal against a first threshold value (e.g. a threshold voltage) and providing a first comparison signal as result of the comparison. A first sampling device receives as input the first comparison signal together with a first timing signal comprising a plurality of successive first timing marks. The first sampling device is adapted to derive a value of the first comparison signal for one or more (and preferably each) of the first timing marks. The sampling device provides as an output a first sampling signal representing the derived value(s) of the first comparison signal over or in relation to the respective first timing mark(s).

[0009] The reference path comprises a second comparator for comparing the test signal against a second threshold value (e.g. a threshold voltage) and providing a second comparison signal as result of the comparison. A second sampling device receives as input the second comparison signal together with a second timing signal comprising a plurality of successive second timing marks. The second sampling device is adapted to derive a value of the second comparison signal for one or more (and preferably each) of the second timing marks. The sampling device provides as an output a second sampling signal representing the derived value(s) of the second comparison signal over or in relation to the respective second timing mark(s).

[0010] The first and the second timing signals are provided having a defined relationship to each other, so that there also is a defined relationship between corresponding ones of the first and second timing marks. Preferably, the first and the second timing signals are both derived from a (common) clock signal. One or more appropriate timing units might be provided for generating the respective timing signal(s) comprising the timing marks from the clock signal.

[0011] The analysis unit receives the first and second sampling signals from the first and the second sampling devices as well as the first and second timing signals. The analysis unit provides a joint analysis of the outputs from the first and second sampling signals, thereby using knowledge about the respective first and second timing signals together with the first and second threshold values.

[0012] In one embodiment, the second threshold voltage together with the second timing signal are provided in order to derive a secure detection (i.e. to minimize measuring uncertainty) of respective states in the test signal. Preferably, the second threshold voltage and the second timing signal are provided to sample the test signal substantially in the middle of an eye diagram derived for the test signal. Preferably, the second threshold voltage is selected to be substantially half of the difference in voltage between a high and a low state of the test signal. Preferably, the timing marks in the second timing signal are provided to be substantially in the middle between two transitions of the same direction (either a rising or a falling edge) of the second timing signal. Preferably, the timing marks of the second timing signal are delayed by half a period of a signal clock associated with the test signal with respect to either the rising or falling edges of at least one of the signal clock or the test signal.

[0013] While the sampling of the reference path is preferably provided to achieve a secure detection of states in the test signal, the sampling points in the sampling path are preferably varied in order to fully or partly analyzed the behavior of the test signal.

[0014] In one embodiment, each of the first and the second comparators compares the test signal against a respective threshold value (the first or the second threshold value) and provides as comparison signal a first value in case the test signal is greater than the threshold value and a second value in case the test signal is smaller than the threshold value.

[0015] In one embodiment, only one comparator is provided instead of the first and the second comparators. The one comparator receives as input the test signal and compares the test signal against one threshold value and provides a comparison signal therefrom. The comparison signal is then provided as input to the sampling device as well as to the phase control unit. Providing two independent comparators and threshold values, however, allows to independently varying the respective threshold values. This might be of advantage in order to safely derive the second sampling signal from the test signal, while still allowing the sampling device to sample at each possible threshold value (as determined by the first threshold value together with the first comparator).

[0016] In one embodiment, the analysis unit uses the output of the reference path for comparing it with the output of the sampling path. The comparison can be made directly or indirectly. In the former case (direct comparison), corresponding samples determined by the first and second sampling devices are directly compared with each other. In other words, the output of the reference path is regarded as representing the expected response signal while the output of the first sampling device represents the detected response signal. A deviation in the corresponding samples indicates an error. Corresponding samples means that both samples are detected within one period of the signal clock. Preferably, the analysis unit compares the first and second sampling signals for corresponding sampling points.

[0017] In the latter case (i.e. indirect comparison) the analysis unit has knowledge about the expected response signal in principle, however, permitted deviations and variations in the expected response signal might occur e.g. resulting from data protocols like 10-Gigabit-Ethernet (10 GbE) or XAUI. For example, a protocol might allow inserting an unknown number of idle cells between data words resulting e.g. from small frequency differences between the inputs and the outputs of such a device. If the output data rate exceeds the input data rate, the device will insert idle cells in order to adjust for that difference. If the output data rate is smaller than the input data rate it will remove idle cells. Further, scrambling might be used to remove long runs of equal bits in data stream. The start phase of a scrambler influences the scrambled data stream, and as it is often unknown the scrambled data content cannot be predetermined. That means, that a course of the expected response signal can only be known in principle, but some variations are allowed. Without considering such “allowed variations” actual response signals, which are compliant with such protocol and without showing bit errors, might be tested to contain errors since the “static” expected response signal (i.e. without consideration of the permitted variations) and the actual expected response signal do not coincide.

[0018] In such case of indirect comparison, the output of the second sampling device is used to generate the expected response signal from the expected response signal known in principle in combination with the output of the second sampling device. This can be achieved e.g. by detecting patterns of the output of the second sampling device in the expected response signal known in principle. Thus, e.g. idle cells can be detected and the actually expected response signal can be generated.

[0019] In an embodiment, the data stream is decoded or de-scrambled and afterwards the position and type of control characters or idle cells is detected. These control characters and idle cells are then inserted into the raw expected data signal. Afterwards the coding or scrambling is performed with the start phase of the scrambler being detected in the received data stream.

[0020] In one embodiment, the signal-analyzing unit further comprises a clock recovery unit also receiving the test signal. The clock recovery unit receives the test signal and derives therefrom a generated clock signal. The generated clock signal might further be provided to the one or more timing unit(s) for generating the timing signal comprising the timing marks (as applied by the sampling devices). The clock recovery unit can preferably be embodied as disclosed in the European Patent Application No. 02016599.9, the teaching thereof shall be incorporated herein by reference.

[0021] In one embodiment, the clock recovery unit comprises a third comparator for comparing the test signal against a third threshold value and for providing a third comparison signal as result of the comparison. However, instead of the third comparator, the clock recovery unit might also receive the second comparison signal from the second comparator.

[0022] In one embodiment, the clock recovery unit further comprises a clock generator and a phase control unit. The clock generator generates the clock signal having substantially the same frequency as a signal clock associated with the test signal. In a further embodiment, wherein the clock generator is tunable in frequency, the clock recovery unit further comprises a frequency correction unit for substantially adjusting the frequency of the clock generator to the frequency of the signal clock.

[0023] The phase control unit receives the respective comparison signal (from the second or third comparator) as well as the clock signal (generated by the clock generator) and determines a difference in the phases there-between. The phase control unit controls the clock generator in order to minimize deviations in phase between the generated clock signal and the comparison signal. In another embodiment, the clock signal is derived by converting the second comparison signal into a return-to-zero (RZ) signal and feeding this signal to a filter (preferably band-pass or notch filter) to extract the clock signal. Other schemes as known in the art for deriving the clock signal from the test signal can be applied accordingly.

[0024] The generated clock signal is preferably further provided as the clock signal to the timing unit for generating the timing marks. Each timing unit preferably derives the timing marks from transitions in the clock signal (preferably from either one of a rising or falling edges). Each timing unit might preferably further allow modifying the timing marks with respect to corresponding transitions in the clock signal. Preferably, the timing marks can be delayed with respect to corresponding transitions. This can be achieved e.g. by a phase shift or delay unit receiving the clock signal and being adapted to (preferably variably) shift the phase of the clock signal and provide the phase shifted clock signal to the sampling device. This allows delaying the timing marks with respect to the transitions of the clock signal.

[0025] Instead of using the clock recovery another clock source having substantially the same frequency as the test signal can be used, e.g. the user can apply an externally generated clock, e.g. the clock used to drive the DUT.

[0026] It is clear that the digital test signal may also be a differential signal. In that case preferably a level-shifting unit as disclosed in the European Patent application No. 02015432.4 is applied. The teaching of that document, in particular with respect to the level-shifting unit, shall be incorporated herein by reference.

[0027] The invention can be partly or entirely embodied or supported by one or more suitable software programs, which can be stored on or otherwise provided by any kind of data carrier, and which might be executed in or by any suitable data processing unit.