DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0039] A transceiver 100 based on the present invention is shown in FIGS. 2 and 3 . The transceiver 100 contains a Receiver Optical Subassembly (ROSA) 102 and Transmitter Optical Subassembly (TOSA) 103 along with associated post-amplifier 104 and laser driver 105 integrated circuits that communicate the high speed electrical signals to the outside world. In this case, however, all other control and setup functions are implemented with a third single-chip integrated circuit 110 called the controller IC.

[0040] The controller IC 110 handles all low speed communications with the end user. These include the standardized pin functions such as Loss of Received Signal (LOS) 111 , Transmitter Fault Indication (TX FAULT) 14 , and the Transmitter Disable Input (TXDIS) 13 . The controller IC 110 has a two wire serial interface 121 , also called the memory interface, for accessing memory mapped locations in the controller. Memory Map Tables 1, 2, 3 and 4, below, are an exemplary memory map for one embodiment of a transceiver controller, as implemented in one embodiment of the present invention. It is noted that Memory Map Tables 1, 2, 3 and 4, in addition to showing a memory map of values and control features described in this document, also show a number of parameters and control mechanisms that are outside the scope of this document and thus are not part of the present invention.

[0041] The interface 121 is coupled to host device interface input/output lines, typically clock (SCL) and data (SDA) lines, 15 and 16 . In the preferred embodiment, the serial interface 121 operates in accordance with the two wire serial interface standard that is also used in the GBIC and SFP standards, however other serial interfaces could equally well be used in alternative embodiments. The two wire serial interface 121 is used for all setup and querying of the controller IC 110 , and enables access to the optoelectronic transceiver's control circuitry as a memory mapped device. That is, tables and parameters are set up by writing values to predefined memory locations of one or more nonvolatile memory devices 120 , 122 , 128 (e.g., EEPROM devices) in the controller, whereas diagnostic and other output and status values are output by reading predetermined memory locations of the same nonvolatile memory devices 120 , 121 , 122 . This technique is consistent with currently defined serial ID functionality of many transceivers where a two wire serial interface is used to read out identification and capability data stored in EEPROM.

[0042] It is noted here that some of the memory locations in the memory devices 120 , 122 , 128 are dual ported, or even triple ported in some instances. That is, while these memory mapped locations can be read and in some cases written via the serial interface 121 , they are also directly accessed by other circuitry in the controller 110 . For instance, certain “margining” values stored in memory 120 are read and used directly by logic 134 to adjust (i.e., scale upwards or downwards) drive level signals being sent to the D/A output devices 123 . Similarly, there are flags stored memory 128 that are (A) written by logic circuit 131 , and (B) read directly by logic circuit 133 . An example of a memory mapped location not in memory devices but that is effectively dual ported is the output or result register of clock 132 . In this case the accumulated time value in the register is readable via the serial interface 121 , but is written by circuitry in the clock circuit 132 .

[0043] In addition to the result register of the clock 132 , other memory mapped locations in the controller may be implemented as registers at the input or output of respective sub-circuits of the controller. For instance, the margining values used to control the operation of logic 134 may be stored in registers in or near logic 134 instead of being stored within memory device 128 . In another example, measurement values generated by the ADC 127 may be stored in registers. The memory interface 121 is configured to enable the memory interface to access each of these registers whenever the memory interface receives a command to access the data stored at the corresponding predefined memory mapped location. In such embodiments, “locations within the memory” include memory mapped registers throughout the controller.

[0044] In an alternative embodiment, the time value in the result register of the clock 132 , or a value corresponding to that time value, is periodically stored in a memory location with the memory 128 (e.g., this may be done once per minute, or one per hour of device operation). In this alternative embodiment, the time value read by the host device via interface 121 is the last time value stored into the memory 128 , as opposed to the current time value in the result register of the clock 132 .

[0045] As shown in FIGS. 2 and 3 , the controller IC 110 has connections to the laser driver 105 and receiver components. These connections serve multiple functions. The controller IC has a multiplicity of D/A converters 123 . In the preferred embodiment the D/A converters are implemented as current sources, but in other embodiments the D/A converters may be implemented using voltage sources, and in yet other embodiments the D/A converters may be implemented using digital potentiometers. In the preferred embodiment, the output signals of the D/A converters are used to control key parameters of the laser driver circuit 105 . In one embodiment, outputs of the D/A converters 123 are use to directly control the laser bias current as well as to control of the level AC modulation to the laser (constant bias operation). In another embodiment, the outputs of the D/A converters 123 of the controller 110 control the level of average output power of the laser driver 105 in addition to the AC modulation level (constant power operation). In yet another embodiment, the outputs of the D/A converters 123 of the controller 110 are used to control the laser bias current as well as to control the biasing of an avalanche photodiode (APD).

[0046] In a preferred embodiment, the controller 110 includes mechanisms to compensate for temperature dependent characteristics of the laser. This is implemented in the controller 110 through the use of temperature lookup tables 122 that are used to assign values to the control outputs as a function of the temperature measured by a temperature sensor 125 within the controller IC 110 . In alternative embodiments, the controller 110 may use D/A converters with voltage source outputs or may even replace one or more of the D/A converters 123 with digital potentiometers to control the characteristics of the laser driver 105 . It should also be noted that while FIG. 2 refers to a system where the laser driver 105 is specifically designed to accept inputs from the controller 110 , it is possible to use the controller IC 110 with many other laser driver ICs to control their output characteristics.

[0047] In addition to temperature dependent analog output controls, the controller IC may be equipped with a multiplicity of temperature independent (one memory set value) analog outputs. These temperature independent outputs serve numerous functions, but one particularly interesting application is as a fine adjustment to other settings of the laser driver 105 or postamp 104 in order to compensate for process induced variations in the characteristics of those devices. One example of this might be the output swing of the receiver postamp 104 . Normally such a parameter would be fixed at design time to a desired value through the use of a set resistor. It often turns out, however, that normal process variations associated with the fabrication of the postamp integrated circuit 104 induce undesirable variations in the resulting output swing with a fixed set resistor. Using the present invention, an analog output of the controller IC 110 , produced by an additional D/A converter 123 , is used to adjust or compensate the output swing setting at manufacturing setup time on a part-by-part basis.

[0048] In addition to the connection from the controller to the laser driver 105 , FIG. 2 shows a number of connections from the laser driver 105 to the controller IC 110 , as well as similar connections from the ROSA 106 and Postamp 104 to the controller IC 110 . These are analog monitoring connections that the controller IC 110 uses to provide diagnostic feedback to the host device via memory mapped locations in the controller IC. The controller IC 110 in the preferred embodiment has a multiplicity of analog inputs. The analog input signals indicate operating conditions of the transceiver and/or receiver circuitry. These analog signals are scanned by a multiplexer 124 and converted using an analog to digital converter (ADC) 127 . The ADC 127 has 12 bit resolution in the preferred embodiment, although ADC's with other resolution levels may be used in other embodiments. The converted values are stored in predefined memory locations, for instance in the diagnostic value and flag storage device 128 shown in FIG. 3 , and are accessible to the host device via memory reads. These values are calibrated to standard units (such as millivolts or microwatts) as part of a factory calibration procedure.

[0049] The digitized quantities stored in memory mapped locations within the controller IC include, but are not limited to, the laser bias current, transmitted laser power, and received power (as measured by the photodiode detector in the ROSA 102 ). In the memory map tables (e.g., Table 1), the measured laser bias current is denoted as parameter B in , the measured transmitted laser power is denoted as P in , and the measured received power is denoted as R in . The memory map tables indicate the memory locations where, in an exemplary implementation, these measured values are stored, and also show where the corresponding limit values, flag values, and configuration values (e.g., for indicating the polarity of the flags) are stored.

[0050] As shown in FIG. 3 , the controller 110 includes a voltage supply sensor 126 . An analog voltage level signal generated by this sensor is converted to a digital voltage level signal by the ADC 127 , and the digital voltage level signal is stored in memory 128 . In a preferred embodiment, the A/D input mux 124 and ADC 127 are controlled by a clock signal so as to automatically, periodically convert the monitored signals into digital signals, and to store those digital values in memory 128 .

[0051] Furthermore, as the digital values are generated, the value comparison logic 131 of the controller compares these values to predefined limit values. The limit values are preferably stored in memory 128 at the factory, but the host device may overwrite the originally programmed limit values with new limit values. Each monitored signal is automatically compared with both a lower limit and upper limit value, resulting in the generation of two limit flag values that are then stored in the diagnostic value and flag storage device 128 . For any monitored signals where there is no meaningful upper or lower limit, the corresponding limit value can be set to a value that will never cause the corresponding flag to be set.

[0052] The limit flags are also sometimes call alarm and warning flags. The host device (or end user) can monitor these flags to determine whether conditions exist that are likely to have caused a transceiver link to fail (alarm flags) or whether conditions exist which predict that a failure is likely to occur soon. Examples of such conditions might be a laser bias current which has fallen to zero, which is indicative of an immediate failure of the transmitter output, or a laser bias current in a constant power mode which exceeds its nominal value by more than 50%, which is an indication of a laser end-of-life condition. Thus, the automatically generated limit flags are useful because they provide a simple pass-fail decision on the transceiver functionality based on internally stored limit values.

[0053] Logic 131 preferably includes a plurality of state machines for executing control functions which require sequences of operations to be performed, such as converting a temperature sensor reading into an index value, and delivering that index value to the temperature lookup tables 122 using a connection not shown in FIG. 3 . The analog to digital conversions by ADC 127 , the comparison of signals with limit values and the generation of limit flags are also handled in part by state machines within the logic 131 . The state machines in logic 131 are configured so as to periodically repeat all the basic operations of the controller 110 .

[0054] In a preferred embodiment, fault control and logic circuit 133 logically OR's the alarm and warning flags, along with the internal LOS (loss of signal) input and Fault Input signals, to produce a binary Transceiver fault (TxFault) signal that is coupled to the host interface, and thus made available to the host device. The host device can be programmed to monitor the TxFault signal, and to respond to an assertion of the TxFault signal by automatically reading all the alarm and warning flags in the transceiver, as well as the corresponding monitored signals, so as to determine the cause of the alarm or warning.

[0055] The fault control and logic circuit 133 furthermore conveys a loss of signal (LOS) signal received from the receiver circuit (ROSA, FIG. 2 ) to the host interface.

[0056] Another function of the fault control and logic circuit 133 is to disable the operation of the transmitter (TOSA, FIG. 2 ) when needed to ensure eye safety. There is a standards defined interaction between the state of the laser driver and the Tx Disable output, which is implemented by the fault control and logic circuit 133 . When the logic circuit 133 detects a problem that might result in an eye safety hazard, the laser driver is disabled by activating the Tx Disable signal of the controller. The host device can reset this condition by sending a command signal on the TxDisableCmd line of the host interface.

[0057] Yet another function of the fault control and logic circuit 133 is to determine the polarity of its input and output signals in accordance with a set of configuration flags stored in memory 128 . For instance, the Loss of Signal (LOS) output of circuit 133 may be either a logic low or logic high signal, as determined by a corresponding configuration flag stored in memory 128 .

[0058] Other configuration flags (see Table 4) stored in memory 128 are used to determine the polarity of each of the warning and alarm flags. Yet other configuration values stored in memory 128 are used to determine the scaling applied by the ADC 127 when converting each of the monitored analog signals into digital values.

[0059] In an alternative embodiment, another input to the controller 102 , at the host interface, is a rate selection signal. In FIG. 3 the rate selection signal is input to logic 133 . This host generated signal would typically be a digital signal that specifies the expected data rate of data to be received by the receiver (ROSA 102 ). For instance, the rate selection signal might have two values, representing high and low data rates (e.g., 2.5 Gb/s and 1.25 Gb/s). The controller responds to the rate selection signal by generating control signals to set the analog receiver circuitry to a bandwidth corresponding to the value specified by the rate selection signal.

[0060] FIG. 4 is a block diagram of another optoelectronic transceiver 400 in accordance with another embodiment of the present invention. The optoelectronic transceiver 400 is preferably housed within a single housing 401 . The optoelectronic transceiver 400 includes an optoelectronic receiver and an optoelectronic transmitter. The optoelectronic receiver preferably forms part of a Receiver Optical Subassembly (ROSA) 402 , while the optoelectronic transmitter preferably forms part of a Transmitter Optical Subassembly (TOSA) 404 , as described above.

[0061] In a preferred embodiment, the optoelectronic receiver is an Avalanche Photodiode (APD) 406 . An APD is a photodiode that exhibits internal amplification of photocurrent through avalanche multiplication of carriers in the junction region. Such amplification requires a relatively high supply voltage, typically in the range of about 30V-70V, shown as APD Voltage in FIG. 4 . This voltage is supplied to the APD by an isolated APD power supply 410 . The optoelectronic receiver is also coupled to a post amplifier 412 , as described above.

[0062] Optical signals received by the optoelectronic receiver in the ROSA 402 are transmitted along a received power connection, shown as Data+/Data− in FIG. 4 , to the post amplifier 412 . The post amplifier 412 generates a fixed output swing digital signal which is connected to a remote host via RX+ and RX− connections, as described above.

[0063] The optoelectronic transmitter is preferably a LED or laser diode 405 , and is electrically coupled to a laser driver 414 . In use, the optoelectronic transmitter within the TOSA 404 is not turned on and off, but rather modulated between high and low levels above a threshold current. This threshold current or DC bias current, shown as DC Bias in FIG. 4 , is supplied to the TOSA 404 from the laser driver 414 . The modulation current, or AC current, shown as Out+/Out− in FIG. 4 , is also supplied to the optoelectronic transmitter from the laser driver 414 . The level of the DC bias current is adjusted to maintain proper laser output (i.e., to maintain a specified or predefined average level of optical output power by the optoelectronic transmitter) and to compensate for variations in temperature and power supply voltage. In use, a host transmits signal inputs TX+ and TX− to the laser driver 414 via TX+ and TX− connections, as described above (but not shown in FIG. 4 ).

[0064] In a preferred embodiment, a Thermoelectric Cooler (TEC) 408 is disposed within the TOSA 404 to dissipate heat from the optoelectronic transmitter, or more generally to regulate the temperature of the optoelectronic transmitter 405 . The TEC 408 is electrically coupled to, and controlled by, a TEC driver 416 .

[0065] In addition, some optoelectronic transceivers include an output power monitor 403 within the TOSA 404 that monitors the energy output from the optoelectronic transmitter. The output power monitor 403 is preferably a photodiode within the laser package that measures light emitted from the back facet of the laser diode 405 . In general, the amount of optical power produced by the back facet of the laser diode, represented by an output power signal, is directly proportional to the optical power output by the front or main facet of the laser diode 405 . The ratio, K, of the back facet optical power to the front facet optical power will vary from one laser diode to another, even among laser diodes of the same type. This ratio is determined during device setup and calibration. The output power monitor signal, shown as LD Power in FIG. 4 , is supplied from the output power monitor 403 in the TOSA 404 to the two controller ICs 418 and 420 .

[0066] The optoelectronic transceiver 400 also includes at least two controller integrated circuits (ICs) 418 and 420 . The first controller IC 418 is preferably configured to control the DC bias current supplied to the TOSA 404 and to control the voltage supplied to the APD 406 . The second controller IC 420 is preferably configured to control the AC current supplied to the TOSA 404 , and to control the TEC 408 . In addition, both the first and second controller ICs are preferably configured to gather diagnostic data from the various optoelectronic transceiver components, store this diagnostic data, and provide this diagnostic data to a remote host (not shown).

[0067] The first controller IC 418 is identical to the controller IC 110 described above in relation to FIGS. 2 and 3 . As shown in FIG. 3 , the first controller IC 418 includes internal analog to digital conversion circuitry 124 ( FIG. 3 ), and digital to analog conversion circuitry 123 ( FIG. 3 ). Therefore, the first controller IC 418 is capable of receiving and transmitting both analog and digital signals. While the first controller 48 is preferably the same as the controller IC 110 described above, in this embodiment the output of one of its D/A converters is used to control the power supply 410 for an avalanche photodiode 406 .

[0068] The second controller IC 420 preferably includes many of the same components as the first controller IC 418 , with the primary exception being that the second controller IC 420 has a central processing unit (CPU) 502 ( FIG. 5 ) that executes stored programs instead of the fixed logic and state machines of the first controller IC 418 . The CPU 502 of this second controller 420 is better suited for controlling the TEC (i.e., generating TEC control signals so as to maintain the temperature in the TOSA 404 at a specified target temperature) than the more limited state machine logic of the first controller IC 418 . FIG. 5 is a more detailed block diagram of the second controller IC 420 shown in FIG. 4 . The second controller IC 420 includes: a CPU 502 , as just mentioned; at least one input port 504 ; at least one output port; general purpose non-volatile memory, such as EEPROM or FLASH, similar to the EEPROM 120 ( FIG. 3 ) described above; diagnostic value and flag storage 508 similar to the storage 128 ( FIG. 3 ) described above; and a serial interface 430 similar to the serial interface 121 ( FIG. 3 ) described above.

[0069] If the first controller IC 418 or the second controller IC 420 do not have enough internal static digital to analog, or analog to digital, converters, then external converters may be provided. In one embodiment, outputs may be implemented using Pulse Width Modulation (PWM), which is a powerful technique for controlling analog circuits with a processor's digital outputs.

[0070] Returning to FIG. 4 , the first controller IC 418 preferably includes a number of input ports 124 ( FIG. 3 ). These input ports are preferably electrically coupled to the APD power supply 410 , post amplifier 412 , and laser driver 414 . Input signals received at these input ports include: a photodiode monitor signal (PD monitor) from the APD power supply; a loss of received power (RxLOS) signal from the post amplifier 412 ; and a DC bias monitor signal (DS Bias) and laser diode monitor signal (LD Monitor) from the laser driver. The photodiode monitor signal (PD monitor) is an indication of the received power. The loss of received power (RxLOS) signal is an indication that the optoelectronic receiver is not receiving an incoming optical signal or is not functioning. The DC bias monitor signal (DC Bias) is an indication of DC bias power being supplied to the optoelectronic transceiver. The laser diode monitor signal (LD Monitor) is an indication of the optoelectronic transmitter power being detected by the output power monitor 403 .

[0071] The first controller IC 418 also preferably includes a number of output ports 123 ( FIG. 3 ). The output ports are preferably electrically coupled to the APD power supply 410 and the laser driver 414 . Output signals supplied from these output ports preferably include an APD control signal (APD Control) supplied to the APD power supply 410 and a DC bias control signal (DC Bias Control) supplied to the laser driver 414 . The APD control signal (APD Control) is used to control the APD power supply and hence the voltage supplied to the APD 406 , while the DC bias control signal (DC Bias Control) is used to control the laser driver 414 and hence the DC bias current supplied to the optoelectronic transmitter.

[0072] The second controller IC's input ports 504 ( FIG. 5 ) are electrically coupled to the APD power supply 410 , the laser driver 414 , and the TEC 408 . Input signals received at these input ports include: a photodiode monitor signal (PD monitor) from the APD power supply; a DC bias monitor signal (DS Bias) and laser diode monitor signal (LD Monitor) from the laser driver; and a TEC temperature (TEC Temp.) from the TEC. The photodiode monitor signal (PD monitor) is an indication of the received power. The DC bias monitor signal (DC Bias) is an indication of the DC bias current being supplied to the optoelectronic transceiver. The laser diode monitor signal (LD Monitor) is an indication of the optoelectronic transmitter power being detected by the output power monitor 403 . The TEC temperature (TEC Temp.) is an indication of the temperature of the TEC.

[0073] The second controller IC's output ports 506 ( FIG. 5 ) are preferably electrically coupled to the laser driver 414 and the TEC driver 416 . Output signals supplied from these output ports preferably include an AC control signal (AC Control) supplied to the laser driver 414 , and a TEC control signal (TEC Control) supplied to the TEC driver 416 . The AC control signal (AC Control) is used to control the laser driver to supply modulated AC current to the optoelectronic transmitter. The TEC control signal (TEC Control) is used to control the TEC driver 416 and hence the TEC 408 itself. The CPU 502 of the second controller IC executes control software so as to control the TEC 408 , so as to maintain a specified or target temperature in the TOSA 404 . The control software executed by the CPU 502 may implement a conventional PID control loop for controlling the TEC 408 , using the TEC temperature feedback signal as a control feedback signal.

[0074] Because in one embodiment the second controller IC 420 does not include enough internal analog to digital, and digital to analog converters, an analog to digital converter (ADC) 422 and a digital to analog converter (DAC) 424 are preferably supplied external to the second controller IC 420 . The ADC 422 converts the DC bias monitor signals (DC Bias Monitor) and photodiode monitor signals (PD Monitor) from analog signals to digital signals before these signals enter the second controller IC 420 . Similarly, the DAC 424 converts the digital AC control signal to an analog equivalent before the signal reaches the laser driver 414 . In alternative embodiment, some or all of the analog to digital and digital to analog conversion functions are performed internally, within the second controller IC 420 .

[0075] Unlike the first controller IC 418 that includes its own internal temperature sensor 125 ( FIG. 3 ), the second controller IC 420 preferably obtains the temperature of the optoelectronic transceiver 400 from an external thermistor 426 . In an alternative, the second controller IC 420 includes an internal temperature sensor.

[0076] In use, the second controller IC 420 controls the TEC driver supplied to the TOSA 404 as follows. The temperature from the thermistor 426 is read by an ADC channel in the second controller IC 420 . The CPU 502 ( FIG. 5 ) in the second controller IC 420 then computes a TEC drive command with a digital servo implemented in software and outputs a TEC control signal (TEC Control) using pulse width modulation, which acts as a kind of DAC. The TEC driver 416 accepts this TEC control signal as a voltage and drives the TEC accordingly. In one embodiment, the digital servo that controls the laser temperature uses a command value, servo gain settings, and limit settings stored in the non-volatile memory 500 ( FIG. 5 ) to produce the TEC control signal.

[0077] Data received from the inputs in the first and second controller ICs are preferably stored in a diagnostic value and flag storage memory 128 ( FIG. 3 ), and 508 ( FIG. 5 ), respectively. In a preferred embodiment, the first controller IC 418 stores values for power supply voltage (Vcc), internal temperature, DC bias current/power, transmitted current/power, received current/power, etc. Similarly, in a preferred embodiment, the second controller IC 418 stores values for power supply voltage (Vcc), temperature measured by the thermistor 426 , DC bias current/power, transmitted current/power, TEC temperature/load, etc. Accordingly, some of the same diagnostic data is stored on both the first and second controller ICs. This redundancy has many benefits, as will be described below.

[0078] The first and second controller ICs are also preferably coupled to a power supply via a supply voltage Vcc. Furthermore, the first and second controller ICs 418 and 420 each include a respective interface 428 and 430 to communicate with a remote host (not shown). The interface 428 is similar to the interface 121 ( FIG. 3 ) described above. This interface is preferably a serial interface, such as an I2C (Inter IC), 2Wire, or MDIO bus. An I2C bus is a bi-directional two wire serial bus that provides a communication link between integrated circuits. An MDIO bus is a Management Data Input/Output bus, as described by the IEEE 802.3 specification. Alternatively, any other suitable serial interface could be used equally well.

[0079] In addition, the first and second controller ICs preferably have different serial device addresses, indicated by A0 and A2 in a preferred embodiment. In this way, a host can access each of these controller ICs separately and independently. Memory mapped locations within each controller are mapped to an address formed by concatenating a device address, specifying the controller, and a sub-device address, specifying a memory mapped location within one of the controllers. Host devices are typically preconfigured to read particular memory mapped locations for particular diagnostic data. However, different hosts may be preconfigured to read different memory mapped locations for the same diagnostic data. The inclusion of two controller ICs, however, allows the same diagnostic data to be stored in completely different memory mapped locations. This allows hosts that are preconfigured differently to read different memory mapped locations on the different controller ICs to obtain the same diagnostic data. In one embodiment, the memory mapped locations on the two controller ICs emulate two different host configurations, having different memory maps for each of the two controller ICs. In another embodiment, the two controller ICs have different device addresses, but identical memory maps (for host accessible locations) within the two controller ICs.

[0080] In yet another embodiment, the interfaces 428 and 430 in the first and second controller ICs, respectively, may communicate using different communication protocols. This allows the same optoelectronic transceiver to be used with hosts that communicate using different protocols. For example, in a first system configuration a first host may access diagnostic information on the first controller IC 418 using a first communication protocol, while in a second system configuration, a second host may access the same diagnostic information on the second controller IC 420 using a second communication protocol. This allows the same optoelectronic transceiver to be used in both systems without any redesign or reconfiguration of the communication protocols used by the optoelectronic transceiver.

[0081] While the combination of all of the above functions is desired in the preferred embodiment of this transceiver controller, it should be obvious to one skilled in the art that a device which only implements a subset of these functions would also be of great use. Similarly, the present invention is also applicable to transmitters and receivers, and thus is not solely applicable to transceivers. It should be pointed out that the controller of the present invention is suitable for application of multichannel optical links. It should also be appreciated that although two controller ICs are described herein, any number of controller ICs greater than one could be used to provide the functionality described above. Finally, the use of the term controller IC is not intended to limit the controller IC to performing control functions. 1

[0082] 2

[0083] 3

[0084] 4