DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

[0028] The present invention now will be described more fully with reference to the accompanying drawings, in which the preferred embodiments of the invention are shown. The present invention may, however, embodied in many different forms and should not be construed as limited to the embodiment set forth herein; rather these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the invention to those skilled in the art.

[0029] FIG. 1 shows a typical radio monitoring system 100 that is programmed to perform the functions of monitoring a trunked radio communications system. The system 100 includes at least one processing element 102 (any 32 bit processor or processors is appropriate), main memory 104 and some storage device 106 . The storage device 106 of the system 100 stores the operating system software 118 , application programs 124 and a database containing a plurality of sample tables 120 .

[0030] As FIG. 1 shows the storage device 106 includes a series of application programs 124 that comprise a signal processing program 126 , an OSW processing program 128 and a radio control program 130 . In accordance with the present invention, these application programs, either singularly or in combination, direct various system components of radio monitoring system 100 such as sound card 110 in conjunction with the frequency tuned radio receiver 140 to automatically identify the type and data rate of any industry standard, commercially available trunked radio communications system from the digital message transmitted across the control channel.

[0031] By selecting a sampling rate substantially higher than the highest expected trunking control channel data rate, the signal processing software can be designed to identify and decode any of the desired trunking systems without changing the sampling rate. This is advantageous, since most personal computer sound cards are limited to only a few rates. For example, most common personal computer sound cards can sample at 11.025 kHz, 22.05 kHz and 44.1 kHz.

[0032] By using the appropriate sampling rate generated by the sound card, as well as a unique signal processing application facility, the present invention scans a range of frequencies, determines the type of radio system, analyzes the extracted information to obtain the channel assignment code and talk group identification code and comparing the agency or group talk identification code, tuning the frequency tuned radio receiver to a working voice channels in order to monitor a truncked communications system. As will be disclosed in detail in FIG. 3 , the present invention includes a bit phase compensator (BPC) that comprises a sample counter, sample selector and bit phase compensator table selects appropriate samples from the incoming sample stream, producing a synchronized output bit data stream at the rate originally transmitted by the trunking system control channel transmitter.

[0033] For example, selecting a sampling rate of 11.025 kHz maybe acceptable for on a Motorola system running at 3600 baud, but it does not provide enough samples to accurately decode data from an EDACS radio system running at 9600 baud. Selecting a sampling rate of 22.05 kHz allows for the accurate decoding of an incoming data stream from either Motorola radio systems or EDACS radio systems.

[0034] Furthermore, a person of ordinary skill in the art will understand the systems 100 may also includes such components as a keyboard, a mouse, and a one or more display devices, such as a high resolution monitor. In addition, the storage device 106 for system 100 will includes devices such as floppy disk drives, CD-ROM drives, or DVD players that are capable of reading computer instructions that has been stored on a compatible computer readable medium.

[0035] In the following discussion, it is understood that the appropriate processors 102 (or similar processors) perform the steps of methods and flowcharts discussed preferably executing instructions stored in storage device 104 . It is also be understood that the invention is not limited to any particular implementation or programming technique and that the invention may be implemented using any appropriate techniques for implementing the functionality described herein. In addition, the present invention is not limited to any particular programming language or operating system.

[0036] The software stored in storage device 106 may have been supplied from computer-readable medium 116 . Execution of the sequence of instructions retrieved from the storage device 106 causes the processor 102 to perform the steps of monitoring a trunked communications system described herein. In addition, alternative embodiments of the present invention are not limited to any specific combination of hardware and software.

[0037] The term “computer-readable medium” as used refers to any medium that provides the sequence of instructions to a processor for execution. Such a medium may take many forms including, but not limited to, volatile media, non-volatile media or through a transmission media. Non-volatile refers to includes either optical or magnetic data storage media. Volatile media refers to various types of dynamic memory. Transmission media includes application content and data sent via coaxial or fiber optic cable or those transmitted via acoustic, light, radio, or infrared data communications facilities. Common forms of computer-readable media include, a floppy disk, a flexible disk, a hard disk, magnetic tape, or any other magnetic medium, a CD-ROM, any other optical medium or any other physical media such as PROM, EPROM, FLASH-EPROM, any other memory chip or cartridge, a carrier wave as or any other medium from which a computer is able to read a sequence of program instructions, applications content or data.

[0038] Various forms of computer readable media may be involved in carrying one or more sequences of instructions to a processor for execution. For example, the instructions may initially be carried on a magnetic or optical disk to and from a remote computer. As shown in FIG. 1 , bus 108 carries either a sequence of program instructions, and applications content to the main memory 104 , from which a processor 102 retrieves and uses the instructions and applications content. The instructions received by main memory may be stored on a storage device 106 either before or after execution by a processor 102 . The instructions can also be transmitted via a carrier wave via a network, such as a LAN, a WAN, or the Internet.

[0039] FIGS. 2 a and 2 b show the message formats of both the Motorola and EDACS radio communication systems. Modernly, most trunked radio communications systems have a number of different features and capabilities. These can be transmission rate, message type, and error correction, for example. But one of the most common characteristics for all these radio systems is the format of a typical transmitted message. Typically, each message includes a preamble and an information frame. As illustrated in FIG. 2 a, the format of a message 202 transmitted by a Motorola trunked dispatch or radio communication system includes a preamble 204 that is eights bits long and an information frame 206 that is seventy-six bits long. FIG. 2 b shows the message format of an Enhanced Digital Access Communications System (EDACS) that includes a preamble 208 that is forty-eight bits long and an information frame 210 that is two hundred-forty bits in length. In either case, the preamble comprises a predetermined sequence of bits that has a set of low auto-correlation characteristics that allow the processing unit of a mobile radio to rapidly synchronize its decoding logic to an incoming signal. In addition, the preamble can be used to determine at what instant in time the information frame will arrive. Here the information frame includes a data message that is preceded by a predetermined bit pattern or code that is added to the data message prior to transmission so that any errors that might occur can be detected or corrected by the receiver or scanner.

[0040] Reference is now made to FIG. 3 which is a detailed block diagram of the signal processor as implemented by the present invention. As FIG. 3 shows a zero cross filter and detector 302 and correlator array 304 precedes the signal processor 126 . As the data message is processed, the zero cross filter and detector 302 detects the polarity of each bit in the incoming data stream, converts the received data stream from PCM to its NRZ equivalent and directs the converted data stream to the correlator array 304 and the polarity inverter 306 . Here, the correlator array 304 is a multi-element software mechanism that compares the incoming received samples with a predetermined set of test values. By performing this function, the correlator array 304 identifies the type of radio system, the polarity of the data, and the proper position in the BPC table to enable the correct rendering of the data stream at the correct rate.

[0041] As shown in FIG. 3 , the signal processor 126 includes a polarity inverter 306 , system selector 310 and a sample selector 312 . In addition, a bit counter 308 and a bit phase compensator table (BPC) 314 are directly interfaced to the sample selector 312 . The bit counter 308 maintains a count of the number of the bits received and directs the sample selector 312 in selecting samples the high rate data.

[0042] Responsive to the results of the correlator array 304 , the radio system selector 310 switches to the appropriate radio system and selects the appropriate BPC table 314 . As shown here, the inbound data stream is introduced to the polarity inverter 306 that inverts the polarity of any data bits or samples in the received data stream from negative to positive, thus, directing an all positive data stream to the sample selector 312 . The sample selector 312 receives the data stream and reconstructs the coded information frame in accordance with the corresponding bit selection from the BPC table 314 .

[0043] Also as FIG. 3 shows, a bit phase compensator (BPC) comprises the sample counter 308 , sample selector 312 and the BPC table 314 . The bit phase compensator (BPC) compensates for the random phase relationship between incoming samples and the transmitted information bits, and produces an output information data stream at the data rate of the originally transmitted information. The bit phase compensator (BPC) processes the incoming high rate data stream whose polarity has been corrected by polarity inverter 306 , and produces an output data stream that is a reconstruction of the originally transmitted data. Incoming samples are processed one at a time.

[0044] FIG. 4 is a graphical illustration that shows a preamble at 3.6 Kb for a Motorola radio system and by applying the appropriate correlation mask a sequence of preferred samples can be calculated as implemented by the present invention. As FIG. 4 shows the preamble of a Motorola radio system at 3.6 Kb 202 and a representative sampling rate of 11.025 KHz 404 . By applying the correlation mask 406 , in accordance to the method described above to the preamble 402 , the best samples are then selected 408 . As FIG. 4 shows, there are more samples in the incoming sample stream than information data bits. The bit phase compensator (BPC) selects the best sample for each information bit and ignores other samples. The sample counter 308 addresses a row in the BPC table 314 . As each incoming sample is processed, the sample counter 308 is then incremented by one. When the end of the table is reached, the sample counter 308 is reset to zero, so the progression through the BPC table 314 represents the repeating phase relationship between samples and information data bits.

[0045] Each row of the BPC table 314 has an indicator for the best bit for each sample. When a BPC row is accessed that is designated as a best bit, the incoming high rate bit is transferred to the output. If the best-bit indication is off, the high rate sample is ignored. Since the sample counter 308 is preset by the one of the correlators in the correlator array 304 when a preamble is detected, the BPC table 314 is then synchronized to the proper point in the repeating phase sequence of samples. Thus the output from the BPC table 314 contains fewer bits than the number of samples in the incoming data stream. This corresponds to the difference between the chosen sampling rate and the information data rate sent by the trunking control channel transmitter.

[0046] The reconstructed information data stream is then presented to the OSW processing element 128 . This element scans the data stream for the beginning of the information data frame, determines the type of message, and extracts frequency and talk group codes from the messages. Once the frequency and talk group information have been extracted, the radio receiver processing element 130 the tunes the radio to the appropriate frequency in order to receive the voice transmission.

[0047] In the case of the EDACS trunking system, the OSW messages do not contain frequency information, only contain logical channel numbers. To properly tune a radio to an EDACS working channel, the receiver processing element 130 must know the frequency that corresponds to the logical channel number in the message.

[0048] To discover the frequencies in use in an EDACS system, the receiver processing element employs an adaptive search method described here. First, tables in the computer memory are created containing five integer data elements for each potential radio frequency. The data elements are the active count, inactive count, test count, fail count and the lock indicator. One table is created for each logical channel whose frequency is unknown. The number of possible radio frequencies is large, but limited by factors such as channel spacing and the way frequencies are assigned to users by the government frequency management authority.

[0049] When an OSW message is received with a logical channel number whose frequency is unknown, the receiver processing element 130 begins a frequency search. When searching, frequencies above and below the control channel are sequentially tuned at fixed steps. As each frequency is tuned, the receiver processing element determines if a signal is present on the frequency. If a signal is present, the active count is incremented. If a signal is not present, the inactive count is incremented. After the appropriate counter is incremented, another frequency is selected and the process is repeated. This process continues for a user configurable time, typically two seconds, the receiver processing element then terminates the search and returns to the trunking system control channel to decode more OSW messages.

[0050] The receiver processing element 130 takes an additional step to validate the information collected during the searching process. Each time a new OSW message with an unknown logical channel number is decoded, the frequency with the highest ratio of active to inactive counts is tuned first, before the sequential search is begun. If a signal is found to be present, the test count in the table is incremented. If there is no signal, the fail count is incremented. Channels with more than a few fail counts can be ruled out.

[0051] If the test count for a frequency exceeds a user configurable threshold level, and the fail count is very small or zero, the receiver processing element forgoes the searching process and remains tuned to the frequency to allow the user to listen to the transmission. The user can decide to accept the frequency, in which case the receiver processing element will permanently associate the frequency with the logical channel. The user can also decide that the transmission being heard is not from the trunking system, and the receiver processing element sets the lock indicator. Once the lock indicator is set, the frequency is no longer considered a candidate, and will be ignored in future searching activities. If the user takes no action, the receiver processing element 130 handles the transmission the same way as it would a normal EDACS transmission where the logical channel association was known, i.e. returning to the control channel after the transmission ends. Thus, after some period of time, the receiver processing element 130 will gradually discover the logical channel to frequency relationship, and scanning the EDACS system will approach normal.

[0052] FIGS. 5 a - 5 d is flowcharts illustrating the steps used to calculate the values in the BPC table 314 . Each of the steps shown are carried out for once each combination of sample rate and system baud rate that are the stored as table functions to be used during the correlation and bit phase compensation processes.

[0053] As shown by FIG. 5 a, at step 504 , the data rate is set to 3.6 Kb while, at step 506 the sample rate is set to 11.025 KHz. Once these two parameters have been set, at step 508 , the monitoring system calculates the values that are required for the bit phase compensation table. The calculation of the values for the bit phase compensation table, at step 508 , comprises a series of intricate of steps that are shown in FIGS. 5 b to 5 e. As shown in FIG. 5 b, to obtain the necessary values required for the bit phase compensation table, a series of calculations are performed that includes calculating the sample period (at step 503 ), determining the data bit width DBW (at step 505 ) and calculating data bits alignment (at step 507 ). Next the monitoring system calculate what portion the received data bits are to be ignored (at step 509 ), what portion of the received data bits are positioned in the early zone (at step 511 ), what portion of the received data bits are in the middle zone (at step 513 ) and what portion of the received data bits are last and thus, will be ignored (at step 515 ).

[0054] As FIG. 5 c shows, the monitoring system, at step 517 , determines the placement of the data bit in the pattern and then, at step 519 determines if the received sample falls either in front of or behind the center point of the DBW. Once the it has been determined that the sample is either in the in front or behind the center point of the DBW, the monitoring system, step 521 , determines if the received bit pattern is repeated and if the bit pattern is aligned. If the repeated bit pattern is not aligned, at step 521 , the monitoring system, at step 523 , then proceeds to calculate the next sample time and repeats steps 517 to 521 until the bit pattern that is repeated is aligned. But if the repeated bit pattern is aligned, the monitoring system at steps 525 and 527 respectively, allocates enough space to store the bit phase compensation table and determines the placement of the data bit in the bit pattern.

[0055] At this point in the process, the monitoring system performs a number of subroutines to determine what will be the best sample to use. As FIG. 5 d shows, at step 531 , the monitoring system calculates the position of a sample and then, at step 533 , performs a zone subroutine to determine the relative position of the specified sample. Referring to FIG. 5 e that show, in detail, the method, at step 533 , used to determine the relative position of a sample. As FIG. 5 e shows at step 550 , the mentoring system calculates the actual position of the sample in accordance to one of three zones and if it is to close to the near edge of the received pattern. Thus, if, at step 552 , the offset of the sample is to close to the edge, then at step 554 , the sample will be ignored. But if the offset is just beyond the near edge then at step 556 the sample is said early, then the bit is classified, at step 558 , as being in the early zone. If the offset, at step 560 , places the sample somewhere close to the middle, then it is classified, at step 562 , as being in the middle zone. If the offset, at step 564 , places the sample beyond the boundaries of the middle zone, then the sample is classified, at step 566 , as being late and those samples that are even beyond the late zone, at step 568 , are ignored.

[0056] Once the position of the sample has been determined relative distance from the center of the data bit is calculated at step 535 . This then is used, at step 537 , to determine if the sample is either in front of or behind the center data bit. Then at step 539 , the sample closest to the center is selected and store in the bit phase compensation table. If the table is not complete (i.e. the best sample has not been found) then, at step 545 , a new sample time is calculated and steps 529 to 545 are repeated. But, if the table is complete, then, at step 571 process of finding the best sample is done and the monitoring system proceeds back to step 510 to calculate the preamble test value.

[0057] The signal processor, at step 510 , selects the preamble subset for each radio system to be monitored. The preamble subset is then used by the correlator to detect the presence of the desired radio system. This means that the bit phase compensation table calculated at step 508 for a Motorola radio system with a sampling rate of 22.05 kHz has 49 entries and spans 8 bits of 3600 Baud data, while a EDACS data sampled at 22.05 kHz requires 147 samples to span 64 bits of 9600 baud of data. Thus, in the case of Motorola systems, where each data frame contains an eight-bit preamble, the entire preamble fits exactly in a complete set of 49 samples. Thus, the Motorola correlator for samples at 22.05 kHz will require only a single preamble value. On the other hand, the EDACS data format has a 48-bit preamble. As a result, there are thirteen possible positions for the EDACS preamble in a set of 64 samples. For maximum speed, the EDACS correlator should compare each of the thirteen possible values. However, if simplicity is desired over speed, then less than thirteen values can be used.

[0058] Once the preamble subset has been determined, at step 512 , the preamble test values used by the correlator are then calculated. The value is computed by setting bits in the test value corresponding to the preamble bit values selected in the previous step. Thus, a portion of system memory that is large enough to accommodate the test values is reserved. Since the Motorola system at 22.05 kHz requires 49 bits, seven eight-bit bytes are required, or two 32-bit words. The initial value of each bit is set to zero. For Motorola systems a preamble value of ‘AC’ in hexadecimal notation is used. The first bit from the preamble subset from step 506 is placed in each bit position of the test value according to a predefined sequence of data bits. Likewise, the remaining bits are similarly placed in the test value and those bits in the test value that are to be ignored are set to zero. If the preamble subset contains fewer bits than are spanned in one set of samples (EDACS for example), additional test values are calculated by shifting the original preamble value and repeating this process.

[0059] Now that the preamble test value has been calculated, at step 514 the inverted preamble test value is calculated. In this step, the correlator test value is calculated for an inverted system. This additional value is calculated by inverting the bits calculated for a test value (step 508 ), and then resetting bits in the inverted test value that are marked as ignored are set to zero. At step 516 , the correlation mask value is then calculated for each preamble test value. The correlator uses this value to select which bits will be compared. Each mask value has the same number of bits as the preamble test value. Each mask value initially contains all zeroes. Bits in the mask value that are set correspond to the bits found in the bit phase compensation table that are not ignored. Thus, for the Motorola radio system sampled at 22.05 kHz will have the following values:

[0060] Motorola preamble: ‘AC’

[0061] Motorola test value: ‘01 F81 F81 FFE000’

[0062] Motorola mask value: ‘01 F7DF7CFBEFBE’

[0063] Then the system, at step 518 , determines the minimum preamble alignment interval. In this step the expected frequency of a preamble aligned in a set of successive samples is determined. First, the number of incoming samples per transmitted data word is calculated. For a Motorola system that transmits a data word containing an 8 bit preamble and a 76 bit information frame, a set of 49 samples at 22.05 kHz will span 8 bits of transmitted data will require approximately 514.5 successive samples (i.e. 84/8×49). Since this result is not a whole number, the correlator will only be able to detect a preamble in the incoming data every 1029 samples (514.5×2). It also should be noted that even though the preamble may not be aligned for every message, the bit phase compensator will render the correct transmitted data. Once these values have all been calculated, at step 520 , they are stored in an appropriate set of tables to be used by the signal processor 126 to decode and monitor a plurality of truncked radio systems.

[0064] Reference is now directed to FIG. 6 is a block diagram that details the operative elements of the correlator array in accordance with FIG. 3 . As previously mentioned the zero cross filter and detector 302 detects the polarity of each bit in the incoming data stream, converts the received data stream from PCM to its NRZ equivalent and directs the data stream to the correlator array 304 . As FIG. 6 shows, the correlator array 304 is a multi-element software mechanism that processes incoming samples and detects the presence of a system by scanning the incoming samples for the pre-calculated preamble test value, masked by the corresponding mask value. As shown in this illustrative view, the correlator includes a set of Motorola positive 604 and negative 608 correlators, a set of EDACS positive 606 and negative 610 correlators as well as a set of positive and negative correlators 612 for each of the other designated radio systems. As a result, the positive data bits or samples of the incoming data message from a Motorola radio system are directed to and correlated by the Motorola positive correlator 604 while the negative data bits or samples are directed to and correlated by the Motorola negative correlator 608 simultaneously and in parallel.

[0065] FIG. 7 is a schematic diagram detailing the logic functions of the correlation elements of a correlator in accordance with the implementation of the correlator array shown in FIG. 6 . As FIG. 7 shows, correlator 700 includes a plurality of correlation elements 702 a - 702 n. Each correlation element 702 a - 702 n includes an exclusive-OR (XOR) 710 and an AND logic function 712 . As one ordinarily skilled in the art will realize and appreciate that the process of correlating a plurality of incoming data bits can be performed in parallel depending on the processor and configuration of system used. For example, the test and correlation mask values of a Motorola radio system are approximately 49 bits in length when sampled at 22.05 kHz. As a result, an eight-bit microcontroller used in a radio system will require approximately seven iterations to perform the required correlation function. But, if a personal computer system having a 32-bit processor such as Intel Pentium III™ or IV™ is used, it will only takes a relatively small number of machine cycles to perform the same function. But for this embodiment, those components in the figures that comprise a number of elements will be clearly referenced, as such but for the purposes of clarity, the individual, single operative components of correlation element 702 a will be used specifically for this discussion.

[0066] As FIG. 7 shows the exclusive-Or 710 receives data bits and test values via input nodes 704 and 706 , respectively and computes a resultant value that is then directed to an “AND” logic function 712 . Here, the “AND” function 712 combines the value received from the exclusive-OR 710 with a correlation mask value received via input node 708 that produces a correlation result 714 . If the output from the “AND” logic function is all zeroes, indicating that the test value matches the incoming data bits in all positions, then correlation result is a positive match. When a positive match is detected, the correlator 700 saves the value accumulated by sample counter 308 and then resets the counter 308 to zero. In addition, if the saved value is equal to a specific pre-calculated minimum preamble alignment interval or it is at least equivalent to an integer multiple of that value and if the position of two preamble codes detected in the incoming data stream are consistent with the length of the transmitted data messages, there is a high probability that the appropriate system has been identified. If so, the system selector 302 is then set to the identified system type, and the bit phase compensator 310 is reset, indicating that the sampled data is aligned.

[0067] It should be also noted that it is possible for the preamble bit sequence to appear in the body of a data message, thus giving rise to the possibility of a false detection of the preamble. Looking for multiple preamble codes in the incoming sample stream at intervals of the expected message length reduces, but does not eliminate, the possibility of a false detection. It is understood that the error correction and cyclic redundancy features inherent in a transmitted data message will further reduce the possibility of decoding an invalid message to an acceptable level, as well.

[0068] An alternative embodiment of the present invention envisions uses a micro-controller such as the one used to control a receiver scanner. In this embodiment, the pre-calculation steps are carried out once, during the programming of the micro-controller. Additionally, the incoming data bits are sampled directly using an input port on the micro-controller, rather than using a sound card. Here, the sample rate is selected from a possible set of values for a given the micro-controller architecture and its associated clock rate.

[0069] Although the invention has been described with respect to certain preferred embodiments, modifications and additions within the spirit of the invention will occur to those of skill in the art. Therefore, the scope of the invention is not limited by the foregoing description but is defined solely by the following claims.