Title:

Nonvolatile semiconductor memory device

Document Type and Number:

United States Patent Application 20030235080

Kind Code:

Abstract:

A cell array is configured by arranging a plurality of electrically writable erasable nonvolatile memory cells on a semiconductor substrate. Each of the memory cells has a charge accumulation layer formed via a first gate insulating film and a gate electrode formed on the charge accumulation layer via a second gate insulating film. A control circuit controls the sequence of writing and erasing the data into and from a memory cell selected in the memory cell. In writing the data into the memory cell, a first write operation is to apply a write pulse voltage with a first step-up voltage between the gate electrode and the semiconductor substrate. A second write operation is to apply a write pulse voltage with a second step-up voltage lower than the first step-up voltage.

Inventors:

Yaegashi, Toshitake (Yokohama-shi, JP)
Goda, Akira (Yokohama-shi, JP)
Noguchi, Mitsuhiro (Yokohama-shi, JP)

Plaque It!

What is claimed is:

1. A nonvolatile semiconductor memory device comprising: a semiconductor substrate; a cell array which is configured by arranging a plurality of electrically writable erasable nonvolatile memory cells on the semiconductor substrate, each of the memory cells having a gate insulating film including a stacked structure of a tunnel insulating film and a charge accumulation insulating film, and a gate electrode formed on the gate insulating film; and a control circuit which controls write operation and erase operation of a memory cell selected in the cell array and which has an operation mode in which a sequentially stepped-up pulse voltage is applied between the gate electrode and the semiconductor substrate in at least one of the write operation and the erase operation.

2. The nonvolatile semiconductor memory device according to claim 1, wherein the write operation is to apply a monotonously increasing write pulse voltage.

3. The nonvolatile semiconductor memory device according to claim 1, wherein the plurality of memory cells are coupled in series and a source of one of the memory cells is connected to a drain of a select transistor.

4. The nonvolatile semiconductor memory device according to claim 1, wherein the memory cell has its channel width set in the range of 2 Tono to 20 Tono, where Tono is the equivalent oxide film thickness of the gate insulating film.

5. The nonvolatile semiconductor memory device according to claim 1, wherein the gate insulating film is formed so as to be thicker at the ends of the memory cell in the direction of channel width than in the central part of the channel region.

6. The nonvolatile semiconductor memory device according to claim 1, wherein the charge accumulation insulating film extends outward beyond the ends of the channel region or the gate electrode in the direction of channel width.

7. A nonvolatile semiconductor memory device comprising: a semiconductor substrate; a cell array which is configured by arranging a plurality of electrically writable erasable nonvolatile memory cells on the semiconductor substrate, each of the memory cells including a charge accumulation layer formed on a first gate insulating film, a second gate insulating film on the charge accumulation layer, and a gate electrode on the second gate insulating film; and a control circuit which controls the sequence of writing and erasing data into and from a memory cell selected in the cell array and which has a write operation mode including a first write operation of applying sequentially a write pulse voltage with a first step-up voltage between the gate electrode and the semiconductor substrate and a second write operation of applying a write pulse voltage with a second step-up voltage lower than the first step-up voltage in writing the data into the memory cell.

8. The nonvolatile semiconductor memory device according to claim 7, wherein the first and second gate insulating films are silicon oxide films or silicon oxynitride films and the charge accumulation layer is a silicon nitride film.

9. The nonvolatile semiconductor memory device according to claim 7, wherein the first gate insulating film has a thickness of 4 nm or less.

10. The nonvolatile semiconductor memory device according to claim 7, wherein the first gate insulating film is a silicon oxide film or silicon oxynitride film, the charge accumulation layer is a conductive material film, and the second gate insulating film is a stacked insulating film of a second silicon oxide film or silicon oxynitride film, a silicon nitride film, and a third silicon oxide film or silicon oxynitride film.

11. The nonvolatile semiconductor memory device according to claim 10, wherein the thickness of the second silicon oxide film and the silicon oxynitride film is thinner than that of the third silicon oxide film or silicon oxynitride film.

12. The nonvolatile semiconductor memory device according to claim 7, wherein the plurality of memory cells are coupled in series and a source of one of the memory cells is connected to a drain of a select transistor.

13. The nonvolatile semiconductor memory device according to claim 10, wherein the second gate insulating film has a thickness of 4 nm or less.

14. The nonvolatile semiconductor memory device according to claim 7, wherein the first write operation does not include a verify read operation after a write pulse voltage is applied and the second write operation includes a verify read operation to determine a threshold voltage after each write pulse voltage is applied.

15. The nonvolatile semiconductor memory device according to claim 7, wherein the first write operation is to apply a monotonously increasing write pulse voltage.

16. A nonvolatile semiconductor memory device comprising: a semiconductor substrate; a cell array which is configured by arranging a plurality of electrically writable erasable nonvolatile memory cells on the semiconductor substrate, each of the memory cells including a charge accumulation layer made of a conductive material film formed on a first gate insulating film, a second gate insulating film on the charge accumulation layer, and a gate electrode on the second gate insulating film, the second gate insulating film including a lower insulating film, an upper insulating film and a middle insulating film located therebetween, the lower insulating film being thinner than the upper insulating film; and a control circuit which controls the sequence of writing and erasing data into and from a memory cell selected in the cell array and which has an erase operation mode in which a sequentially stepped-up pulse voltage is applied between the gate electrode and the semiconductor substrate in erasing the data from the memory cell.

17. The nonvolatile semiconductor memory device according to claim 16, wherein the second gate insulating film includes either a silicon oxide film of 4 nm or less thick or a silicon oxynitride film of 4 nm or less thick.

18. The nonvolatile semiconductor memory device according to claim 16, wherein the erase operation mode includes a first erase operation of applying an erase pulse voltage with a first step-up voltage and a second erase operation of applying an erase pulse voltage with a second step-up voltage lower than the first step-up voltage.

19. The nonvolatile semiconductor memory device according to claim 18, wherein the first erase operation does not include a verify read operation after an erase pulse voltage is applied and the second erase operation includes a verify read operation to determine a threshold voltage after each erase pulse voltage is applied.

20. The nonvolatile semiconductor memory device according to claim 19, wherein the first erase operation is to apply a monotonously increasing erase pulse voltage discretely.

21. The nonvolatile semiconductor memory device according to claim 19, wherein the plurality of memory cells are coupled in series and a source of one of the memory cells is connected to a drain of a select transistor.

22. The nonvolatile semiconductor memory device according to claim 18, wherein the lower insulating film is configured by one of a silicon oxide film and a silicon oxynitride film, the middle insulating film is configured by a silicon nitride film, and the upper insulating film is configured by one of the silicon oxide film and the silicon oxynitride film.

23. A nonvolatile semiconductor memory device comprising: a semiconductor substrate; a cell array which is configured by arranging a plurality of electrically writable erasable nonvolatile memory cells on the semiconductor substrate, each of the memory cells having a gate insulating film including a stacked structure of a tunnel insulating film and a charge accumulation insulating film, and a gate electrode on the gate insulating film; and a control circuit which controls the sequence of writing and erasing data into and from a memory cell selected in the cell array and which has an erase operation mode in which a first erase pulse defined by a first voltage and a first pulse width is applied between the gate electrode and the semiconductor substrate and thereafter applying a second erase pulse defined by a second voltage smaller in absolute value than the first voltage and a second pulse width greater than the first pulse width in erasing the data from the memory cell.

24. A nonvolatile semiconductor memory device comprising: a memory cell array which is configured by arranging a plurality of electrically rewritable nonvolatile semiconductor memory cells in a matrix, each of the memory cells having a control gate and a charge accumulation layer; a write circuit which writes data by applying a write voltage to the control gate of a memory cell selected in the memory cell array; and a verify circuit which is connected to the selected memory cell and which senses the threshold voltage of the memory cell each time the write voltage is generated and verifies whether the threshold voltage has reached a specific value, wherein each time a write operation is carried out, the write voltage outputted from the write circuit is increased in such a manner that the increment of a first write voltage between a first write operation and a second write operation is larger than the increment of a second write voltage between the second write operation and a third write operation and the increments of the second and later write voltages are constant.

25. The nonvolatile semiconductor memory device according to claim 24, wherein said plurality of write operations have a constant write time.

26. The nonvolatile semiconductor memory device according to claim 24, wherein said plurality of write operations are at least four in number.

27. The nonvolatile semiconductor memory device according to claim 24, wherein said plurality of write operations are such that a first write time is shorter than a second and later write times and the second and later write times are constant.

28. The nonvolatile semiconductor memory device according to claim 24, wherein the first write voltage causes the threshold voltages of at least two memory cells to reach the specific value.

29. The nonvolatile semiconductor memory device according to claim 24, wherein the memory cells are arranged in series in units of plural cells to constitute NAND cells.

30. A nonvolatile semiconductor memory device comprising: a memory cell array which is configured by arranging a plurality of electrically rewritable nonvolatile semiconductor memory cells in a matrix, each of the memory cells having a control gate and a charge accumulation layer; a write circuit which writes data by applying a write voltage to the control gate of a memory cell selected in the memory cell array; and a verify circuit which is connected to the selected memory cell and which senses the threshold voltage of the memory cell each time the write voltage is generated and verifies whether the threshold voltage has reached a specific value, wherein the write voltage outputted from the write circuit is such that a first write time is shorter than a second and later write times and the second and later write times are the same and that a second and later write voltages increase in a specific increment each time a write operation is carried out.

31. The nonvolatile semiconductor memory device according to claim 30, wherein the first write voltage is the same as the second write voltage.

32. The nonvolatile semiconductor memory device according to claim 30, wherein the first write voltage is lower than the second write voltage.

33. The nonvolatile semiconductor memory device according to claim 30, wherein the first write voltage causes the threshold voltages of at least two memory cells to reach the specific value.

34. The nonvolatile semiconductor memory device according to claim 30, wherein the memory cells are arranged in series in units of plural cells to constitute NAND cells.

35. A nonvolatile semiconductor memory device comprising: a semiconductor substrate; a cell array which is configured by arranging a plurality of electrically writable erasable nonvolatile memory cells on the semiconductor substrate, each of the memory cells having a gate insulating film including a stacked structure of a tunnel insulating film and a charge accumulation insulating film, and a gate electrode on the gate insulating film; and a control circuit which controls the sequence of writing and erasing data into and from a memory cell selected in the cell array and which has an erase operation mode in which, when the data in the memory cells is erased, a write pulse is applied between the gate electrode and the semiconductor substrate and then an erase pulse is applied between the gate electrode and the semiconductor substrate and thereafter a verify operation is carried out to verify whether the data has been erased.

36. The nonvolatile semiconductor memory device according to claim 35, wherein the erase operation mode has a mode in which, when the verify operation has determined that the erase operation is incomplete, a write pulse is applied between the gate electrode and the semiconductor substrate and then an erase pulse is applied between the gate electrode and the semiconductor substrate and thereafter a verify operation is carried out to verify whether the data has been erased.

Description:

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2002-179751, filed Jun. 20, 2002; and No. 2002-347798, filed Nov. 29, 2002, the entire contents of both of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] This invention relates to a nonvolatile semiconductor memory device, and more particularly to a step-up write/erase operation.

[0004] 2. Description of the Related Art

[0005] A floating-gate memory cell has been widely used as one of the electrically writable erasable nonvolatile semiconductor memory devices. A floating-gate memory cell has a structure where a floating gate and a control gate are stacked, on a semiconductor substrate. A tunnel oxide film of about 9 nm thick is formed between the semiconductor substrate and the floating gate. An ONO film equivalent to an oxide film of about 14 nm thick is formed between the floating gate and the control gate. The memory cell changes the threshold value of the cell according to the amount of charge accumulated in the floating gate and thereby distinguishes between the state of data “0” (written state) and the state of data “1” (erased state).

[0006] In recent years, a MONOS memory cell using a silicon nitride film as a charge accumulation layer in place of a floating gate has been developed. In a MONOS memory cell, a silicon nitride film formed above the semiconductor substrate via a thin tunnel oxide film of about 2 nm is used as a charge accumulation layer. Data is written into or erased from a MONOS cell by injecting electrons or holes from the substrate into the silicon nitride film to change the amount of accumulated charge in the silicon nitride film and thereby changing the threshold value of the memory cell.

[0007] When writing and erasing are done repeatedly in a MONOS cell, the interface level increases at the interface between the silicon substrate and the tunnel oxide film as pointed out by S. C. Everist, et al. (reference 1: “Modeling the cycling degradation of silicon-oxide-nitride-oxide-semiconductor transistors,” Appl. Phys. Lett. 60(17)27, April 1992, pp. 2101-2103).

[0008] According to reference 1, the increase in the interface level depends on the total amount of charge of the holes passed through the tunnel oxide film. Shin-ichi Minami, et al. have proposed a model where the holes accumulated in the charge accumulation layer pass through the tunnel oxide film when a write voltage is applied, thereby generating an interface level (reference 2: “A Novel MONOS Nonvolatile Memory Device Ensuring 10-Year Data Retention after 10⁷Erase/Write Cycles,” IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 40, NO. 11, November 1993, pp. 2011-2017).

[0009] According to these references, in order to increase the reliability of a MONOS memory cell, the total amount of charge of the holes passed through the tunnel oxide film and the number of holes accumulated after erasure have only to be decreased. To decrease the total number of holes passing through without changing the number of program and erase cycles, it is suggested that the difference (the threshold voltage window) between the programmed threshold voltage (the threshold voltage after writing) and the erased threshold voltage (the threshold voltage after erasing) have to be made smaller. In addition, to decrease the number of holes after erasure, it is suggested that the threshold value after erasure have to be made more positive.

[0010] However, this method has the following problem.

[0011] Let a state where electrons are accumulated in the charge accumulation layer be a written state. In this state, when the cell is left at it is for a long time, the accumulated electrons leak gradually into the silicon substrate via the thin tunnel oxide film. As a result, the threshold value of the cell lowers gradually. This might make it impossible to distinguish between the written state and the erased state. When the difference in threshold value between the written state and the erase state is small, the margin for such data collapse becomes small. A similar problem arises in a case where the threshold value of a cell in the erased state increases gradually to the extent that it cannot be distinguished from the written state.

[0012] Furthermore, when the erased threshold voltage is made positive and the threshold window is made constant, the written threshold voltage increases. As a result, the amount of negative charge in the charge storage (charge accumulation) electrode in the written state increases further. The increase in the amount of charge in the charge storage electrode makes it easier for the charge to escape from the charge storage electrode through its electric field, which adversely influences the charge retention characteristic.

[0013] Therefore, in the prior art, it is difficult to make the increase of the number of program and erase cycles compatible with the securing of a sufficient threshold margin for data collapse. Furthermore, an increase in the interface level when there is no hole accumulation has not been described and measures against the increase have not been disclosed in references 1 and 2.

[0014] On the other hand, a step-up writing method where a write voltage of Vpgm is increased gradually has been proposed by G. J. Hemink, et al., as a method of writing data into a conventional floating-gate NAND EEPROM (reference 3: “Fast and accurate programming method for multilevel NAND flash EERPOMs,” VLSI Tech. Dig., pp. 129-130, 1995). In a write operation (“0” program) in a floating-gate memory cell, a high-voltage write pulse Vpgm of about +15V to +25V is applied, with 0V being applied to the well and diffused layer, and a Flowler-Nordheim current (FN tunnel current) is caused to flow thorough the tunnel oxide film, electrons are injected from the channel into the floating gate to charge the floating gate negatively, and the threshold voltage of the memory cell is raised, which completes the write operation.

[0015] Using FIGS. 1 and 2, a step-up write operation will be explained. FIG. 2 schematically shows a write voltage pulse waveform applied to the control gate of a memory cell. First, a pulse with a write start voltage of Vpgm0 is applied to the control gage. Thereafter, a verify read operation to verify whether the memory cell has reached a desired threshold voltage is carried out. If the threshold voltage of the cell has not reached the desired one, a write pulse with a voltage obtained by raising the write voltage by a step-up voltage of ΔVpgm is applied to the control gate and the write operation is carried out again. Then, the threshold voltage of the memory cell is verified in a verify operation. Thereafter, a write operation to apply a voltage stepped up in ΔVpgm increments to the control electrode of the memory cell and a verify operation are repeated until the memory cell has exceeded a desired threshold voltage of Vverify.

[0016] FIG. 1 shows the change of a drain-current (Id)-gate-voltage (Vg) characteristic of a floating-gate memory cell when writing is done by raising a write pulse voltage of FIG. 2 in ΔVpgm increments and applying the voltage a plurality of times. In FIG. 1, Ith indicates the drain current value of a memory cell producing a threshold voltage. As shown in FIG. 1, in the prior art, the write pulse voltage Vpgm0 is applied to a memory cell with an erased threshold voltage of Vthe, with the result that the threshold voltage of the memory cell rises close to the write threshold voltage significantly. Furthermore, each time a pulse ΔVpgm higher in voltage than the preceding one is applied, the Id-Vg curve shifts in parallel in ΔVth (Pgm) steps toward the high-voltage side. That is, each time a pulse ΔVpgm higher in voltage than the preceding one is applied, the threshold voltage of the memory cell rises in ΔVth (Pgm) steps.

[0017] The threshold voltage change ΔVth (pgm) becomes larger, as the step-up voltage ΔVpgm becomes higher. According to a detailed analysis based on “Flash Memory Technical Handbook,” pp. 176-178, 1993, compiled by Fujio Masuoka, it goes as follows. It is assumed that the gate length is L_G, the channel width is W, the total capacitance of the floating gate electrode is Ctot, the thickness of the tunnel oxide film is tox, the electric field of the tunnel oxide film at time t is Eox (t), α and β are invariables. It is also assumed that the density of tunnel current satisfies the expression aα[Eox(t)]²×exp[−β/Eo x(t)] and each write pulse duration is tpgm. It is further assumed that the charge density of a surface depletion layer is Q_B, the inversion potential is 2φ_F, the equivalent gate capacitance per unit area measured from the channel is Ceff, the channel potential in programming is Vchannel, and the control gate voltage in programming is V_CG. Under these conditions, the dependence Vth(t) of the threshold voltage on the write time when a constant voltage of V_CGat t=0 is given by equation (1): 1 $\begin{matrix} Vth (t) = 2 φ_{F} - Q_{B} <
mo>/ Ceff + V_{G
G} - Vchannel - (Ctot \cdot tox) β / {Cpoly \cdot In [(L_{G} W  α β / Ctot \cdot tox <
mo>) t + \exp [β <
mo>/ Eox (o)]]} & (1) \end{matrix}$ embedded image

[0018] Here, in a write operation, the channel potential Vchannel can be considered almost constant in the inverted state. Therefore, the difference ΔVpgm in the control gate voltage in writing is equal to the difference ΔVth(pgm) in the increase in the threshold voltage in a specific time within an error of ±10% under the condition that equation (2) holds:

tpgm≧< /highlight>6×[(tox·Ctot)/(L _GWαβ)]×exp{β/Eox(0)} (2)

[0019] In an ordinary floating-gate memory cell, to hold the control gate voltage in writing low, the coupling ratio Cl/Ctot (where Cl is the capacitance between the control gate and the floating gate) is designed to be 0.5 or more. At this time, if the permittivity of the oxide film is εox, the electric field of the tunnel oxide film meets the following expression:

(tox·Ctot)/(L_GW)εox/{1−(Cl/Ctot)}≧6. 9×10⁻¹¹[F/m]

[0020] Furthermore, in the case of FN tunnel current in a cell using a polycrystalline silicon floating-gate electrode, the following equations are fulfilled:

α=3.2×10⁻⁶ [A/V²], β=2.4×10¹⁰[V/m]

[0021] Therefore, it follows that, with Eox (0)≧11.5 [MV/cm], tpgm satisfies equation (2) in the range of a write pulse duration equal to or longer than 6.2×10⁻⁶[s], and that ΔVth (pgm) can be considered almost equal to ΔVpgm in the practical operation range using a write electric field of 11.5 [MV/cm] and a pulse duration of 6.2 μs or longer.

[0022] FIG. 3 shows, in more detail, the change of the threshold voltage of a memory cell in fast and slow writing, using the writing method of FIG. 1 is applied. The figure is based on the assumption that a write and erase threshold voltage distribution as shown in FIG. 4 holds. In FIG. 4, it is assumed that the erase threshold voltage has a spread that has Vthel as the lower limit and Vtheh as the upper limit and is broader than the distribution of the write threshold voltage.

[0023] In a conventional floating-gate NAND flash memory, the threshold voltage after erasure may be negative. Immediately after erasure, the threshold voltage has a distribution width equal to or greater than 2V. For example, Vthel is set in the range from −4V to −2V and Vtheh is set in the range of from −2V to 0V. In the threshold voltage immediately after writing, the threshold voltage distribution width can be made smaller than the erase threshold voltage width (Vtheh−Vthel) because of a verify operation. Immediately after writing, the threshold voltage is set in the range that has Vverify as the lower limit and Vverify+ΔVth (pgm) as the upper limit.

[0024] In FIG. 3, white circles indicate a memory cell with the fastest write speed and black circles indicate a memory cell with the slowest write speed. Here, it is assumed that the cell with the fastest write speed has the upper limit Vtheh of the erase threshold as the initial erase threshold voltage and the cell with the slowest write speed has the lower limit Vthel of the erase threshold voltage as the initial erase threshold. However, even if the initial threshold voltage and the write speed are independent factors, the same reasoning holds because the condition of FIG. 3 is the worst one that will probably happen.

[0025] Traditionally, to reduce the number of write pulses and shorten the write time, Vpgm is set so as to be higher than the lower limit Vthw of the write threshold voltage in the memory cell with the fastest write speed. It is preferable that Vpgm be set so as to be in the range that has Vverify as the lower limit and Vverify+ΔVth (pgm) as the upper limit. Normally, Vverify is set, for example, 0.1 to 1V higher than the minimum setting value Vthw of the write threshold value, because the threshold voltage changes with time due to variations in the charge retention characteristic.

[0026] On the other hand, in the memory cell with the slowest write speed in FIG. 3, a first write pulse has a threshold voltage smaller than Vverify and a further write operation is carried out. Thereafter, the application of step-up pulses raises the threshold value of the memory cell in ΔVth (pgm) increments each time the number of write pulses increases. After a third write pulse is applied, the threshold voltage of the memory cell is a little lower than Vverify. Consequently, it is determined that the writing is insufficient and a fourth write operation is carried out with the result that the threshold voltage of the memory cell rises by ΔVth (pgm). This completes the write operation.

[0027] Even in the memory cell with the slowest write speed, immediately after the verify write operation, the threshold voltage is in the range that has Vverify as the lower limit and Vverify+ΔVth (pgm) as the upper limit. Although not shown in FIG. 3, even in memory cells with other write speeds, Vpgm is in the range that has Vverify as the lower limit and Verify+ΔVth (pgm) as the upper limit immediately after the verify write operation, with the result that Vpgm has a threshold distribution as shown in FIG. 4.

[0028] As seen from FIG. 3 and the above explanation, when ΔVpgm is made smaller to narrow the threshold distribution width, the number of pulses necessary for writing increases, depending on the number obtained by raising (Vtheh−Vthel)/ΔVpgm to an integer. This results in an increase in the write time.

[0029] In such a step-up write operation, as the step-up voltage ΔVpgm is made higher, the number of pulses necessary for writing decreases, which enables a higher-speed write operation. On the other hand, since the increment ΔVth(pgm) of the threshold voltage of the cell written into becomes almost equal to ΔVpgm, making ΔVpgm larger results in an increase in the threshold distribution width.

[0030] Furthermore, consider a case where Vpgm is set so as to be higher than the lower limit Vthw of the write threshold voltage in the memory cell with the fastest write speed to shorten the write time by reducing the number of write pulses. In this case, if Cl is the capacitance between the charge accumulation electrode and the control gate electrode and (Vth−V_FB) is the threshold voltage with no charge accumulation on the basis of the flat band voltage of the control electrode, the tunnel insulating film electric field when a first pulse is applied to the memory cell with the slowest write speed of FIG. 3 is expressed as equation (3) in the worst case:

{(Vpgm0−Vthel) +(Vth−V _FB)}×(Cl/Ctot)/tox (3)

[0031] That is, in the case of the memory cell with the fastest write memory cell of FIG. 3, a greater electric field than the one expressed by equation (3) is applied. As a result, the stress electric field causes a dielectric breakdown of the tunnel insulating film or an increase in the interface level or in the fixed charge traps, which result in the deterioration of the charge retention characteristic and a shift in the threshold voltage after writing and erasing are done repeatedly. This causes a reliability problem.

[0032] Furthermore, in a NAND EEPROM, when the data is read, a read pass voltage Vread is applied to the control gate of the memory cells unselected in reading. The memory cells unselected in reading must be on (conducting), regardless of the data state. Thus, Vread has to be a sufficiently higher voltage than the write threshold voltage. Therefore, when the threshold distribution width ΔVth of the cell written into is large, the pass voltage Vread must also be high.

[0033] As the pass voltage Vread gets higher, the threshold value of the memory cell rises due to Vread stress during the read operation, with the result that the cells can change their state from the erased state (or the state with a low threshold voltage) to the written state (or the state with a high threshold voltage). That is, when making ΔVpgm larger increases ΔVth, it is necessary to raise Vread, which decreases the reliability of the memory cells.

[0034] Moreover, in cells written into too high threshold voltage, the number of charges passing through their gate electrode film is large, which causes the problem of degrading the gate insulating film due to repetitive rewrite operations.

[0035] For the above reasons, it is difficult to make a high-speed write operation compatible with high reliability (a narrow threshold width). To solve this problem, a method of setting the step-up voltage ΔVpgm to two or more values by switching modes according to the application has been proposed (as disclosed in U.S. Pat. Nos. 6,031,760 or 6,108,238). With this method, a mode with a large ΔVpgm can be used when the application of memory cells requires a high-speed write operation, whereas a mode with a small ΔVpgm can be used when the application of memory cells requires high reliability (a narrow threshold width).

[0036] In this method, however, either the high-speed write operation or the narrow threshold distribution is given priority by mode selection, but both of them cannot be satisfied at the same time.

[0037] As described above, with the conventional MONOS cell, it is difficult to make the increase in the number of repeatable rewrite operations compatible with securing a threshold margin for data collapse. Furthermore, in the conventional floating-gate cell step-up writing method, it is not clear how the step-up voltage ΔVpgm is set to make high-speed writing compatible with high reliability (or a narrow threshold distribution). Therefore, a nonvolatile semiconductor memory using a step-up writing method capable of making high-speed writing compatible with high reliability has been needed. In addition, a step-up writing method capable of increasing the number of repeatable rewrite operations without degrading the threshold margin was also needed.

BRIEF SUMMARY OF THE INVENTION

[0038] According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising: a semiconductor substrate; a cell array which is configured by arranging a plurality of electrically writable erasable nonvolatile memory cells on the semiconductor substrate, each of the memory cells having a gate insulating film including a stacked structure of a tunnel insulating film and a charge accumulation insulating film, and a gate electrode formed on the gate insulating film; and a control circuit which controls write operation and erase operation of a memory cell selected in the cell array and which has an operation mode in which a sequentially stepped-up pulse voltage is applied between the gate electrode and the semiconductor substrate in at least one of the write operation and the erase operation.

[0039] According to another aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising: a semiconductor substrate; a cell array which is configured by arranging a plurality of electrically writable erasable nonvolatile memory cells on the semiconductor substrate, each of the memory cells including a charge accumulation layer formed on a first gate insulating film, a second gate insulating film on the charge accumulation layer, and a gate electrode on the second gate insulating film; and a control circuit which controls the sequence of writing and erasing data into and from a memory cell selected in the cell array and which has a write operation mode including a first operation of applying sequentially a write pulse voltage with a first step-up voltage between the gate electrode and the semiconductor substrate and a second write operation of applying a write pulse voltage with a second step-up voltage lower than the first step-up voltage in writing the data into the memory cell.

[0040] According to another aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising: a semiconductor substrate; a cell array which is configured by arranging a plurality of electrically writable erasable nonvolatile memory cells on the semiconductor substrate, each of the memory cells including a charge accumulation layer made of a conductive material film formed on a first gate insulating film, a second gate insulating film on the charge accumulation layer, and a gate electrode on the second gate insulating film, the second gate insulating film including a lower insulating film, an upper insulating film and a middle insulating film located therebetween, the lower insulating film being thinner than the upper insulating film; and a control circuit which controls the sequence of writing and erasing data into and from a memory cell selected in the cell array and which has an erase operation mode in which a sequentially stepped-up pulse voltage is applied between the gate electrode and the semiconductor substrate in erasing the data from the memory cell.

[0041] According to another aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising: a semiconductor substrate; a cell array which is configured by arranging a plurality of electrically writable erasable nonvolatile memory cells on the semiconductor substrate, each of the memory cells having a gate insulating film including a stacked structure of a tunnel insulating film and a charge accumulation insulating film, and a gate electrode on the gate insulating film; and a control circuit which controls the sequence of writing and erasing data into and from a memory cell selected in the cell array and which has an erase operation mode in which a first erase pulse defined by a first voltage and a first pulse width is applied between the gate electrode and the semiconductor substrate and thereafter applying a second erase pulse defined by a second voltage smaller in absolute value than the first voltage and a second pulse width greater than the first pulse width in erasing the data from the memory cell.

[0042] According to another aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising: a memory cell array which is configured by arranging a plurality of electrically rewritable nonvolatile semiconductor memory cells in a matrix, each of the memory cells having a control gate and a charge accumulation layer; a write circuit which writes data by applying a write voltage to the control gate of a memory cell selected in the memory cell array; and a verify circuit which is connected to the selected memory cell and which senses the threshold voltage of the memory cell each time the write voltage is generated and verifies whether the threshold voltage has reached a specific value, wherein each time a write operation is carried out, the write voltage outputted from the write circuit is increased in such a manner that the increment of a first write voltage between a first write operation and a second write operation is larger than the increment of a second write voltage between the second write operation and a third write operation and the increments of the second and later write voltages are constant.

[0043] According to another aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising: a memory cell array which is configured by arranging a plurality of electrically rewritable nonvolatile semiconductor memory cells in a matrix, each of the memory cells having a control gate and a charge accumulation layer; a write circuit which writes data by applying a write voltage to the control gate of a memory cell selected in the memory cell array; and a verify circuit which is connected to the selected memory cell and which senses the threshold voltage of the memory cell each time the write voltage is generated and verifies whether the threshold voltage has reached a specific value, wherein the write voltage outputted from the write circuit is such that a first write time is shorter than a second and later write times and the second and later write times are the same and that a second and later write voltages increase in a specific increment each time a write operation is carried out.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

[0044] FIG. 1 shows a drain-current-gate-voltage characteristic in writing data into a floating-gate memory cell;

[0045] FIG. 2 shows a data write operation waveform in a floating gate memory cell;

[0046] FIG. 3 is a characteristic diagram showing the relationship between the number of write pulses and the change of the threshold in a floating-gate memory cell;

[0047] FIG. 4 shows a data threshold distribution in a floating-gate memory cell;

[0048] FIGS. 5A and 5B are sectional views of a MONOS memory cell according to a first embodiment of the present invention;

[0049] FIG. 6 shows a write operation waveform in the first embodiment;

[0050] FIG. 7 is a flowchart for write sequence in the first embodiment;

[0051] FIG. 8 is a characteristic diagram showing the relationship between the number of write pulses and the change of the threshold in a memory cell in the first embodiment;

[0052] FIG. 9 shows a change in the threshold distribution in writing data into a memory cell in the first embodiment;

[0053] FIG. 10 shows a write operation waveform in a modification of the first embodiment;

[0054] FIG. 11 is a characteristic diagram showing the relationship between the number of write pulses and the change of the threshold in a memory cell in a modification of the first embodiment, together with a comparative example;

[0055] FIG. 12 is a characteristic diagram showing the relationship between the injection of holes from the bottom oxide film and an increase in the interface level in a MONOS memory cell;

[0056] FIG. 13 is a characteristic diagram showing the relationship between the flat band voltage after erasing and an increase in the interface level in a MONOS memory cell;

[0057] FIG. 14 shows a write operation waveform in a second modification of the first embodiment;

[0058] FIG. 15 shows a write operation waveform in a third modification of the first embodiment;

[0059] FIG. 16 is a sectional view of a floating gate memory cell according to a second embodiment of the present invention;

[0060] FIG. 17 shows an erase operation waveform according to the second embodiment;

[0061] FIG. 18A is a flowchart for data erase sequence in the second embodiment;

[0062] FIG. 18B is a flowchart for erase operation;

[0063] FIG. 19 is a diagram showing the change of the threshold distribution in erasing the data in a memory cell in the second embodiment;

[0064] FIG. 20 shows an erase operation waveform in a first modification of the second embodiment;

[0065] FIG. 21 shows an erase operation waveform in a second modification of the second embodiment;

[0066] FIG. 22 shows a write operation waveform in a third embodiment of the present invention using a MONOS memory cell;

[0067] FIG. 23 is a flowchart for write sequence in the third embodiment;

[0068] FIG. 24 is a diagram to help explain the data threshold distribution of a memory cell in the third embodiment;

[0069] FIG. 25 shows a drain-current-gate-voltage characteristic in writing data in the third embodiment;

[0070] FIG. 26 shows the relationship between the number of write pulses and the change of the threshold in a memory cell in the third embodiment;

[0071] FIG. 27 is a diagram to help explain the data threshold distribution of a memory cell in the third embodiment;

[0072] FIG. 28 is a sectional view to help explain the relationship between biases in writing data into a memory cell in the third embodiment;

[0073] FIG. 29 shows a potential distribution in a gate insulating film in a write operation in the third embodiment;

[0074] FIG. 30 is a diagram to help explain an electric field distribution in an ONO film in a write operation in the third embodiment;

[0075] FIG. 31 is sectional views to help explain a state where charges are accumulated in a memory cell in the third embodiment;

[0076] FIG. 32 shows an equivalent circuit of a memory cell in the third embodiment;

[0077] FIG. 33 is a diagram showing the number of write pulses and the change of the threshold in a memory cell in the third embodiment;

[0078] FIG. 34 is a drain-current-gate-voltage characteristic in writing data in the third embodiment;

[0079] FIG. 35A shows a structure of an edge of a memory cell in the third embodiment;

[0080] FIG. 35B shows another structure of an edge of a memory cell in the third embodiment;

[0081] FIG. 35C shows another structure of an edge of a memory cell in the third embodiment;

[0082] FIG. 36A shows an erase operation waveform according to a fourth embodiment of the present invention;

[0083] FIGS. 36B to 36E are flow charts for the erase operation;

[0084] FIG. 37 is a diagram showing the relationship between the erase time and the change of the threshold in a memory cell in the fourth embodiment;

[0085] FIG. 38 shows the configuration of an EEPROM according to a fifth embodiment of the present invention;

[0086] FIG. 39A is an equivalent circuit diagram of a NAND cell unit;

[0087] FIG. 39B is a plan view of FIG. 39A;

[0088] FIG. 40A is a sectional view taken along line 40A-40< /bold>A′ of FIG. 39B in the case of a MONOS memory cell;

[0089] FIG. 40B is a sectional view taken along line 40B-40< /bold>B′ of FIG. 39B in the case of the MONOS memory cell;

[0090] FIG. 41A is a sectional view taken along line 41A-41< /bold>A′ of FIG. 39B in the case of a floating-gate memory cell;

[0091] FIG. 41B is a sectional view taken along line 41B-41< /bold>B′ of FIG. 39B in the case of the floating-gate memory cell;

[0092] FIG. 42 is a diagram to help explain the way of selecting a memory cell in a write operation in the fifth embodiment;

[0093] FIG. 43 is a timing chart for a write operation in the fifth embodiment;

[0094] FIGS. 44A and 44B are another timing charts for a write operation in the fifth embodiment;

[0095] FIG. 45 shows an AND memory cell array;

[0096] FIG. 46 shows a NOR memory cell array;

[0097] FIG. 47 shows a virtual-grand-array-type cell array;

[0098] FIG. 48 shows the relationship between the number of write operations and the write voltage in the prior art;

[0099] FIG. 49 shows a threshold voltage distribution in a memory cell after a first write operation in the prior art;

[0100] FIG. 50 shows a threshold voltage distribution in the memory cell after a second write operation in the prior art;

[0101] FIG. 51 shows a threshold voltage distribution in the memory cell after a third write operation in the prior art;

[0102] FIG. 52 shows a threshold voltage distribution in the memory cell after a fourth write operation in the prior art;

[0103] FIG. 53 schematically shows the configuration of a semiconductor nonvolatile semiconductor memory device according to the present invention;

[0104] FIG. 54 is a schematic circuit diagram showing the configuration of the memory cell array shown in FIG. 53;

[0105] FIG. 55 shows the relationship between the number of write operations and the write voltage according to a sixth embodiment of the present invention;

[0106] FIG. 56 shows a threshold voltage distribution of memory cells after a first write operation in the sixth embodiment;

[0107] FIG. 57 shows a threshold voltage distribution of the memory cells after a second write operation in the sixth embodiment;

[0108] FIG. 58 shows a threshold voltage distribution of the memory cells after a third write operation in the sixth embodiment;

[0109] FIG. 59 shows a threshold voltage distribution of the memory cells after a fourth write operation in the sixth embodiment;

[0110] FIGS. 60A and 60B show the relationship between a threshold voltage distribution width and the number of bits in the prior art and that in the sixth embodiment, respectively;

[0111] FIG. 61 shows a threshold voltage distribution of memory cells after a first write operation in one other conventional equivalent;

[0112] FIG. 62 shows a threshold voltage distribution of the memory cells after a second write operation in the one other conventional equivalent;

[0113] FIG. 63 shows a threshold voltage distribution of the memory cells after a third write operation in the one other conventional equivalent;

[0114] FIG. 64 shows a threshold voltage distribution of the memory cells after a fourth write operation in the one other conventional equivalent;

[0115] FIG. 65 shows the relationship between the number of write operations and the write voltage in a seventh embodiment of the present invention;

[0116] FIG. 66 shows the relationship between the number of write operations and the write voltage in an eighth embodiment of the present invention; and

[0117] FIG. 67 shows the relationship between the number of write operations and the write voltage in a ninth embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0118] Hereinafter, referring to the accompanying drawings, embodiments of the present invention will be explained.

[0119] [First Embodiment]

[0120] A MONOS flash memory according to a first embodiment of the present invention will be explained. In a MONOS cell, if the captured charge centroid is in a place a distance of tox equivalent to oxide film thickness from the semiconductor substrate, the electric field in the tunnel oxide film is Eox, the capacitance between the captured charge centroid and the gate electrode is Cl, and the sum of the capacitance between the charge centroid and the control gate and the capacitance between the charge centroid and the semiconductor substrate is Ctot, these reference symbols can be considered in the same manner as those in a conventional floating-gate memory cell.

[0121] It is well known that writing data into a MONOS cell (that is, injecting electrons) can be expressed in FN tunnel current as into a floating-gate cell (reference 4: “Scaling of Multidieledtric Nonvolatile SONOS Memory Structures,” M. L. French and M. H. White, Solid State Electronics Vol. 37, No. 12, 1994, pp. 1913-1923). According to equation (25) in reference 4, in a MONOS cell whose tunnel oxide film is thinner than, for example, 3 nm, the tunnel current density is expressed as α[Eox(t)]²×exp[−β/Eox (t)], where α=3.2×10⁻⁶[A/V²] and β=1.6×10¹⁰[V/m].

[0122] If the equivalent oxide film thickness of the tunnel insulating film is toxeq, the equivalent oxide film thickness of the charge accumulation insulating film is tNeq, and the equivalent oxide film thickness of the block insulating film is tboxeq, (tNeq+tboxeq)/(toxeq+tNeq+tboxeq) is made 0.9 or less in an ordinary MONOS to suppress the write voltage of the control gate to a low level. Under this condition, the coupling ratio of Cl/Ctot=1−(tNeq+tboxeq)/(toxeq+tNeq+tboxeq) becomes 0.1 or more.

[0123] As described earlier, according to an analysis based on “Flash Memory Technical Handbook,” pp. 176-178, 1993, compiled by Fujio Masuoka, it is assumed that the gate length is L_G, the channel width is W, the electric field at time t in the tunnel oxide film is Eox(t), α and β are invariables, the tunnel current density is expressed as α[Eox(t)]²×exp[−/Eox(t )], and each write pulse width (or duration) is tpgm. It is also assumed that charge density of a surface depletion layer in a write operation is Q_B, the inversion potential is 2φ_F, the equivalent gate capacitance per unit area measured from the channel is Ceff, the channel potential in a write operation is Vchannel, and the control gate electrode voltage in a write operation is V_CG. Under these assumptions, the dependence Vth(t) of the threshold voltage on the write time when a specific voltage of V_CGis applied to the control gate at t=0 is expressed by equation (1) as described earlier.

[0124] The channel potential Vchannel in writing can be considered almost constant in the inverted state. As a result, the difference ΔVth(pgm) of the control gate voltage in writing is equal to the difference ΔVpgm of the increase in the threshold in a specific time within an error of ±10% under the condition where equation (2) holds.

[0125] Therefore, in the MONOS cell, when Eox(0)≧8 [MV/cm], it can be considered that equation (2) is satisfied in the write pulse duration range of tpgm≧2.2×10⁻⁶[s] and that ΔVth(pgm) is almost equal to ΔVpgm in the a practical operation range using a write pulse duration equal to or longer than 2.2 μs. When the tunnel oxide film is as thick as 3 nm or more and FN tunnel current caused by the tunnel insulating film is predominant, the same equation holds as in the prior art even in the MONOS cell. In addition, when Eox(0)≧11.5 [MV/cm], it can be considered that equation (2) is satisfied in the write pulse duration range of tpgm equal to or larger than 6.2×10⁻⁶[s] and that ΔVth(pgm) is almost equal to ΔVpgm in a practical operation range using a write pulse duration equal to or longer than 6.2 μs. It can be seen from equation (1) that ΔVth(pgm) increases as ΔVpgm becomes larger, regardless of the value of tpgm, when the initial charge state is the same.

[0126] The first embodiment is characterized in that, in a write operation, after a first write operation in which data is written with a weak electric field in such a manner that a write end decision voltage (or a verify voltage) Vverify has not been exceeded, data is written in a second write operation in such a manner that Vverify has been exceeded. Writing data into the MONOS memory cell by the method of the first embodiment makes it possible to increase the number of possible rewrite operations without degrading a threshold value margin for data collapse and write data at a high speed.

[0127] Furthermore, in the first embodiment, it is preferable that the step-up voltage in the first write operation is made higher or the write pulse width in the first write operation is made greater than those of the second embodiment. That is, the first embodiment is characterized in that two stages of step-up voltage are used in writing data into a memory cell and that its range and effect are clarified.

[0128] Use of the first embodiment makes it possible to increase the number of possible rewrite operations without degrading the threshold value margin even after writing and erasing are done repeatedly in writing data into a memory cell using an insulating film as a charge accumulation layer and write data at a high speed. Even when the writing method using two kinds of step-up voltage is applied to a floating-gate memory cell, the electric field applied to the inter-gate insulating film can be made smaller, which realizes a high reliability of the memory cells. Furthermore, the amount of change in the threshold voltage against the number of applications of write pulses can be made larger at the beginning of a write operation and made smaller at the end of the write operation. Therefore, it is possible to make a high-speed write operation compatible with a narrow threshold distribution, or a high reliability.

[0129] FIGS. 5A and 5B are sectional views taken along the channel width and along the channel length of a nonvolatile semiconductor memory cell in the first embodiment. In a cell array region of a silicon substrate 1, a p-type well 2 with, for example, a boron or indium impurity concentration of 10¹⁴(cm⁻³) to 10¹⁹(cm⁻³) is formed. In the p-type well 2, an element isolation insulating film 3 is formed to a thickness of about 10 to 500 nm. In the element region defined by the element isolation insulating film 3, a stacked gate insulating film including a charge accumulation layer is formed. The stacked gate insulating film is composed of a tunnel insulating film 4 composed of, for example, a silicon oxide film or silicon oxynitride film with a thickness of 0.5 to 10 nm, a charge accumulation layer 5 composed of a silicon nitride film with a thickness of 3 to 50 nm, and a block insulating film 6 composed of a silicon oxide film or silicon oxynitride film with a thickness of 3 to 30 (nm). It is preferable that the thickness of the tunnel insulating film 4 is 4 nm or less.

[0130] On the stacked gate insulating film, a control gate electrode 7 is formed. The control gate electrode 7 can be composed of an n-type or p-type polysilicon layer to which phosphorus, arsenic, or boron are heavily added. In this embodiment, however, the control gate electrode 7 has a stacked structure of a polysilicon layer 7a and a metal silicide layer 7b of 10 to 500 nm thickness. Not only WSi (tungsten silicide) but also NiSi, MoSi, TiSi, CoSi may be used as the metal silicide 7b. Alternatively, a polysilicon layer and a metal layer, such as Al or W, may be combined to form a stacked structure. On both sides of the gate electrode 7, n-type source-drain diffused layers 8 are formed.

[0131] The well 2, control gate electrode 7, and source-drain diffused layers 8 are each connected to electrode wires, which makes it possible to control voltages. Normally, the control gate electrode 7 is connected to a word line, one of the source-drain diffused layers 8 is connected to a bit line and the other is connected to a common source line.

[0132] To erase data, an erase voltage of Vera is applied to the well, with the control gate electrode 7 at 0V, thereby injecting holes from the semiconductor substrate via the tunnel insulating film into the charge accumulation layer 5, which shifts the threshold voltage of the memory cell in the negative direction. To read the data, the well 2 and source are set to 0V, a positive voltage is applied to the drain, and a decision voltage of Vref is applied to the gate electrode 7. In this state, whether the threshold voltage of the memory cell is higher or lower than Vref is determined, depending on whether current flows between the source and the drain. In this determination, data “0” (written state) and data “1” (erased state) are decided. The reading and erasing method may be a known method as disclosed in, for example, U.S. Pat. Nos. 6,031,760 or 6,108,238.

[0133] To write data, a high-voltage write pulse is applied to, for example, the gate electrode 7, with the well 2 and source-drain diffused layers 8 at 0V, thereby injecting electrons from the semiconductor substrate into the charge accumulation layer 5 via the tunnel insulating layer 4. In this way, the threshold voltage of the memory cell is shifted in the positive direction, thereby writing the data.

[0134] A write operation in the first embodiment will be explained concretely by reference to FIGS. 6 to 9.

[0135] FIG. 7 shows a write sequence. When write data is inputted in step S1, write control in step S2 to step S5 are performed automatically in the chip. In a first write pulse voltage applying operation (step S2), the data is written with a weak write electric field in such a manner that a write end decision voltage (or verify voltage) Vverify has not been exceeded. Thus, in the write operation, a verify read operation is not carried out. After the first write pulse applying operation (S2), a second write pulse voltage applying operation (step S3) is carried out. After the second write pulse voltage applying operation (S3), a verify read operation to determine the threshold is carried out (step S4), thereby determining whether all of the memory cells have been written into using the verify voltage Vverify (step S5). If any one of the memory cells has not been written into, the write pulse applying operation (S3) and the verify read operation (S4) are repeated until it has been written into.

[0136] FIG. 6 shows write pulses and the timing of a verify read operation. In a first write operation, a pulse with a write start voltage of Vpgm0′ [V] is applied and thereafter the write operation is repeated n times (n≧1) with the voltage raised in steps of a step-up voltage of ΔVpgm1 (=ΔVth(pgm1)). FIG. 6 shows the case of n=1 at which the first write operation is the simplest. After the first write operation is completed, all of the memory cells are such that their thresholds have not reached the write end decision voltage Vverify yet and a verify operation is not required, as described above.

[0137] Next, the step-up voltage is set to ΔVpgm2 (>Δpgm1) and a second write operation is started. In the second write operation, a verify read operation is carried out after a write pulse voltage is applied. After the verify read operation, if the desired threshold voltage has been reached, the write operation is ended. If the desired threshold voltage has not been reached, the write pulse voltage is further stepped up by ΔVpgm2 and the same operation is repeated.

[0138] In FIG. 8, a solid line shows the change of the threshold voltage in a step-up write operation in the first embodiment and a broken line shows a case in the prior art. The cell with the fastest write speed represented by a white circle has an erase threshold upper limit of Vtheh as the initial erase threshold and the cell with the slowest write speed represented by a black circle has an erase threshold lower limit value of Vthel as the initial erase threshold. Even if the initial threshold and the write speed are independent factors, the same reasoning holds because the condition is the worst one that will probably happen. Since a verify read operation is not carried out in the first write operation as described above, the time required to make a write end verify determination can be reduced.

[0139] The first write pulse voltage in the second write operation is set to Vpgm0, the first write pulse voltage in the first write operation is set to Vpgm0′, and the initial voltage Vpgm0′ is set in the range equal to or higher than 5V and equal to or lower than 20V. Specifically, taking the threshold distribution of FIG. 9 into account, when n=1, ΔVth(pgm1) is set to a voltage fulfilling the expression (Vverify−Vtheh)/2≦ΔVth(pgm1)≦(Verify+ΔVth(pgm2)−Vt heh)/2, and Vpgm0′=Vpgm0−ΔVth(pgm1) holds. The threshold voltage of the memory cell written into the earliest with the first write pulse is Vth1=Vtheh+ΔVth(pgm1) and the threshold voltage of the memory cell written into the latest is Vth2=Vthel+ΔVth(pgm1), which produces a distribution shown in FIG. 9.

[0140] Next, a second write pulse is applied. Since the increment of the second pulse voltage with respect to the first write pulse voltage is ΔVth(pgm1), the threshold voltage of the memory cell written into the earliest with the second write pulse is Vth1=Vtheh+2×ΔVth(pgm1), which lies in the range from Vverify and (Vverify+ΔVth(pgm2). This completes the write operation. On the other hand, the threshold voltage of the memory cell written into the latest is Vthe1+2×ΔVth(pgm1), which is equal to the threshold when the first pulse is applied as explained in the prior art.

[0141] Thereafter, a step-up voltage obtained by raising the preceding pulse by ΔVpgm2 (=ΔVth(pgm2), is applied, thereby carrying out a verify operation so as to place the write threshold voltage between Vverify and Vverify+ΔVth(pgm2). To realize the same threshold distribution as that in the prior art, setting is done to meet the equation ΔVth(pgm2)=ΔVth(pgm).

[0142] In the memory cell written into the latest in FIG. 8, if the total capacitance viewed from the charge accumulation layer is Ctot and the capacitance between the charge accumulation layer and the control gate electrode is Cl, the tunnel insulating film electric field when the first write pulse is applied to the memory cell written into the latest in FIG. 8 is expressed by the following equation in the worst case:

{(Vpgm0′−Vthel)+(Vth−V_FB)}×(Cl/Ctot< /italic>)/tox={(Vpgm0−ΔVth(pgm1)−Vthel)+(Vth−V_FB)}×(Cl/Ctot)/tox

[0143] In the case of FIG. 3, the tunnel insulating film electric field is smaller than the electric field {(Vpgm0−Vthel)+(Vth−V_FB)}×(Cl/Ctot)/tox by ΔVth(pgm1)×(Cl/Ctot)/tox.

[0144] On the other hand, the tunnel insulating film electric field when the second write pulse is applied to the memory cell written into the latest is expressed by the following equation in the worst case: 2 ${(Vpgm 0^{'} + Δ Vth <
mrow> (pgm1) <
mo>- (Vthe1 + Δ Vth <
mrow> (Pgm1) <
mo>+ (Vth - {<
mi>V}_{FB})) \times (C1 / Ctot) /tox = {(Vpgm �
� 0 - Δ Vth <
mrow> (pgm1) <
mo>- Vthe1) + (Vth - V_{FB})} \times (C1 /Ctot) / tox$ embedded image

[0145] That is, the tunnel insulating film electric field caused by the application of the second write pulse is equal to that by the application of the first write pulse. Therefore, in the application of any of the first and second write pulse, the tunnel insulating film electric field is smaller than the electric field {(Vpgm0−Vthel)+(Vth−V_FB)}×(Cl/Ctot)/tox by ΔVth(pgm1)×(Cl/Ctot)/tox. Therefore, dielectric breakdown of the tunnel insulating film caused by the stress electric field, or an increase in the interface level or in the fixed charge trap, are suppressed more than in the prior art. This alleviates the deterioration of the charge retention characteristic and reduces a shift in the threshold voltage after writing and erasing are done repeatedly, which therefore increases the reliability.

[0146] As comparative example 1, consider a case where as many write pulses as those in the first embodiment are applied, with ΔVth(pgm1)=ΔVth(pgm2). In comparative example 1, the tunnel insulating film electric field when a first write pulse is applied is (Vpgm0−Vth(pgm2)−Vthel)×(Cl/Ctot)/tox in the worst case. This means that, when ΔVth(pgm1)>ΔVth(pgm2), the electric field applied to the tunnel insulating film increases as compared with the first embodiment. In the first embodiment, the electric field applied to the tunnel insulating film of the memory cell written into the latest in the first application of a write pulse is made equal to that in the second application of a write pulse. Therefore, the first embodiment improves the reliability more than the comparative example. In this case, because the write pulse application cumulative time in the comparative example is the same as that in the first embodiment, there is no increase in the write time. Since the effect of increasing the reliability has been a new effect newly achieved by the inventors of this invention, it will be explained in detail later.

[0147] The step-up voltage ΔVpgm2 in the second write operation must be lower than the step-up voltage ΔVpgm1 in the first write operation, as described earlier. For example, the step-up voltage ΔVpgm2 is a voltage equal to or higher than 0.1V and equal to or lower than 2V. In the second write operation, when a third write pulse is applied to the memory cell written into the latest, the electric field of the tunnel insulating film is expressed by the following equation in the worst case: 3 ${(Vpgm 0 + Δ Vth <
mrow> (pgm2) <
mo>- (Vthe1 + 2 \times Δ <
mtext> Vth <
mrow> (Pgm1) <
mo>+ (Vth - {<
mi>V}_{FB})) \times (C1 / Ctot) /tox = {(Vpgm �
� 0 - Δ Vth <
mrow> (pgm1) <
mo>- Vthe1) + (Δ Vth <
mrow> (pgm2) <
mo>- Δ Vth <
mrow> (pgm1) <
/mrow>) + (V
th - V_{FB})} \times (C1 / Ctot <
mo>) / tox <
/mrow>$ embedded image

[0148] Thus, if the expression ΔVth(pgm2)<ΔVth(pgm1) is met, the tunnel insulating film electric field in the third application of a write pulse can be made smaller than that in the first or second application of a write pulse, which prevents the tunnel insulating film from deteriorating as compared with the first and second write pulses.

[0149] [Modification 1 of First Embodiment]

[0150] The case where a write pulse is applied only once in the first write operation has been explained. Next, a case where a pulse with a write start voltage of Vpgm0′ [V] is applied in the first write operation and thereafter a write operation is repeated a plurality of times (n>1) with a voltage raised in steps of the step-up voltage ΔVpgm1 will be explained.

[0151] FIGS. 10 and 11 correspond to FIGS. 6 and 8, respectively. A broken line in FIG. 11 shows the case of the comparative example (ΔVth(pgm1)=ΔVth(pgm2)).

[0152] As shown in FIG. 10, in modification 1, two write pulses are applied in the first write operation. During and after the first write operation, the thresholds voltages of all of the memory cells have not reached the write end decision voltage Vverify and therefore a verify operation is not needed. By doing this, the time required to make a write end verify determination can be reduced further. Here, when n>1, ΔVth(pgm1) is determined so as to satisfy the expression (Vverify−Vtheh)/(n+1)<ΔVth(pgm1)≦(Vverify+ΔVth(pgm2 )−Vtheh)/(n+1) and the expression ΔVth(pgm2)<ΔVth(pgm1).

[0153] It is assumed that the first write pulse voltage in the second write operation is Vpgm0 and the first write pulse voltage in the first write operation is Vpgm0′ where Vpgm0′=Vpgm0−n×ΔVth(pgm1). The threshold voltage of the memory cell written into the earliest with the first write pulse is Vtheh+ΔVth(pgm1). The threshold value of the memory cell written into the latest with the first write pulse is Vth2=Vthel+ΔVth(pgm1). As a result, a threshold distribution shown in FIG. 11 is obtained.

[0154] Next, a second write pulse is applied. An increment of the second write pulse with respect to the first write pulse is assumed to be ΔVth(pgm1). Consequently, the threshold voltage of the memory cell written into the earliest with the second write pulse is Vtheh+2×ΔVth(pgm1). The threshold value of the memory cell written into the latest with the second write pulse is Vth2=Vthel+2×ΔVth(pgm1). Up to now, it is apparent that all of the threshold voltages of the memory cells are smaller than Vverify. Therefore, a verify operation is not needed.

[0155] Furthermore, a third write pulse is applied. An increment of the third write pulse with respect to the second write pulse is also assumed to be ΔVth(pgm1). Consequently, the threshold voltage of the memory cell written into the earliest with the third write pulse is Vth1=Vtheh+3×ΔVth(pgm1), which is in the range of Vverify to [Vverify+ΔVth(pgm2)]. Then, the write operation is ended. On the other hand, the threshold of the memory cell written into the latest with the third write pulse is Vth2=Vthe1+3×ΔVth(pgm1), which is equal to the threshold when the first write pulse is applied as explained in the prior art.

[0156] Thereafter, a second write operation is started. A verify operation is carried out by applying a write pulse voltage in steps of the step-up voltage Δvpgm2(=ΔVth(pgm2) higher than in the first write operation in such a manner the write threshold voltage lies between Vverify and Vverify+ΔVth(pgm2). To realize the same write threshold distribution as that in the prior art, setting is done to satisfy ΔVth(pgm2)=ΔVth(pgm).

[0157] In the modification, the tunnel insulating film electric field when the first write pulse is applied to the memory cell written into the latest in FIG. 11 is expressed by the following expression in the worst case: 4 ${(Vpgm 0^{'} - Vthe1) <
mo>+ (Vth - {<
mi>V}_{FB})} \times (C1 / Ctot) /tox = {(Vpgm <
mstyle> 0 - n \times Δ Vth <
mo>(pgm1) - Vthe1) + (Vth - V_{FB})} \times (C1 / Ctot) / tox$ embedded image

[0158] This is smaller than the electric field {(Vpgm0−Vthel)+(Vth−V_FB)}×(C1/Ctot)/tox in FIG. 3 by n×ΔVth(pgm1)×(C1/Ctot)/tox.

[0159] On the other hand, the tunnel insulating film electric field when the second and later write pulses are applied to the memory cell written into the latest in the first write operation is expressed by the following expression in the worst case:

{(Vpgm0−n×ΔVth(pgm1)−Vthel)+(Vt h−V_FB)}×(C1 /Ctot)/tox

[0160] That is, the tunnel insulating film electric field is equal to that caused by the first write pulse. As a result, in the first write operation, the tunnel insulating film electric field is smaller than the electric field {(Vpgm0−Vthel)+(Vth−V_FB)}×(C1/Ctot)/tox in FIG. 3 by n×ΔVth(pgm1)×(C1/Ctot)/tox in any pulse application.

[0161] Therefore, a dielectric breakdown of the tunnel insulating film caused by the stress electric field or an increase in the interface level or in the fixed charge trap are suppressed more than in the prior art. This alleviates the deterioration of the charge retention characteristic and reduces a shift in the threshold value after writing and erasing are done repeatedly, which therefore increases the reliability. Furthermore, when n>1, the electric field applied to the tunnel insulating film is decreased by [n/(n+1)]×(C1/Ctot)/tox as compared with when n=1, which improves the reliability further.

[0162] In FIG. 11, a broken line shows comparative example 2 of applying as many write pulses as in the modification assumed to be ΔVth(pgm1)=ΔVth(pgm2). In this comparative example, the tunnel insulating film electric field when the first write pulse is applied is expressed as (Vpgm0−2×ΔVth(pgm2)−Vthel)×(C1/Ctot)/tox in the worst case. When ΔVth(pgm1)>ΔVth(pgm2), the electric field applied to the tunnel insulating film increases as compared with the modification. This can be seen from the fact that the threshold value shift from a write pulse being 0 to a write pulse being 1 in FIG. 11 in comparative example 2 (represented by a broken line) is larger than that in the modification (represented by a solid line). In this modification, the tunnel insulating film electric field of the memory cell written into the latest in the first application of a write pulse is made equal to that in the second application of a write pulse. Consequently, writing is done at the same speed as in comparative example 2, which improves the reliability further.

[0163] The reason why the reliability is improved in the embodiment found by the inventor of this invention will be explained in detail below.

[0164] The inventor examined the relationship between the write voltage and the number of possible rewrite operations in a MONOS memory cell using a charge accumulation insulating film, paying attention to an increase in the interface level of the interface between the semiconductor substrate and the tunnel oxide film. In a memory cell using a charge accumulation insulating film, electrons are injected into the insulating film in a write operation and holes are injected into the insulating film in an erase operation. In the prior art, the total amount of holes injected was considered to be the possible cause of an increase in the surface level as described in reference 1. The inventor examined the dependence on the write condition in a write operation where electrons are injected.

[0165] FIG. 12 shows the data obtained by the inventor, with the abscissa axis representing the total amount of charges injected into the charge accumulation layer and the ordinate axis representing an increase in the interface level after writing and erasing are alternated repeatedly (after the endurance test). The abscissa axis shows the cumulative amount of charges injected into the charge accumulation layer. The coincidence of the abscissa axis with another means that the product Qp of the amount of the injected charges in one round of write and erase operations multiplied by the number of repetitions is the same. The ordinate axis represents, in percent, (Vth−V_FB) normalized after the endurance by using the difference between the threshold voltage Vth with no accumulated charge before the repetition of write and erase operations and the flat band voltage V_FB.

[0166] In the figure, a black circle (), a white circle (◯), and a triangle (▴) represent cases where writing was done with Vpgm=11, 13, and 15 [V], respectively, while the erase voltage and the conditions were unchanged. In FIG. 12, the sample points show that the write voltage and the number of write and erase operations differ in the same structure shown in the embodiment. The tunnel insulating film was equal to or less than 4 nm, specifically as thick as lies in the range of 2 nm to 3 nm, which is a thickness that allows holes to be injected from the semiconductor substrate into the charge accumulation layer by the tunnel effect.

[0167] As seen from FIG. 12, use of the write voltage as a parameter enables an increase in the interface level to be expressed as a uniform function of Qp, without depending on the number of repetitions, the charge injection cumulative time, the amount of injected charges per round of write and erase operations. From the results, the inventors discovered that the interface level increases as the write voltage rises, even when the total amount Qp of the injected charges remains unchanged, and that the results differ from the results explained in reference 1.

[0168] FIG. 13 shows the relationship between the flat band voltage V_FBafter an erase operation and an increase in the interface level after the endurance test, in a case where the erase voltage condition and the erase pulse width condition are changed. The data shown in FIG. 13 was obtained by the inventor from experiments. In FIG. 13, the cumulative amount of charge of positive charges injected into the charge accumulation layer was fixed to 0.3 C/cm². With the write condition being fixed, the erase voltage condition and the pulse width condition were changed. The structure used for measurement was a MONOS structure using an n-type polysilicon gate electrode as a control electrode. The flat band voltage in the state where no charge was accumulated was in the range of −0.5V to −1V.

[0169] As seen from the result shown FIG. 13, the increase in the interface level decreases more as the flat band voltage rises after an erase operation, even when the flat band voltage after erasure is equal to or higher than −0.5V, that is, even in a state where no holes are accumulated in the erase operation. The dotted line in FIG. 13 represents a linear regression line obtained by the method of linear squares. However, a large change in the inclination of the increase in the interface level cannot be seen at about a flat band voltage of −0.5V after erasure. Therefore, with a model where the interface level is formed as a result of the holes in the charge accumulation layer flowing into the semiconductor substrate, the generation of the interface level in the present device cannot be explained comprehensively. This was what was discovered by the present inventors.

[0170] From the data in FIGS. 12 and 13, the inventors found that an increase in the interface level is a function of the total amount Qp of injected charges and the tunnel insulating film electric field Eox caused by the write pulse applied after erasure, which expresses an increase in the interface level uniquely. In qualitative terms, even when the total amount Qp of injected charges is the same, an increase in the interface level decreases more as the tunnel oxide film electric field Eox caused by the write pulse applied after erasure is smaller.

[0171] Specifically, it was found from FIG. 12 that, with the same total amount Qp of injected charges, when the voltage of the write pulse applied after erasure dropped by 1V, this corresponded to the fact that the maximum electric field of the tunnel oxide film dropped by 0.75 [MV/cm] and the increase in the interface level decreased to 1/1.3 of the original one. On the other hand, it was found that, when a comparison was made with the same increase in the interface level, a drop of 1V in the maximum voltage of the write pulse applied after erasure corresponded to a drop of 0.75 [MV/cm] in the maximum electric field of the tunnel oxide film and increased the Qp to about 1.7 times the original one. The increase in the interface level is determined by Qp and Eox, not by the charge injection cumulative time. Consequently, as compared with a conventional equivalent, there is no additional increase in the interface level in the first embodiment whose charge injection cumulative time differs from that in the conventional equivalent. This was a discovery.

[0172] As described in detail in the explanation of the tunnel oxide film electric field, when the write voltage is constant, the electric field applied to the tunnel oxide film is greater as the threshold value immediately before a write operation is smaller. That is, the threshold voltage Vth before a write operation is low, the voltage applied to the tunnel oxide film becomes the highest. Consequently, as in the first embodiment, making the write start voltage lower lowers the electric field applied to the tunnel oxide film. This makes it possible to increase the number of possible rewrite operations without degrading a threshold value margin for data collapse. Moreover, raising the write applied voltage gradually makes a write operation faster.

[0173] As described above, when an insulating film composed of, for example, a silicon nitride film is used as the charge accumulation layer, use of the first embodiment produces a first effect of improving the memory cells.

[0174] A second effect of the first embodiment is that a faster write operation is compatible with a narrow threshold distribution, or high reliability. In the first embodiment, the step-up voltage Δpgm1 in the first write operation and the step-up voltage ΔVpgm2 in the second write operation are set so as to fulfill the expression ΔVpgm1>ΔVpgm2. Since ΔVpgm1 is set larger at the beginning of a write operation, a variation in the threshold is large, which enables a sufficiently high-speed write characteristic to be realized. In the middle of the write operation, the step-up voltage decreases to ΔVpgm2, with the result that the maximum threshold of a memory cell written into with a voltage higher than the verify voltage becomes Vverify+ΔVth(pgm2). Furthermore, it is lower than the maximum write threshold value Vverify+ΔVth(pgm1) when the step-up voltage is not switched, with the result that the write threshold distribution width becomes narrower.

[0175] Therefore, this alleviates the following problem: the number of charges injected to the memory cells written into with a high threshold voltage becomes larger, decreasing the reliability in rewriting data repeatedly. As a result of overcoming the above problem, high reliability is realized. Furthermore, in a read operation in a NAND EEPROM, the voltage Vread applied to the gate electrode of an unselected memory cell can be made lower. This makes it possible to alleviate a variation in the threshold voltage caused by Vread stress.

[0176] A third effect of the first embodiment is that a write operation can be carried out faster because a verify operation is not carried out during the first write operation. For example, it is assumed that the write pulse application time is 20 μs and the verify read time is 20 μs and that the number of write operations in the first write operation is 5 and the number of write operations in the second operation is 5. Then, the total write operation time is 20 μs×5+(20 μs+20 μs)×5=300 μs. This is shorter than the total write time (20 μs+20 μs)×10=400 μs in carrying out a verify operation during the first write operation.

[0177] To shorten the write time, it is desirable that the number of write operations in the first write operation be made larger and the number of write operations in the second write operation be made smaller. That is, it is desirable that writing be done in the first write operation in such a manner that a threshold voltage as close to the verify voltage as possible is reached. On the other hand, if writing is done by applying a pulse a plurality of times without carrying out a verify operation, there is a strong possibility that abnormal cells written into excessively will appear. Such abnormal cells are considered to be attributable to local defects in the tunnel oxide film.

[0178] To avoid such a problem, it is desirable to use an insulating film as the charge accumulation layer. With the charge accumulation layer composed of an insulating film, even if there is a local defect in the tunnel oxide film, a large number of electrons are not injected through the defect, which prevents abnormal cells written into excessively from appearing. Therefore, since writing can be done close to the verify voltage in the first write operation where a verify read operation is not carried out, the second write operation can be shortened, which enables the write time to be shortened on the whole.

[0179] [Another Modification of First Embodiment]

[0180] FIGS. 14 and 15 show pulse waveforms in modification 2 and modification 3 of the first embodiment, respectively. In modification 2 of FIG. 14, a write pulse in the first write operation is a stepwise pulse stepped up continuously, not a discrete pulse with an idle time as in modification 1. Since a verify read operation is not needed in the first write operation, such an operation can be carried out. In modification 2, the write time of the first write operation can be shortened. Furthermore, to step up the pulse voltage continuously, the voltage has only to be made higher than the preceding pulse voltage by ΔVpgm1. It is not necessary to raise the pulse voltage from the ground potential GND as in a verify operation. Therefore, as shown in FIG. 14, the write pulse voltage can be made more stable than in the second write operation. In addition, the load on the step-up circuit that generates a write pulse voltage can be decreased, which leads to a reduction in the occupied area of the step-up circuit.

[0181] In modification 3 of FIG. 15, a write pulse in the first write operation is a triangular pulse stepped up linearly, not a discrete pulse. In this case, if the write pulse width in the second write operation is tpgm, the rate of increase in the triangular write pulse voltage is expressed as (ΔVpgm1/tpgm). In this modification, too, the program time in the first write operation can be shortened. Furthermore, to step up the pulse voltage continuously in the first write operation, the pulse voltage has only to be stepped up continuously at a low change rate of (ΔVpgm1/tpgm), which makes the pulse voltage more stable than in modification 2. In addition, the load on the step-up circuit can be made smaller and therefore the occupied area of the step-up circuit can be reduced.

[0182] In the first embodiment, when the write pulse width in the first write operation is made equal to the write pulse width in the second write operation, the time constant of the pulse width control circuit in the write voltage generator circuit can be made constant. This is preferable to simplifying the circuit. However, the step-up voltage of the write pulse voltage in the first write operation may be made equal to that in the second write operation and the write pulse width in the first write operation may be made greater than that in the second write operation. This configuration produces the same effect. That is, the amount of shift in the threshold in a write operation is calculated using equation (1) and the configuration is designed to meet the above-described condition so as to satisfy the expression ΔVth(pgm1)≧ΔVth(pgm12). This produces the same effect.

[0183] As described in detail, use of the write pulse applying method in the first embodiment enables the increase in the interface level to be reduced more than in a conventional equivalent. This also enables the current flowing from the silicon nitride film via the interface level to be reduced, which improves the retention characteristic of the MONOS element. The interface level has been used as a quantitative parameter of reliability. This has its origin in the formation of a dangling bond and a change in the bond angle at the interface, which is well known physically. It is also possible to suppress the charge trap generation caused by a similar origin, which improves the reliability.

[0184] In the first embodiment, the charge accumulation layer is an insulating film. Therefore, when a MONOS memory cell where the accumulated charge distribution in the charge accumulation layer is non-uniform is used and the step-up writing method is applied, this makes it possible to realize a narrow write threshold distribution unobtainable in a floating-gate memory cell.

[0185] Furthermore, use of the write sequence of switching the step-up voltage of a write pulse in two stages enables high-speed writing and improves the reliability without degrading the threshold value margin.

[0186] Specifically, a verify read operation after the application of a write pulse voltage is not carried out in the first write operation and a verify read operation to determine a threshold voltage after the application of each write pulse voltage is. carried out in the second write operation, which enables a high-speed write operation.

[0187] [Second Embodiment]

[0188] The effect of the first embodiment is not peculiar to the MONOS cell structure using an insulating film as a charge accumulation layer and is also expected even in a floating-gate cell structure with an ONO film intervening between a control gate electrode and a floating-gate electrode. The reason is that the ONO film has a stacked structure of a silicon oxide film, a silicon nitride film, and a silicon oxide film in that order and that the ONO film has the same stacked insulating film configuration as that of the stacked insulating film including the charge accumulation layer of a MONOS cell explained in the first embodiment.

[0189] When either the thickness of the upper oxide film of the ONO film or the thickness of the lower oxide film is decreased to 4 nm or less, an increase in the current flowing through the ONO film resulting from the injection of holes into the silicon nitride film is observed. This phenomenon has already been reported (reference 5: K. Kobayashi, H. Miyatake, J, Mitsuhashi, M. Hirayama, T. Higaki, H. Abe, VLSI Symp. Tech, Digest, pp. 119-120, 1990, see FIG. 3 in particular).

[0190] It is clear that, even in a floating-gate memory cell with an ONO film whose upper or lower oxide film is 4 nm or less in thickness, the injection of electrons or holes resulting from write and erase operations takes place at its ONO film as in the MONOS cell structure explained in the first embodiment. In an erase operation, the direction in which the voltage is applied to the ONO film is the opposite of that in a write operation. Therefore, when electrons and holes are injected into the upper and lower oxide films, it is important to secure reliability not only in a write operation shown in the first embodiment but also in an erase operation.

[0191] FIG. 16 is a sectional view of a memory cell with a floating-gate structure. On a semiconductor substrate 11, a p-type well 12 with, for example, a boron or indium impurity concentration of 10¹⁴(cm⁻³) to 10¹⁹(cm⁻³) is formed. In the p-type well 12, a tunnel insulating film 13 made of a silicon oxide film or silicon oxynitride film is formed to a thickness of about 3 to 15 nm.

[0192] On the tunnel insulating film 13, a floating gate 14 made of polysilicon to which, for example, phosphorus or arsenic has been added at a concentration of 10¹⁸(cm⁻³) to 10²¹(cm⁻³) is placed. On the floating gate 14, an interpoly insulating film (ONO film)