DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] There is provided by the present invention a method for fabricating a microelectronic inductor structure within a microelectronic fabrication, as well as the microelectronic inductor structure fabricated within the microelectronic fabrication while employing the method, wherein the microelectronic inductor structure is fabricated with enhanced performance.

[0026] The present invention realizes the foregoing object by employing when fabricating a microelectronic inductor structure within a microelectronic fabrication in accord with the present invention an annular magnetic shielding layer annularly surrounding a spirally patterned conductor layer which comprises a planar spiral inductor within the microelectronic inductor structure.

[0027] A microelectronic inductor structure fabricated in accord with the present invention provides particular value when fabricating an integrated circuit microelectronic fabrication which may be employed for higher frequency microelectronic fabrication applications, such as but not limited to wireless communications higher frequency microelectronic fabrication applications. However, a microelectronic inductor structure in accord with the present invention may be fabricated within a microelectronic fabrication selected from the group including but not limited to integrated circuit microelectronic fabrications, ceramic substrate microelectronic fabrications, solar cell optoelectronic microelectronic fabrications, sensor image array optoelectronic microelectronic fabrications and display image array optoelectronic microelectronic fabrications. Similarly, a microelectronic inductor structure in accord with the present invention may be employed within microelectronic fabrication applications including but not limited to higher frequency (i.e., greater than about 100 MHZ) microelectronic fabrication applications, mid range frequency (i.e., from about 100 MHZ to about 1000 MHZ) microelectronic fabrication applications and lower frequency (i.e., less than about 100 MHZ) microelectronic fabrication applications.

[0028] Referring now to FIG. 1 and FIG. 2 , there is shown a pair of schematic plan view diagrams illustrating the results of progressive stages in fabricating a microelectronic inductor structure in accord with a preferred embodiment of the present invention.

[0029] Shown in FIG. 1 is a schematic plan view diagram of the microelectronic inductor structure at an early stage in its fabrication in accord with the preferred embodiment of the present invention.

[0030] Shown in FIG. 1 is a dielectric substrate layer 60 having formed thereupon a spirally patterned conductor layer 12 which terminates in: (1) a first bond pad region 14 a integral to the spirally patterned conductor layer while employing an underpass to an interior section of the spirally patterned conductor layer 12 ; and (2) a second bond pad region 14 b integral to an exterior section of the spirally patterned conductor layer 12 . Within the schematic plan view diagram of FIG. 1 , the spirally patterned conductor layer 12 forms a planar spiral inductor 10 in accord with the present invention.

[0031] As is illustrated within the schematic plan view diagram of FIG. 1 , the spirally patterned conductor layer 12 is formed of a bi-directional outer spiral width W1 of from about 30 μm to about 500 μm, while similarly having a bi-directional inner spiral width W2 of from about 0 μm to about 30 μm which forms a central cavity defined by the spirally patterned conductor layer 12 .

[0032] Although not specifically illustrated within the schematic plan view diagram of FIG. 1 , at portions of the spirally patterned conductor layer 12 other than those within the first bond pad region 14 a and the second bond pad region 14 b of the spirally patterned conductor layer 12 , the spirally patterned conductor layer 12 is formed with a linewidth of from about 3 μm to about 30 μm. Similarly, at portions of the spirally patterned conductor layer 12 other than those within the first bond pad region 14 a and the second bond pad region 14 b of the spirally patterned conductor layer 12 , adjacent traces of the spirally patterned conductor layer 12 are separated by a separation width of from about 0.5 μm to about 15 μm. Finally, although the schematic plan view diagram of FIG. 1 illustrates the planar spiral inductor 10 of the present invention as being formed employing two and one half full turns in a nominally rectangular geometry, planar spiral inductor structures in accord with the present invention may be formed employing geometries including but not limited to triangular geometries, square geometries, rectangular geometries, higher order polygonal geometries, elliptical geometries and circular geometries having full turns ranging from about 1 to about 20.

[0033] Referring now to FIG. 2 , there is shown a schematic plan view diagram illustrating the results of further processing of the microelectronic inductor structure whose schematic plan view diagram is illustrated in FIG. 1 .

[0034] Shown in FIG. 2 is a schematic plan view diagram of a microelectronic inductor structure otherwise equivalent to the microelectronic inductor structure whose schematic plan view diagram is illustrated in FIG. 1 , but wherein, in a first instance, there is formed and planarized upon the planar spiral inductor 10 a patterned planarized intra coil dielectric layer 20 . Similarly, there is also shown within the schematic plan view diagram of FIG. 2 : (1) formed within the patterned planarized intra-coil dielectric layer 20 and within the central cavity defined within the center of the spirally patterned conductor layer 12 a magnetic core layer 16 ; and (2) formed within the patterned planarized intra-coil dielectric layer 20 and completely annularly surrounding the spirally patterned conductor layer 12 an annular magnetic shielding layer 18 .

[0035] Within the present invention and the preferred embodiments of the present invention, the magnetic core layer 16 provides an enhanced Q factor for a microelectronic inductor structure fabricated in accord with the present invention, while the annular magnetic shielding layer 18 provides for enhanced annular magnetic shielding of the planar spiral inductor 10 .

[0036] As is understood by a person skilled in the art, a Q factor of a microelectronic inductor structure is in general described in terms of a ratio of energy storage capacity within the microelectronic inductor structure with respect to power dissipation within the microelectronic inductor structure. Additional description of Q factor is disclosed within the related art references cited within the Description of the Related Art.

[0037] Within the present invention, the magnetic core layer 16 may be employed independently of the annular magnetic shielding layer 18 when fabricating a microelectronic inductor structure in accord with the present invention. Similarly, while the schematic plan view diagrams of FIG. 1 and FIG. 2 illustrate a microelectronic inductor structure in accord with the present invention formed while first fabricating the spirally patterned conductor layer 12 and then the magnetic core layer 16 in conjunction with the annular magnetic shielding layer 18 , alternative and reverse ordering of fabrication of the foregoing layers is also within the context of the present invention.

[0038] Referring now to FIG. 3 , there is shown a schematic cross-sectional diagram of a microelectronic inductor structure corresponding with the microelectronic inductor structure whose schematic plan view diagram is illustrated in FIG. 2 .

[0039] Shown within the schematic cross-sectional diagram of FIG. 3 is a semiconductor substrate 40 having formed therein a pair of isolation regions 42 a and 42 b which define an active region of the semiconductor substrate 40 . Similarly, there is also shown within the schematic cross-sectional diagram of FIG. 3 , and formed within and upon the active region of the semiconductor substrate 40 a series of structures which comprises a field effect transistor (FET) device. The series of structures which comprises the field effect transistor (FET) device includes: (1) a gate dielectric layer 44 formed upon the active region of the semiconductor substrate 40 , the gate dielectric layer having formed and aligned thereupon; (2) a gate electrode 46 , where the gate dielectric layer 44 and the gate electrode 46 further define; (3) a pair of source/drain regions 48 a and 48 b formed within the active region of the semiconductor substrate 40 at areas not covered by the gate dielectric layer 44 and the gate electrode 46 . Each of the foregoing layers and structures may be formed employing methods, materials and dimensions as are conventional in the art of semiconductor integrated circuit microelectronic fabrication.

[0040] Similarly, there is also shown within the schematic cross-sectional diagram of FIG. 3 : (1) a series of patterned pre-metal dielectric (PMD) layers 50 a , 50 b and 50 c formed upon the semiconductor substrate 40 having formed therein the pair of isolation regions 42 a and 42 b which define the active region of the semiconductor substrate in turn having formed therein the field effect transistor (FET) device, where the series of patterned pre-metal dielectric layers 50 a , 50 b and 50 c define a pair of vias which leave exposed the pair of source/drain regions 48 a and 48 b ; (2) a pair of conductor contact studs 52 a and 52 b formed into the pair of vias, the pair of conductor contact studs 52 a and 52 b having formed connected thereto a pair of patterned first conductor layers 54 a and 54 b ; and (3) a series inter-metal dielectric (IMD) layers 56 , 58 and 60 formed further passivating the pair of patterned first conductor layers 54 a and 54 b and the series of patterned pre-metal dielectric (PMD) layers 50 a , 50 b and 50 c.

[0041] Similarly with the semiconductor substrate 40 having formed therein and thereupon the field effect transistor (FET) device as illustrated within the schematic cross-sectional diagram of FIG. 3 , the foregoing conductor layers and dielectric layers may similarly also be formed employing methods, materials and dimensions as are conventional in the art of semiconductor integrated circuit microelectronic fabrication.

[0042] Finally, there is shown within the schematic cross-sectional diagram of FIG. 3 a pair of annular magnetic shielding layers 18 a and 18 b (representative of the annular magnetic shielding layer 18 as illustrated within the schematic plan view diagram of FIG. 2 ) having contained within their separation distance a series of spirally patterned conductor layers 12 a , 12 b , 12 c , 12 d , 12 e and 12 f (representative of the spirally patterned conductor layer 12 as illustrated within the schematic plan view diagram of FIG. 2 ), further having contained within their separation distance the magnetic core layer 16 (as is also illustrated within the schematic plan view diagram of FIG. 2 ). Within the schematic cross-sectional diagram of FIG. 3 , the foregoing series of layers is separated by a series patterned planarized intra coil dielectric layers 20 a , 20 b , 20 c , 20 d , 20 e , 20 f , 20 g , 20 h , 20 i and 20 j (representative of the patterned planarized intra coil dielectric layers 20 as illustrated within the schematic plan view diagram of FIG. 2 ).

[0043] As is illustrated within the schematic cross-sectional diagram of FIG. 3 , the pair of annular magnetic shielding layers 18 a and 18 b , as well as the magnetic core layer 16 , are formed of a thickness (typically and preferably from about 10000 to about 50000 angstroms) greater than the series of spirally patterned conductor layers 12 a , 12 b , 12 c , 12 d , 12 e and 12 f (which is typically and preferably from about 3000 to about 10000 angstroms). Such a thickness differential is, however, not required within the present invention. However, with respect to the magnetic core layer 16 there is provided enhanced performance of the microelectronic inductor structure whose schematic cross-sectional diagram is illustrated in FIG. 3 when the magnetic core layer 16 is formed of increased height in comparison with the series of spirally patterned conductor layers 12 a , 12 b , 12 c , 12 d , 12 e and 12 f . Similarly, with respect to the pair of annular magnetic shielding layers 18 a and 18 b , the pair of annular magnetic shielding layers 18 a and 18 b also provide enhanced magnetic shielding properties to the microelectronic inductor structure whose schematic cross-sectional diagram is illustrated in FIG. 3 when formed with enhanced height.

[0044] Within the preferred embodiment of the present invention with respect to the series of spirally patterned conductor layers 12 a , 12 b , 12 c , 12 d , 12 e and 12 f , the series of spirally patterned conductor layers 12 a , 12 b , 12 c , 12 d , 12 e and 12 f may be formed from any of several conductor materials as are conventional in the art of microelectronic fabrication for forming inductor structures within microelectronic fabrications, such conductor materials being selected from the group including but not limited to: (1) nonmagnetic metal and non-magnetic metal alloy (such as but not limited to aluminum, aluminum alloy, copper and copper alloy) conductor materials: (2) magnetic metal and magnetic metal alloy (such as permalloy and higher order alloys incorporating permalloy alloy) conductor materials; (3) doped polysilicon (having a dopant concentration greater than about 1E15 dopant atoms per cubic centimeter) and polycide (doped polysilicon/metal silicide stack) conductor materials; and (3) laminates thereof. Typically and preferably, each of the spirally patterned conductor layers 12 a , 12 b , 12 c , 12 d , 12 e and 12 f is formed at least in part of a nonmagnetic metal or metal alloy conductor material.

[0045] Similarly, within the preferred embodiment of the present invention, the magnetic core layer 16 and the pair of annular magnetic shielding layers 18 a and 18 b is typically and preferably formed of a ferromagnetic material, such as but not limited to a nickel cobalt alloy having a nickel content of from about 20 to about 60 weight percent and a cobalt content of from about 50 to about 70 weight percent ferromagnetic shielding material, formed to a thickness of from about 10000 to about 50000 angstroms. However, other ferromagnetic materials, such as but not limited to iron, cobalt, nickel ferromagnetic materials may also be employed for forming the magnetic core layer 16 and the pair of annular magnetic shielding layers 18 a and 18 b.

[0046] Upon forming the microelectronic fabrication whose schematic cross-sectional diagram is illustrated in FIG. 3 , there is formed a microelectronic fabrication having formed therein a microelectronic inductor structure with enhanced performance. The microelectronic inductor structure exhibits enhanced performance insofar as there is formed annularly surrounding a planar spiral inductor within the microelectronic inductor structure an annular magnetic shielding layer.

[0047] As is understood by a person skilled in the art, the preferred embodiment of the present invention is illustrative of the present invention rather than limiting of the present invention. Revisions and modifications may be made to methods, materials, structures and dimensions through which is fabricated a microelectronic inductor structure in accord with the preferred embodiment of the present invention while still fabricating a microelectronic inductor structure in accord with the present invention, further in accord with the appended claims.