DETAILED DESCRIPTION

[0084] In what follows, we describe approaches that are useful to identify and characterize areas of a chip that are likely to be problematic due to predicted variation in film thickness, surface topography uniformity, and electrical impact resulting from pattern dependencies during processing of an integrated circuit. The approaches are applicable to the high density plasma (HDP) and chemical-mechanical polishing (CMP) processes used in the formation of shallow trench isolation (STI) structures, as well as the electroplated copper deposition (ECD) and chemical mechanical polishing (CMP) processes used in the formation of single- and multi-level interconnect structures for integrated circuit (IC) devices. The approaches are also applicable to the processes and flows used to create oxide and low-k dielectric layers. The approaches are also applicable to plasma-etch processes and the measurement of critical dimensions. The approaches are also applicable to lithography processes. The approaches are also applicable to any step or steps that constitute damascene process flows. The approaches assemble the locations or coordinates of problematic areas into measurement plans and may also generate measurement recipes for used by metrology tools.

[0085] In fabricating integrated circuits, interconnect film thickness and surface topography uniformities are dependent on variation in circuit layout patterns (e.g. material density, linewidth and linespace). Surface non-uniformity often leads to subsequent manufacturability and process integration issues. These pattern dependencies may also affect device performance by introducing variation in capacitance and resistance depending on the location of a given structure on the device.

[0086] Film thickness variation in chemical mechanical polishing (CMP) processes can be separated into various components: lot-to-lot, wafer-to-wafer, wafer-level, and die-level. Often, the most significant component is the pattern dependent die-level component. Die-level film thickness variation is often due to differences in layout patterns on the chip. For example, in the CMP process, differences in the underlying metal pattern result in large long-range variation in the post CMP film thicknesses, even though a locally planar surface topography is achieved.

[0087] For oxide polishing, the major source of variation is caused by within-die pattern density 2 , shown as two groups of metal lines in FIG. 2A . The metal lines 501 on the left side of FIG. 2A have a lower density in the directly of the plane of the integrated circuit than do the metal lines 502 on the right side of the figure. Pattern density, in this case, is the ratio of raised oxide area 503 divided by the total area of the region. The region may be taken as a square with the length of the sides equal to some length, the planarization length. The planarization length is usually determined by process factors such as the type of polishing pad, CMP tool, slurry chemistry, etc.

[0088] FIG. 2D illustrates an example of how the underlying feature density affects the film thickness variation. FIG. 2E plots the film thickness variation corresponding to each density type. For a given square area defined by planarization length 521 , the higher the underlying feature density leads to larger film thickness variation 523 and the lower the underlying feature density leads to a reduced film thickness 524 . Designers often try to maintain density tightly around 50% 522 to promote planarity. The effective pattern density may be computed for each location on the die by filtering the designed layout densities, often by using various two-dimensional filters of densities around the given location. FIG. 2A illustrates how the underlying features 2 , 6 , 11 and 12 cause variation in local surface topography (step height) 4 and global non-planarity 3 .

[0089] In creating shallow trench isolation (STI) structures (shown in FIG. 2B ), SiO ₂ 6 is deposited in a trench etched in silicon 5 and planarized using CMP to electrically isolate devices. As with oxide inter-level dielectric (ILD) polishing, the underlying pattern of isolated trenches results in unwanted variation. Problematic areas often are created as a result of CMP such as nitride erosion 7 (where the nitride barrier is removed and possibly exposes the underlying Si to contaminants and damage), corner rounding 8 (which has the effect of potentially widening the trench and where the exposure of Si destroys the device) and oxide dishing 9 which results in topography variation which impacts subsequent lithography. In STI polishing, pattern density is an important feature with regard to topographical variation and other CMP effects.

[0090] FIG. 2C illustrates the effects of polishing metal features (e.g. copper lines 11 and 12 ) entrenched in a dielectric (e.g. SiO ₂ ) 10 , during a damascene CMP process. For metal polishing, computation of pattern density is important to characterizing full-chip pattern dependencies; however other physical layout effects such as the linewidth and linespace may also be required. Two effects known as dishing and erosion result from metal damascene CMP. Dishing 13 is measured as the difference in metal thickness at the edge of a line and its center. Erosion 14 is defined as the difference in oxide thickness above a metal line, typically within an array of lines, to an adjacent unpatterned region. In a third effect residual copper 15 has not been removed from field or up areas of the chip.

[0091] FIGS. 3B and 3C illustrate in more detail some of the electrical effects that result from copper CMP performed during the creation of interconnects. A goal of a damascene process is to achieve a globally and locally planar surface of deposited metal 16 in an oxide or ILD material 17 , as shown in FIG. 3A . When the polish time is not sufficiently long enough, residual copper 19 may remain on the chip and in the case shown in FIG. 3 B, form a jumper or electrical short 19 across two electrically active structures or lines 17 . When the same structure is polished for too long (as shown in FIG. 3C ), copper is removed from the lines 20 in an effect called dishing. The electrical impact of dishing is to increase the resistance 22 of the line, which subsequently affects the RC time-constant of this section of the chip.

[0092] As illustrated in FIG. 1 B, One effective measurement technique is to measure 28 only those problematic areas 29 within the active area of an IC design 27 that are most likely to violate the design specifications or requirements. If those areas are measured to be within design specifications, then it can be assumed that all other areas of the chip are, too. The design specifications or requirements may be wafer-state parameters, such as minimum and maximum film thickness variation, or critical dimensions or electrical parameters such as maximum sheet resistance or maximum variation in sheet resistance across the chip. One approach uses the characterization of pattern dependencies during fabrication to identify such problematic areas by location and determine the appropriate measurement recipe for measuring the variation at that site. The approach may be used to match metrology recipes (i.e. settings on the metrology tool that describe where and how a measurement is to be made) with processes to characterize and minimize variation, thus reducing ramping times for pilot lines and factories. In general, however, this approach is difficult because designers generally do not know where the problem areas are a priori.

[0093] The approach may also be used with pre-existing metrology recipes and measurement plans. In some cases, a pre-defined measurement pattern will be used for in-situ or in-line measurement. As the approach is introduced into the fab environment, it may be used to add likely problematic sites to pre-existing measurement plans that are accepted and qualified within some fab. As such, the approach may be used independently or with existing measurement plans and strategies.

[0094] The approach may also be used to generate complete measurement recipes, not just site locations. For example, from a predicted thickness variation across an array structure the approach may specify the scan location, scan start and scan end locations and the number of measurement samples to take along the scan length—all based upon the predicted thickness variation compared with the desired chip specifications. The approach may also be used to coordinate measurement sites and recipes across multiple metrology tools. For example to measure erosion in a copper CMP test wafer, the approach may specify a thickness measurement in a field area adjacent to an array structure and generate the appropriate recipe for a Metapulse optical measurement tool. The approach would also specify a profilometry scan to start at a location at or near the thickness measurement and end at a field location at the other side of the array, as well as the number of samples to be taken along the scan. All of these implementations may be considered as measurement strategies where the measurement site plan or measurement recipes are generated from the predicted chip and wafer level characteristics and transmitted to one or more metrology tools.

[0095] By choosing measurement sites and recipes based on pattern-dependent process variation and automatically generating measurement plans for metrology tools, the system may identify, for example, potentially problematic areas across a chip that may result during ECD or HDP and subsequent CMP of interconnect features used in semiconductor devices. As explained earlier, these problematic areas are often due to variation in wafer quality (e.g. film thickness variation and surface topography variation such as dishing and erosion) and electrical parameters (resistance R, capacitance C, and noise). This variation is modeled and simulated using semi-physical process models that may be calibrated to a particular process and tool for each step in a sequence of one or more steps within a process flow. An example of such a model and calibration for an ECD and CMP process flow is described in the prior filed United States patent applications referenced above, incorporated here by reference. In general, a semi-empirical model, based on some physical understanding of the process, is fit to a particular tool at a particular recipe condition using data measured from actual processed test or production wafers. This fit of a model to better represent a given tool and recipe is often referred to as a calibration.

[0096] Engineers must be judicious in how measurement sites are selected to confirm the effectiveness of process steps or sequences. Each measurement may delay subsequent process steps and negatively impact yield. For a new IC design, determining the areas of the chip most likely to be problematic can be difficult. In addition, dummy fill strictures may be placed in the layout to improve thickness and surface topography uniformity of the manufactured wafer while maintaining the electrical parameters at the intended or designed values. However, the introduction of dummy fill introduces further complexity by changing the topography of the chip and thus may shift problematic areas from one chip location to another. Using the approach discussed here, the metrology tool can be controlled to confirm that full-chip variation meets the design specifications for the actual manufactured device.

[0097] The approach illustrated in FIG. 4 includes sub-blocks 31 , 33 , 34 and 35 that will be described in greater detail in later sections. The approach may be used with in-line, in-situ, and off-line measurements. The figures illustrate the approach for use with in-line operation.

[0098] An IC design is commonly represented electronically (e.g. in a Graphical Data Stream or GDS format) in a library of files that define structures and their locations at each level of an integrated circuit 30 . These files are typically large, although the features that are relevant to process variation could be described more efficiently. A process of layout extraction 31 involves summarizing discrete grids of IC designs in a compact set of such parameters such as linewidth, linespace, and density for each grid. A description of how to perform layout extraction is described in section a.

[0099] The layout features are mapped 33 to wafer quality, such as film thickness, or to electrical parameters, such as sheet resistance or capacitance. A flow description for this component is shown in FIG. 10 . This information may be used with a process model (e.g. a CMP model) or set of process models (e.g. ECD and a multi-step CMP process or a more complex process flow) to predict or simulate the manufacturing results and corresponding variation 33 - 1 that will occur when the design represented by the layout features is manufactured on the modeled process. The resulting device variation can be measured physically, such as by optical measurement of the film thickness, or surface profiling of the wafer surface to measure topography (e.g. dishing or step height and erosion or array height). The variation can also be measured electrically, such as by measuring sheet resistance or capacitance 33 - 2 and may require the use of the original IC design 39 . The computed parameters from 33 - 1 and 33 - 2 relevant to the desired specifications for comparison are acquired for the full-chip, both within die and for multiple dies across the wafer 33 - 3 . This information is stored in a database 121 - 1 and used for comparison to the desired chip and wafer specifications.

[0100] Using a combination of both process models and electrical simulations, the performance of a given IC design can be predicted and compared against the desired wafer quality and electrical parameters as well as design rule criteria 32 . The dynamic measurement plan 35 component performs two basic functions. The first is to compare predicted and desired parameters and the second is to generate the wafer measurement plan for a particular metrology tool. The comparison can be a simple check to see if the predicted wafer or electrical parameters exceed the design threshold or are within a specified tolerance. If so, the location of that position on the die is entered into the measurement plan for a specific tool.

[0101] Often a measurement site may require multiple recipe settings to direct the tool appropriately. For example, a profilometry scan requires not only the scan location but also a start and end point as well as the number of sample to take along the scan length. As such, the approach could specify these recipe parameters based upon film thickness variation. The site locations and other parameters may be used to generate complete measurement recipes for one or more metrology tools to be used at a particular point in a process flow. The locations to be measured, the associated measurement plans and measurement recipes are stored in a database 35 - 7 for presentation and review by the user or automatic electronic transfer to a metrology tool 36 .

[0102] The metrology tool 36 uses the measurement recipe (e.g. one or more measurement site locations and tool parameters such as where a profile scan is to begin and end) to direct where to measure 39 on a wafer 37 that is processed by one or more process steps (e.g. a process flow) 38 . An optional application 40 of this system can repeatedly store any errors between predicted and measured sites 41 to refine the models 42 and achieve better prediction. This may be useful to account for process drift that may occur after a tool has been calibrated. In some cases, process drift can be accounted for by tuning the model and not require a full re-calibration of the tool.

[0103] Illustrative embodiments of a method for measurement are described in the following sections. Section a. describes the extraction of layout parameters related to process variation as a method to transform the large design files into a manageable set of features. Layout extraction is not required but is useful. Section b. describes a desirable use of process and electrical models to characterize the impact of process variation on wafer-state specifications and electrical performance. Section c. describes how model based predictions are used to manually and automatically generate measurement plans for metrology tools. Section d. describes the construction and computational framework used to implement the dynamic measurement system as well as the operation of the system and methods by users.

[0104] a. Layout Parameter Extraction

[0105] A layout is a set of electronic files that store the spatial locations of structures and geometries that comprise each layer of an integrated circuit. It is known that process variation, which negatively impacts the planarity of processed films, is related to the variation in spatial densities and linewidths of a given design. To characterize this relationship, our method uses layout extraction, in which linewidth and density features are extracted spatially across a chip from the geometric descriptions in layout files. The extracted information may then be used to determine areas of the chip that exceed design rule criteria regarding designed linewidth and density.

[0106] The layout parameters used to compute dummy fill include the effective pattern density and linewidth. Although the dummy fill method works with extracted densities and linewidths, it is useful to include the extracted linespace, as well as linewidth and density.

[0107] The flowchart in FIGS. 5A and 5B provides a detailed flow of the layout extraction component 31 of FIG. 4 . In FIG. 5 , the layout file is transferred or uploaded to the dummy fill system 31 - 1 . The layout is divided into discrete grids, small enough so that aggregate computations of mean, maximum and minimum features can be used to represent the structures in the grid and still allow accurate dummy placement 31 - 2 . A typical grid size could be 40 μm×40 μm. The grids are ordered or queued for processing 31 - 3 . One desirable approach is to use multiple processors to compute the grids in parallel 31 - 4 . A grid is selected 31 - 5 and within that grid the linewidth of each object 31 - 6 is computed 31 - 7 . This process is repeated for every object within that grid 31 - 8 . For each set of neighboring objects (e.g. adjacent objects or objects within some defined distance) the maximum, minimum and mean linespace is computed 31 - 9 . The effective density for the entire grid is then computed 31 - 10 . This process is repeated for all the remaining grids 31 - 11 . Once all the grids are processed, the extracted features such as linewidth, linespace and density are re-assembled from the different processors 31 - 12 .

[0108] A table is then created and the maximum, minimum and mean linewidth, linespace, and density for each grid are placed in it as well as the maximum, minimum and mean linewidth for the whole chip 31 - 13 . The minimum and maximum linewidths for the whole chip used to compute a range.

[0109] Bins are useful for computing statistical and probabilistic distributions for layout parameters within the range specified by the bin. The linewidth range (M) for the chipis divided by a number of desired bins (N) 31 - 14 to determine the relative size of each of the N bins. For example the first bin would be the minimum linewidth or small nonzero value Δ to the linewidth (M/N) and continue until the N ^th bin which will span the linewidth from min LW _BinN =(N−1)·(M/N) to max LW _BinN =(N)·(M/N), which is also the maximum linewidth. The limits for these bins may also be set manually by the user. There are three sets of bins, a set of bins for each of maximum, minimum and mean linewidth. Each grid is placed in the appropriate bins according to its max, min and mean linewidth 31 - 15 . A histogram is also created for each bin showing the distribution of values within that bin 31 - 16 . This information is stored in the database and fed into process models, for example, ECD models, as well as the dummy fill rules generation 31 - 17 .

[0110] The maximum, minimum and mean linespace ranges are computed for the full chip 31 - 18 . The linespace range (M) is divided by the number of desired bins (N) 31 - 19 to determine the relative size of each of the N bins. For example the first bin would be the minimum linespace or small nonzero value Δ to the linespace (M/N) and continue until the N ^th bin which will span the linespace from min LW _BinN =(N−1)·(M/N) to max LW _BinN =(N)·(M/N), which is also the maximum linespace. The limits for these bins may also be set manually by the user. There are three sets of bins, a set of bins for each of maximum, minimum and mean linespace for the full chip. Each grid is separated into the appropriate bins according to its max, min and mean linespace 31 - 20 . A histogram is also created for each bin showing the distribution of values within that bin 31 - 21 . This information is stored in the database and fed into process models, in particular ECD models, as well as the dummy fill rules generation 31 - 22 .

[0111] The density range is computed for the full chip 31 - 23 . The density range (M) is divided by the number of desired bins (N) 31 - 24 to determine the relative size of each of the N bins. For example the first bin would be the minimum density or small nonzero value Δ to the density value (M/N) and continue until the Nth bin which will span the density from min LW _BinN =(N−1)·(M/N)+Δ to max LW _BinN =(N)·(N/M), which is also the maximum density. The limits for these bins may also be set manually by the user. There is one set of bins for density. Each grid is assigned to the appropriate bins according to its density 31 - 25 . A histogram is also created for each bin showing the distribution of values within that bin 31 - 26 . This information is stored in the database and fed into process models, in particular ECD models, as well as the dummy fill rules generation 31 - 27 . Finally all the linewidth, linespace and density information are stored either in the database or on the file system 3 - 17 , 3 - 22 and 3 - 27 for later use in process model prediction 31 - 28 .

[0112] An illustration of how an extraction table 44 (for all the grids across the full-chip or die) is generated is shown in FIG. 6 . The chip or die 43 is segmented into discrete grids 45 and the extraction procedure, described in FIG. 5 , is used to compute the linewidth 47 linespace 48 , and density 49 for each grid element 46 . FIG. 6 also illustrates how the linewidth (LW) 47 , linespace (LS) 48 and density 49 values placed 50 in an extraction table relate to the grid 45 at (yx) coordinate (1,1) and the grid at (y,x) coordinate (2,1). In many cases, the max, min and mean of the features within each grid are stored in the table 44 as well.

[0113] b. Process and Electrical Models

[0114] A process model or a series of models (i.e. a flow) can be used to predict the manufactured variation in physical and electrical parameters from an IC design. By characterizing the process variation relative to IC structures, the appropriate measurement sites can be determined to characterize those sites where physical and electrical parameters are likely to exceed desired values.

[0115] Each process tool generally has unique characteristics and thus a model needs to be calibrated to a particular recipe and tool. It is common practice to process a given IC design to determine the impact of processing on physical and electrical parameters and to develop or calibrate process models specific to a particular tool or recipe, as shown in FIG. 7A . In FIG. 7 A, the actual product wafer 64 is processed using a recipe 65 on a particular tool 66 . The pre-process wafer measurements 67 and post-process wafer measurements 68 are used to fit model parameters 69 . A semi-empirical model is used to characterize pattern dependencies in the given process. The calibration model parameters or fitting parameters 70 may be extracted using any number of computational methods such as regression, nonlinear optimization or learning algorithms (e.g. neural networks). The result is a model that is calibrated to this particular tool for a given recipe 71 .

[0116] Certain IC characteristics such as feature density, linewidth and linespace are directly related to variation in topography for plating, deposition, and CMP processes. Test wafers that vary these features throughout some range across the die can be used to build a mapping from design parameters (e.g. linewidth, linespace, density) to manufacturing variation (e.g. film thickness, dishing and erosion) for a given tool and recipe. Test wafers are an attractive alternative for assessing process impact in that they are generally less expensive to manufacture and one test wafer design can be used to characterize any number of processes or recipes for a wide range of IC designs. As shown in FIG. 7B, a test wafer 701 can be also be used to generate a calibrated process model or multiple process models or a process flow. The calibration model parameters may be computed using the same method in FIG. 7A . One difference is that the pre-process measurement, 74 , may be conducted by the test wafer manufacturer and retrieved in an electronic form, such as via the internet, email, disc or CD or paper form. Another difference is that the resulting calibration 78 normally spans a much larger range of linespace, linewidth and density features and thus is more applicable to a broad range of devices.

[0117] More details regarding the use of test wafers in calibrating a process are provided in FIG. 8A . A test wafer die 79 is patterned with a range of linewidth and linespace values 80 . The test wafer is processed (e.g. by CMP, ECD or deposition) on a tool using a given recipe 81 and the resulting variation in a parameter is measured across the chip 83 using a metrology tool (e.g. film thickness, 84 ). This mapping may be considered a model that maps a wide range of linewidth and linespace values to a particular film thickness variation for this tool and recipe. These mappings are useful for predicting process variation for new IC designs, as shown in FIG. 8B . Linewidth and linespace features thatfall within the range 86 spanned by the test die and wafer are extracted 85 from a new IC layout. The extracted linewidth and linespace features for spatial locations across the chip 86 are input into the mapping 87 and an accurate prediction of film thickness variation across the chip 89 and 90 can be acquired for a given tool and a given recipe before processing of the new IC design.

[0118] As shown in FIG. 8 C, the predicted process variation 91 can be fed into electrical models or simulations 92 to assess the impact of processing on the electrical performance of the chip 93 . Some of the electrical parameters that may be computed using the models include variation in sheet resistance, resistance, capacitance, interconnect RC delay, voltage drop, drive current loss, dielectric constant or crosstalk noise. These predictions can be used to determine the appropriate locations for measuring.

[0119] The following paragraphs and figure descriptions provide a detailed flow of the use of process and electrical models to characterize variation, as implemented for dummy fill.

[0120] FIG. 9 describes the steps involved in calibrating a process model to a particular tool or recipe. As described in FIG. 5, 31 layout extraction parameters are computed, or in the case of test wafers, uploaded from the wafer provider. The second step 33 - 4 - 1 pre-measures the wafer using metrology equipment. These measurements may include film thickness and profilometry scans to acquire array and step heights. The third step 33 - 4 - 2 processes the test wafer using the particular process or process flow that is to be characterized. Such processes or flows may include plating, deposition and/or polishing steps. It is particularly useful to calibrate on individual processes and also to calibrate on sections of the flow as a way to capture any coupling of variation between subsequent process steps in a flow. It is also recommended to calibrate the model for different recipe parameters such as time. The processed wafers are measured 34 - 3 - 3 at the same locations as the pre-measurements; such measurements may include film thickness, profilometry, or electrical; and the variation for the given process may be characterized 33 - 4 - 4 . Process models or representations are uploaded in 33 - 4 - 5 and the pre and post measurements as well as computed variation may be used to calibrate or fit the model or representation to a particular tool and/or recipe or recipes. These models may be formulated and uploaded by a user or selected from a library of models on the modeling computer system. The pre and post measurements and computed process variation are used to fit the model or simulation parameters for the given tool and recipe 33 - 4 - 6 . The result 33 - 4 - 7 is a process model calibrated to a particular tool and recipe or recipes. The result may also include a series of calibrated process models that can be used to simulate a process flow.

[0121] FIG. 10 describes the steps involved in using calibration models to predict the impact of process variation and subsequent variation in electrical parameters and performance. A new layout or set of layout files as well as desired IC features, geometries and design rule information are loaded into the system 30 . The second step performs layout extraction 31 to extract a description or set of features relevant to process variation for a number of locations across the chip. One common approach is to discretize the layout into a number of grids and compute the structure density for each grid element. However, our approach computes the effective linewidth and linespace for each grid element as well. The calibrated process models are uploaded or assembled to simulate processing 33 - 4 . The extracted layout parameters for each spatial location are fed into the model and the resulting process parameters are computed, such as film thickness, dishing, erosion, array and step heights 33 - 1 . The difference between the target and predicted IC parameters are used to compute the process variation. The predicted process parameters may also be fed into electrical models or simulations to characterize the electrical performance of the IC, which when compared with the desired performance allows for the electrical variation to be computed 33 - 2 . Some of the electrical parameters that may be computed include variation in sheet resistance, resistance, capacitance, interconnect RC delay, voltage drop, drive current loss, dielectric constant or crosstalk noise. Some of the electrical models and simulators that may be used include electrical timing, extractor and other IC related CAD software components.

[0122] Our approach is particularly suited for measuring sites in interconnect layers. Thus, interconnect metrics (R,C,L variation) are used as general metrics for all areas of the chip, as shown in the following table. Other critical areas may require simulating the circuit performance effects, including the addition of dummy fill. For example, a metric for the signal delay variation may be imposed in addition to a percentage RC variation to ensure that timing constraints of critical paths meet the circuit specifications. Similarly, clock skew and crosstalk noise simulations may be used to determine whether or not the circuit will function properly. This way, RC (or RLC) criteria can be used as a first pass estimate of where to add the dummy fill. Then the dummy fill placement can be fine tuned in the next iteration by selectively performing circuit simulations for specific signals or certain areas of the chip. Once dummy fill is finally placed and the circuit manufactured the predicted critical variation locations are then selected for in-line or in-situ measurements. In other words, the dynamic measurement system is then used to determine how the chip should be measured or tested to confirm this. The term dynamic includes the use of measurement data from test wafers and the models to determine measurement sites for a new IC layout. The term dynamic also includes the use of the same prior measurement data and models but adds feedback from prior metrology tool measurements on a production wafer to determine measurement sites for the current production wafer. For example, predictions of variation in sheet resistance in a location may prompt a profilometry scan over that feature to measure dishing and erosion. 1

[0123] The result of models and simulations described in this section is a full-chip prediction of process and electrical parameters and performance for a new IC design, as well as prediction of how these parameters may be impacted with the addition of dummy fill 33 - 3 . The next section describes how these parameters are input into the measurement plan generation component which compares them with the design specifications and requirements and determines which sites to measure and with which tool.

[0124] c. Dynamic Measurement Plan Generation

[0125] As shown in FIG. 4 , the dynamic sample plan generation component 35 compares predicted wafer-state parameters such as film thickness and electrical parameters such as sheet resistance with design specifications or requirements. The locations of the chip that exceed or are sufficiently close (e.g. as defined by the user, in that different circuit designs may dictate different distances) to a particular design constraint are used to generate a measurement plan for a particular metrology tool. The generation of a measurement plan is illustrated in FIG. 11 . FIG. 11A shows the model prediction of film thickness 94 over two metal lines 95 and 96 as a result of copper polishing. Residual copper across the two lines results in a jumper or short 97 at that location. Although the target thickness is T, the location where the jumper or short exists has a thickness of T plus an additional thickness of copper of R. The result of the model prediction stage is a computation of film thickness or electrical parameters such as sheet resistance for the complete chip.

[0126] The model may predict that the thickness bounds or shorts may not be a problem, but the measurement site locations of the thickest and thinnest spots may also be predicted from the model such that the measurement tool can actually measure those locations.

[0127] The use of the model prediction to determine locations for measurement is illustrated in FIG. 11B . The design specifications for the chip are used to determine the tolerances on prediction parameters such as film thickness variation. For example, a large positive variation or increase in film thickness, due to CMP, would result in jumpers 105 . A large negative variation or reduction in copper thickness, due to CMP, results in the dishing of lines and a subsequent increase in sheet resistance 107 . When predicted film thicknesses reach some pre-defined amount or exceed such thickness variation levels, the location is selected for measurement. It is likely that the locations selected for measurement would include the maximum and minimum variation levels associated with a particular wafer or electrical parameter and in the case of FIG. 11 , this parameter is film thickness.

[0128] In this case, the maximum copper film thickness variation (where jumpers are likely to occur) is defined as T+ΔT 101 . The predicted film thickness over the metal lines, as illustrated in FIG. 11 A, is plotted in FIG. 11 B and the maximum height, 103 , where the jumper occurs has the height, T+R 102 . In this case, the location of the point where the jumper occurs, 103 , would be entered into the sampling plan for film thickness measurement. This is one example of a threshold based cost function but other types of cost functions may be used to help determine which sites are to be selected.

[0129] The types of measurements and tools used also have an impact on which parameters are monitored. For example, dishing, which impacts interconnect sheet resistance, is normally measured with a profilometry tool whereas copper film thickness is normally measured with a film thickness tool. So the measurement plans generated may be specific to the particular tool type or types indicated by the user as available. Once the measurement plan is generated, it may be displayed to the user through a graphical user interface ( FIG. 11C ) and the user may choose to manually load in the measurement sites. The measurement plan may be automatically transferred and loaded into a particular measurement tool.

[0130] The steps involved in generating the measurement plan are described in the flow diagram of FIG. 12 . Full-chip predictions of wafer-state and electrical parameters, 33 - 3 , are input along with chip design specifications and requirements, 35 - 2 , and the selected metrology tools, 35 - 1 . The full-chip wafer and electrical parameters are compared against the design specifications and requirements, 35 - 3 . As described in FIG. 11 , the design constraints are used to set up thresholds on the predicted wafer-state and electrical parameters. Also a tolerance region is defined where if a particular prediction is within some distance, for example 15% of the limit, or exceeds the constraint, that location is flagged and stored. A tolerance region is preferred in that predictions may be off by 10-15% depending upon the amount of drift in the process. As such, some modeling error needs to be accounted for. The tolerances may also be defined statistically so that there is a limit on the number of measurements to be taken and the most likely locations to create problems are given higher priority. This computation could also be extended to hypothesis testing and other statistical fault diagnostic methods where the probabilistic likelihood of a particular location or feature impacting chip performance is maintained.

[0131] The x and y coordinates of all the measurement locations are consolidated 35 - 5 and heuristics are used to generate measurement plans for selected metrology tools 35 - 6 . For example, severe dishing which results in higher sheet resistance may be measured using a profilometry tool whereas residual copper that may result in a jumper could be measured using a film thickness metrology equipment. Measurement tools require recipes and as such, the heuristics are used to generate the measurement recipes and format it appropriately for a given tool.

[0132] The measurement site plans and recipes are stored in the database 35 - 7 , which allows for transfer to the user via the GUI or electronic file transfer 35 - 7 . It is useful to automatically transfer 35 - 7 and load 36 the measurement plan and recipe to the metrology tool. It is possible to supply the metrology tool with a measurement plan consisting of a number of sites to measure and metrology tool settings, in which the plan is generated based only upon model prediction outputs. As stated previously, the approach may also generate measurement recipes for more than one metrology tool, as in the example of using both thickness and profilometry to measure copper erosion. In such cases, the measurement recipes for both tools may be stored in the database 35 - 7 .

[0133] The advent of computer controlled measurement decision systems also allows the method to be used dynamically, that is to iteratively provide measurement site and recipe information to direct measurements and use the results of those measurements to generate additional measurement sites or recipes.. Measurement data often indicates drift in a manufacturing process and as such the model used for prediction needs to be tuned or a more accurate calibration acquired. In such cases, there is little value in continuing to make measurements until a more accurate prediction and measurement directive is obtained. A more accurate prediction may be acquired with a model calibrated for a different process state and may be selected from other calibration models 257 , 260 and 263 in a database 274 , as described in more detail later in FIGS. 24 and 25 .

[0134] A heuristic may use the method to measure one site at a time, for example maximum thickness variation, to check where the copper may not have cleared in a CMP process. Another heuristic may supply measurement sites to the tool and based upon the actual measurements, select another calibrated model that better fits the current state of the process. FIG. 13 provides examples of the some of the heuristics the system may use for post-CMP measurements in damascene process flows. In FIGS. 13A and 13B , heuristics are illustrated for the serial approach where the measurement plan is generated from the model prediction only ( FIG. 13A ) and for the iterative approach where the heuristic uses iterative measurements along with the full-chip prediction to select the next measurement site or sites ( FIG. 13B ).

[0135] Thus, the method may be used with any number of heuristics to determine problematic areas across the chip or wafer. An application of the method for dynamic measurement and graphical description of several heuristics are described later.

[0136] d. Implementation and Operation

[0137] A common use of the method is to direct metrology tools where to measure within a die and within one or more dies across a wafer. This direction is primarily based upon the effects of pattern dependencies on processing at the die and wafer level. The method may be used any kind of metrology too, including with film thickness, resistivity, ellipsometry, profilometry, atomic force microscopy, optical measurement equipment, electrical capacitance and resistance testers, or electrical material property testers (e.g. four-point probe sheet resistance testers). The method may be used in any mode of operation of metrology tools, for example, in an off-line, in-line and in-situ manner.

[0138] FIGS. 14A through 14C describe implementations of the method to characterize variation at the die and wafer level, as well as, wafer-to-wafer. As shown in FIG. 14 A, the method may be used to determine measurement locations across a full-die 110 based upon wafer-state or electrical variation across the die 111 . As shown in FIG. 14 B, the method also allows for multiple die 113 to be characterized across the wafer 112 by using models calibrated for each die location, see 34 in FIG. 4 . In this application, the model predictions are generated for each die 115 . The individual and aggregate die variation 114 is compared against design specs and measurement plans generated accordingly, see 35 in FIG. 4 . Variation at the wafer level is often radial, so normally three die are used; one at the edge of wafer, one at the center of the wafer, and one at some distance in-between. As shown in FIG. 14 C, the method can be used to characterize and direct measurement across multiple wafers 117 . Often process drift results in changes in how a wafer is processed. By utilizing a drift component with the process models, model based prediction can be used to identify problematic areas that require measurement or that may be drifting toward a design specification or constraint. In this approach, models calibrated at different times in the process life cycle are used to predict how variation will behave from wafer to wafer 118 . This characterization can be used to direct the metrology tool on which areas need to be measured and potentially add problematic sites as drift gets worse.

[0139] There are different ways in which to interact with the metrology tool, as shown in FIG. 15A . One approach is to have the system 122 reside on a computer 121 directly connected to the metrology tool 123 or housed within the computer control system of the metrology tool. The design specifications and layout files (if extraction has yet to be done) or layout extractions 120 for the production wafer are input into the method. The system 122 processes the design and generates a measurement plan, which is communicated to the software that actually commands the measurement process. After a particular process step 124 such as CMP, the wafer 125 is measured by the tool 123 . The measurements are normally stored on electronic media and may be transferred to the operator or process engineer via a GUI 126 . An optional approach is for the method to reside on a computer that is connected to the metrology tool via a network connection. A network may include electrical or optical communication via an extranet, intranet, internet or VPN.

[0140] Another implementation of the method uses the optional component (see 40 in FIG. 4 ) to tune the models when errors occur between the predicted variation and the actual measurements. In this approach, shown in FIG. 15 B, the design specs and layout information 127 are provided to the dynamic measurement method 129 . The method 129 may reside on a computer 128 connected to the metrology tool or housed within the computer control system inside the metrology tool 130 . The design specifications and layout files (if extraction has yet to be done) or layout extractions 127 for the production wafer are input into the method. The method 129 processes the design and generat