DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0141] With reference to FIGS. 4 to 37 , embodiments of the present invention will be explained as follows.

[0142] Referring to FIG. 4 , the driving apparatus of a PDP according to an embodiment of the present invention includes a data driver 42 applying data to address electrodes X 1 to Xm, a scan driver 43 driving scan electrodes Y 1 to Yn, a sustain driver 44 driving sustain electrodes Z that are a common electrode, a timing controller 41 controlling each of the drivers 42 , 43 and 44 , and a driving voltage generator 45 supplying a driving voltage to each of the drivers 42 , 43 and 44 .

[0143] The data driver 42 is supplied with data that are mapped to each sub-field by a sub-field mapping unit after conversely gamma-corrected and error-diffused by a reverse gamma correction circuit and error diffusion circuit (not shown), respectively. The data driver 42 takes samples of and latches the data in response to timing control signals CTRX, and then the address electrodes X 1 to Xm are supplied with the data.

[0144] On the other hand, the data driver 42 can apply positive data voltages Vd or another positive data voltages to the address electrodes X 1 to Xm during a sustain period or, during the sustain period and the period when a pre-erase signal is generated from the scan driver 43 and the sustain driver 44 .

[0145] The scan driver 43 simultaneously applies initialization waveforms to the scan electrodes Y 1 to Yn under control of the timing controller 41 , wherein the initialization waveforms are for initializing a full screen. Then, the scan driver 43 sequentially applies scan pulses to the scan electrodes Y 1 to Yn during an address period in order to select scan lines. Further, the scan driver 43 , after completion of the address period, simultaneously applies the pre-erase signals to the scan electrodes Y 1 to Yn for eliminating unnecessary wall charges that remain behind within off-cells where address discharge is not generated. The scan driver 43 then simultaneously applies sustain pulses to the scan electrodes Y 1 to Yn, with the sustain pulses causing sustain discharge, i.e., display discharge, to be generated in on-cells for the sustain period. The scan driver 43 simultaneously applies post-erase signals to the scan electrodes Y 1 to Yn for eliminating the wall charges within the on-cells, which are generated by the sustain discharge, after completion of the sustain period.

[0146] The sustain driver 44 works simultaneously with the scan driver 43 under control of the timing controller 41 and simultaneously applies the initialization waveform for initializing the full screen to the sustain electrodes Z, and then applies the pre-erase signals to the sustain electrodes Z. The pre-erase signals are used to eliminate the unnecessary wall charges remaining within the off-cells, after completion of the address period. The sustain driver 44 and the scan driver 43 operate in turn for the sustain period to supply sustain pulses to the sustain electrodes Z.

[0147] The timing controller 41 receives vertical/horizontal synchronization signals, generates timing control signals CTRX, CTRY and CTRZ necessary for each driver, and applies the timing control signals CTRX, CTRY and CTRZ to the corresponding drivers 42 , 43 and 44 for control thereof. The timing control signals CTRX applied to the data driver 42 include sampling clock for sampling data, latch control signals, and switch control signals that control the on/off time of an energy recovery circuit and a driving switch device. The timing control signals CTRY applied to the scan driver 43 from the timing controller 41 include switch control signals that control the on/off time of the energy recovery circuit and the driving switch device within the scan driver 43 . The timing control signals CTRZ applied to the sustain driver 44 from the timing controller 41 include switch control signals that control the on/off time of the energy recovery circuit and the driving switch device within the sustain driver 44 .

[0148] The driving voltage generator 45 generates positive setup voltages Vsetup, positive bias voltages Vscan-com, Vz-com applied as a common voltage for the address period, negative scan voltages Vscan for selecting scan lines, and positive sustain voltages Vs and pre-erase voltages Vpre-erase; the driving voltage generator 45 applies the generated voltages to the scan driver 43 . In the event that setup waveforms and set-down waveforms are continuously generated from the scan driver 43 , the driving voltage generator 45 applies to the scan driver 43 set-down voltages, Vset-dn, that are selected as any one of 0V, a ground voltage GND and a negative voltage. Setup voltages Vsetup are set to be higher than the sustain voltage Vs. Scan bias voltages Vscan-com are normally selected within a range of substantially 80˜130V, and the scan voltages Vscan are normally selected within a range of −70˜−180V. The sustain voltages Vs are selected within a range of 180˜200V. The pre-erase voltages Vpre-erase are applied to the scan driver 43 and the sustain driver 44 when pre-erase signals are separately applied between the address period and the sustain period. The pre-erase voltages Vpre-erase vary in accordance with the level of voltages applied to the address electrodes X 1 to Xm while the pre-erase signals are applied. This is because pre-erase discharges are generated when potential differences between the scan electrodes Y 1 to Yn or the sustain electrodes Z supplied with the pre-erase voltages Vpre-erase and the address electrodes X 1 to Xm opposite thereto are higher than a firing voltage that can cause a discharge. Accordingly, the pre-erase voltage Vpre-erase has a lower voltage level as a voltage applied to the address electrodes X 1 to Xm while the pre-erase signal being applied is positive and the level of the voltage gets higher, but the pre-erase voltage is selected between 0V and the set-down voltage, Vset-dn, in consideration of the voltages applied to the address electrodes X 1 to Xm.

[0149] Further, the driving voltage generator 45 generates positive data voltages Vd, applies the generated data voltages Vd to the data driver 42 , and applies to the sustain driver 44 the bias voltages Vz-com set to be identical to the scan bias voltages Vscan-com. The data voltages Vd are selected between 50˜80V. Such voltage conditions may vary in accordance with the composition of discharge gas or the structure of discharge cells.

[0150] On the other hand, the initial waveform generated simultaneously in each of the scan driver 43 and the sustain driver 44 may consist of a waveform where the voltage increases little by little or step by step, and a waveform where the voltage decreases little by little or step by step over time. Further, the initial waveform generated simultaneously in each of the scan driver 43 and the sustain driver 44 may only consist of a waveform where the voltage increases little by little or step by step over time. Herein, it is desirable that the initialization waveform only includes the waveform where the voltage increases. If all cells are initialized only with the waveform in which the voltage increases in such a way, a sufficient negative wall charge is accumulated on the scan electrodes Y 1 to Yn and the sustain electrodes Z that are formed within all cells, allowing their driving voltages to be commensurately reduced. In other words, if all cells are initialized only with the waveform where the voltage increases in such a way, a sufficient negative wall charge is formed on the scan electrodes Y to reduce the external driving voltages Vscan, Vd required for addressing, and the negative wall charges formed on the scan electrodes Y and the sustain electrodes Z are sustained until the address period ends, such that a low voltage is required for a sustain discharge. Further, if all cells are initialized only with the waveforms where the voltages increase, the initialization period is shortened.

[0151] FIGS. 5 and 6 are waveform diagrams explaining a method for driving a PDP according to the first embodiment of the present invention. FIG. 7 illustrates a change of wall charge distribution with the lapse of time within an on-cell in the event of the application of the waveform diagram of FIG. 6 . FIGS. 8A to 8 D are simulation results particularly representing a change of wall charge distribution for an initialization period. In FIGS. 8A to 8 D, the axis of ordinates represents the amount of charge (C), and the horizontal axis represents distance (μm).

[0152] Referring to FIGS. 5 to 8 , in the driving method for the PDP according to the first embodiment of the present invention, one frame period is time-divided into a plurality of sub-fields to drive the PDP. Each sub-field includes an initialization period for which only rising ramp waveforms are applied to the scan electrodes Y and the sustain electrodes Z to initialize the cells of a full screen, an address period for which cells are selected, a pre-erase period for which wall charges unnecessary for sustaining are eliminated, and a sustain period through which discharges of the selected cells are sustained.

[0153] In the initialization period (reset period), all the scan electrodes Y and sustain electrodes Z are simultaneously supplied with the rising ramp waveforms, Ramp-up. The rising ramp waveforms, Ramp-up, include a rising part where a voltage is substantially rising from the sustain voltage Vs to the setup voltage Vsetup and a sustaining part where the voltage is sustained for a specific period. The address electrodes X are supplied with 0V or a ground voltage GND while applying the rising ramp waveform, Ramp-up. By simultaneously applying the rising ramp waveforms to the scan electrodes Y and the sustain electrodes Z like this, dark discharges occur within the cells of the full screen, with the dark discharges generating almost no light. As a result, as shown in FIGS. 7 and 8 , the negative (−) wall charges are accumulated in each of the scan electrode Y and the sustain electrode Z, and the positive (+) wall charges are accumulated on the address electrode X. The amount of charge and the distribution characteristic of wall charges on the scan electrode Y and the sustain electrode Z, as shown in FIG. 8 , increase symmetrically. Because the same voltage is simultaneously applied to the scan electrode Y and the sustain electrode Z, a potential difference between the scan electrode Y and the address electrode X and a potential difference between the sustain electrode Z and the address electrode X are the same as an opposite firing voltage between the scan electrode Y and the address electrode X, which is required for the address discharge. As can be seen in FIGS. 7 and 8 , there is no potential difference between the scan electrode Y and the sustain electrode Z. The same amount of wall charge is in each of the scan electrode Y and the sustain electrode Z as a result of the discharge caused by the rising ramp waveform, Ramp-up, even though the previous condition of the initialization period, i.e., initial condition, is different.

[0154] On the other hand, before the address discharge starts, there is no potential difference between the scan electrode Y and the sustain electrode Z and the value of the wall charge formed in each of two electrodes is sustained the same; thus there occurs no undesired discharge, which is generated by a wall charge change under a high temperature environment before the start of the address discharge, even though the PDP is used under a high temperature environment of 50° C. and above.

[0155] The address period starts when the positive scan bias voltages Vscan-com are simultaneously applied to the scan electrodes Y, and the sustain electrodes Z are simultaneously supplied with the bias voltages Vz-com, which are substantially the same as the scan bias voltage Vscan-com. Because the same voltages Vscan-com, Vz-scan are simultaneously applied to the scan electrode Y and the sustain electrode Z, there is no potential difference between the scan electrode Y and the sustain electrode Z. Subsequently, scan pulses SCAN falling down to the negative scan voltage Vscan are sequentially applied to the scan electrodes Y and, at the same time, data pulses DATA synchronized with the scan pulse SCAN and rising up to the positive data voltage Vd are applied to the address electrodes X. The voltage difference between the scan pulse SCAN and the data pulse DATA is added to the wall voltage generated during the initialization period to generate the address discharge within an on-cell to which the data pulse DATA is applied. Wall charges are formed within the selected on-cells by the address discharge, so as to be able to generate discharges when the sustain voltage Vs is applied.

[0156] A voltage in the scan electrode Y gradually falls down to 0V or a ground voltage GND at the end of the address period. Excessive wall charges on the scan electrode Y, which are unnecessary for the sustain discharge, are eliminated by a voltage SLD that decreases at a designated slope.

[0157] In the pre-erase period, the sustain electrodes Z are simultaneously supplied with pre-erase waveforms Pre-ers that rise from 0V or the ground voltage GND substantially to the sustain voltage Vs at a designated slope. The pre-erase waveform Pre-ers has a narrow pulse width and has its voltage level set to be substantially the sustain voltage Vs. Due to the pre-erase waveform, weak dark discharges occur between the sustain electrode Z and the scan electrode Y or between the sustain electrode Z and the address electrode X within off-cells that are not selected by the address discharge. As a result, since the pre-erase discharge is generated, the wall charges remaining within the off-cells from the initialization period are eliminated. Accordingly, the wall charges remaining within the off-cells radically prevent the undesired discharges that can be generated by sustain pulses SUS applied during the sustain period.

[0158] The pre-erase waveform Pre-ers can be applied only to the sustain electrode Z or the scan electrode Y, or may be applied to both the scan electrode Y and the sustain electrode Z.

[0159] In the sustain period, the sustain pulses SUS are alternately applied to the scan electrodes Y and the sustain electrodes Z. In the on-cell selected by the address discharge, the wall voltage within the cell is added to the sustain pulse SUS to generate the sustain discharge, i.e., display discharge, between the scan electrode Y and the sustain electrode Z whenever each sustain pulse SUS is applied.

[0160] In a post-erase period that is allocated after completion of the sustain discharge, a square waveform with narrow pulse width or a post-erase signal Pst-ers of a ramp wave type, as shown in FIG. 6 , can be applied to at least one of the scan electrode Y and the sustain electrode Z in order to eliminate the wall charges generated by the sustain discharge. On the other hand, the post-erase signal Pst-ers and a post-erase period can be omitted.

[0161] As a result, a method and apparatus for driving a PDP according to the first embodiment of the present invention can reduce the time needed for initialization because the set-down period in FIG. 3 is omitted and the PDP is initialized only with the setup discharge; and the present invention can also drastically reduce the external driving voltages Vscan, Vd needed for addressing because a sufficient negative wall charge is formed on the scan electrodes Y. Further, the method and apparatus for driving the PDP according to the first embodiment of the present invention can reduce the external driving voltage Vs needed for the sustain discharge because the negative wall charges formed on the scan electrodes Y and the sustain electrodes Z are sustained until the address period ends. Furthermore, the method and apparatus for driving the PDP according to the first embodiment of the present invention can prevent undesired discharge in the sustain period by having the pre-erase waveforms Pre-ers applied to the sustain electrodes Z before the start of the sustain discharge to eliminate the unnecessary wall charges accumulated within the off-cells. The pulse width of the pre-erase waveform Pre-ers is 10˜20 μs, and the voltage thereof is substantially the sustain voltage Vs. The pulse width and voltage of the pre-erase waveform Pre-ers can be adjusted in accordance with the wall voltages within the cell and the voltage applied to other electrodes. In the on-cell selected during the address period, because the positive wall charges are accumulated on the scan electrode Y and the negative wall charges are accumulated on the address electrode X by the address discharge, no discharge is generated even though a positive pre-erase waveform Pre-ers is applied to the sustain electrode Z.

[0162] On the other hand, it is suggested in Japanese Laid Open Gazette No. 2001-135238 that a PDP may have efficiency heightened more than that of the related art low density Xe panel by increasing the Xe component in the discharge gas sealed with the PDP. By the way, the Hi-Xe PDP has a problem in that the reliability of address operation and sustain operation decreases because the discharge is unstable. If the present invention is applied to such a high density Xe panel, the efficiency of the PDP can not only be increased but the stable address discharge can also be generated, by increasing the Xe component in the discharge gas, thus it is possible to stabilize the address operation and the sustain operation.

[0163] In order to prove the effect of the PDP according to the first embodiment of the present invention, a simulation was conducted in use of ‘PSPICE’ that is a widely used simulation tool; FIGS. 9 and 10 represent the simulation results. In this simulation, the rising ramp waveform, Ramp-up, was set to rise from 200V to 380V substantially for 0.2 ms. The rising ramp waveform Ramp-up is simultaneously applied to the scan electrode Y and the sustain electrode Z. The pulse width of the scan pulse SCAN applied to the scan electrode Y is 1.4 μs, and the pulse width of the sustain pulse SUS is 2 μs. The gaps between the sustain pulses SUS is 2 μs. The rising time and the falling time of each of the scan pulse SCAN and the sustain pulse SUS are set to be 200 ns. The voltage level of the scan voltage Vscan is set at −80V, and the voltage level of the scan bias voltage Vscan-com, Vz-scan is set at 110V. The voltage level of the data voltage Vd is set at 55V, and the voltage level of the sustain voltage Vs is set at 190V.

[0164] As can be seen in FIG. 10 , the voltage difference between the scan electrode Y and the sustain electrode Z is sustained at 0V before the address discharge starts.

[0165] The rising ramp waveform, Ramp-up, simultaneously applied to the scan electrode Y and the sustain electrode Z can have its rising section increase linearly, in an exponential function type, i.e., a gentle curve shape as in FIGS. 11 and 12 , or in a sinusoid as in FIG. 13 . The waveform of the exponential function type or the sinusoid can be realized by applying the circuit disclosed in Korean Patent Application Nos. 10-2001-0003005, 10-2001-0015755 and 10-2002-0002483 that were filed by the applicant of this application.

[0166] FIG. 14 is a waveform explaining a driving method for a PDP according to the fifth embodiment of the present invention.

[0167] Referring to FIG. 14 , in the driving method for the PDP according to this embodiment of the present invention, one frame period is time-divided into a plurality of sub-fields to drive the PDP, and the scan electrodes Y and the sustain electrodes Z are supplied with erase signals Pre-ers of a falling ramp waveform falling between the address period and the sustain period to eliminate the wall charges remaining within the off-cells.

[0168] In the initialization period (reset period), the cells of the full screen can be initialized by continuously applying the rising ramp waveforms and the falling ramp waveforms to the scan electrodes Y as in FIG. 3 , or by applying only the rising ramp waveform to the scan electrodes Y and the sustain electrodes Z as in the present embodiment. Further details relating to this will be described later. Also, the initialization waveform can be applied to the initialization waveform explained in another embodiment described later.

[0169] The waveforms applied during the address period and the sustain period, and operations caused by them, are substantially the same as in the foregoing embodiments, thus repetitive explanation will be omitted.

[0170] The pre-erase period is allotted between the address period and the sustain period. In the pre-erase period, positive DC voltages Vx-com substantially equal to data voltages Vd are applied to the address electrode X and, at the same time, the scan electrode Y and the sustain electrode Z are supplied with the pre-erase ramp signal Pre-ers at a falling slope. The pre-erase ramp signal Pre-ers can vary in accordance with a discharge condition within the cell, but it is desirable to generate the pre-erase ramp signal Pre-ers within about 20 μs. The voltage level of the pre-erase ramp signal Pre-ers falls down below the scan voltage Vscan. On the other hand, the voltage difference between two electrodes needed for an erase discharge depends on the firing voltage between the address electrode X and the scan electrode Y, and the firing voltage between the address electrode X and the sustain electrode Z. Because of this, the pre-erase ramp signal Pre-ers can have its voltage level changed in accordance with the voltage in the address electrode X. The pre-erase ramp signal Pre-ers causes a dark discharge, where no light is generated, between the address electrode X and the scan electrode Y, and between the address electrode X and the sustain electrode Z. The dark discharge causes the wall charges remaining within the off-cells from the initialization period to be eliminated. As a result, the voltage between the electrodes X, Y and Z is kept below the firing voltage so as not to generate discharges in the off-cells because the wall voltage inside the off-cells is 0 (zero) or close thereto even when the sustain pulse SUS is applied to the scan electrode Y and the sustain electrode Z. On the other hand, no discharge occurs between the electrodes X, Y and Z in the on-cells because negative charges are charged on the address electrode X and positive charges are charged on the scan electrode Y even when the pre-erase ramp signal Pre-ers of negative voltage is applied to the scan electrode Y and the sustain electrode Z.

[0171] On the other hand, the pre-erase ramp signal Pre-ers can be a multi-step waveform MSPre-ers as shown in FIG. 15 , and can have its voltage level decreased step by step.

[0172] FIG. 16 is a waveform diagram representing an embodiment where the initialization waveform shown in FIG. 5 is applied to the driving waveform shown in FIG. 14 . FIG. 17 is a waveform diagram representing an embodiment where the initialization waveform shown in FIG. 5 is applied to the driving waveform shown in FIG. 15 .

[0173] Referring to FIGS. 16 and 17 , in the driving method for the PDP according to further embodiments of the present invention, the cells of the full screen are initialized in use of only the rising ramp waveform, Ramp-up, for the initialization period in each sub-field, and the remaining charges within the off-cells are eliminated in use of the pre-erase waveforms, Pre-ers and MSPre-ers, where their voltages decrease gradually or step by step for the pre-erase period which is allotted between the address period and the sustain period.

[0174] In the initialization period (reset period), all the scan electrodes Y and sustain electrodes Z are simultaneously supplied with the rising ramp waveforms, Ramp-up, that rise substantially from the sustain voltage Vs to the setup voltage Vsetup at a designated slope. At the same time, the address electrodes X are supplied with 0 V or a ground voltage GND. By simultaneously applying the rising ramp waveforms to the scan electrodes Y and the sustain electrodes Z like this, dark discharges occur within the cells of the full screen, with the dark discharges generating almost no light. As a result, the negative (−) wall charges are accumulated in each of the scan electrode Y and the sustain electrode Z, and the positive (+) wall charges are accumulated on the address electrode X. Because the same voltage is simultaneously applied to the scan electrode Y and the sustain electrode Z, a potential difference between the scan electrode Y and the address electrode X, and a potential difference between the sustain electrode Z and the address electrode X are the same as an opposite firing voltage between the scan electrode Y and the address electrode X, which is required for the address discharge. There is no potential difference between the scan electrode Y and the sustain electrode Z. The same amount of wall charge is in each of the scan electrode Y and the sustain electrode Z as a result of the discharge caused by the rising ramp waveform, Ramp-up, even though the previous condition of the initialization period, i.e., initial condition, is different.

[0175] On the other hand, before the address discharge starts, there is no potential difference between the scan electrode Y and the sustain electrode Z, and the wall charge formed in each of two electrodes Y, Z is equal; thus no undesired discharge occurs even though the PDP is used under a high temperature environment of 50° C. and above.

[0176] The address period starts when the positive scan bias voltages Vscan-com are simultaneously applied to the scan electrodes Y, and the sustain electrodes Z are simultaneously supplied with the bias voltages Vz-com, which are substantially the same as the scan bias voltage Vscan-com. Because the same voltages Vscan-com, Vz-scan are simultaneously applied to the scan electrode Y and the sustain electrode Z, there is no potential difference between the scan electrode Y and the sustain electrode Z. Subsequently, scan pulses SCAN falling down to the negative scan voltage Vscan are sequentially applied to the scan electrodes Y and, at the same time, data pulses DATA synchronized with the scan pulse SCAN and rising up to the positive data voltage Vd are applied to the address electrodes X. The voltage difference between the scan pulse SCAN and the data pulse DATA is added to the wall voltage generated during the initialization period to generate the address discharge within an on-cell to which the data pulse DATA is applied. Wall charges are formed within the selected on-cells by the address discharge, so as to be able to generate discharges when the sustain voltage Vs is applied.

[0177] In the pre-erase period, the pre-erase ramp signals, Pre-ers, MSPre-ers, having a falling slope are simultaneously applied to the scan electrodes Y and the sustain electrodes Z. The pre-erase ramp signals, Pre-ers, MSPre-ers, can have a different voltage level, slope or number of steps in accordance with the voltage in the address electrode X and the discharge condition within the cell. The pre-erase ramp signals, Pre-ers, MSPre-ers, cause dark discharge, where almost no light is generated, between the address electrode X and the scan electrode Z, and between the address electrode X and the sustain electrode Z. The dark discharge causes the wall charges remaining within the off-cells from the initialization period to be eliminated. As a result, no discharge is generated in the off-cells even when the sustain pulse SUS is applied to the scan electrode Y and the sustain electrode Z. On the other hand, no discharge occurs between the electrodes X, Y and Z in the on-cells even when the pre-erase ramp signal, Pre-ers, of negative voltage is applied to the scan electrode Y and the sustain electrode Z, because negative charges are charged on the address electrode X and positive charges are charged on the scan electrode Y.

[0178] In the sustain period, the sustain pulses SUS are alternately applied to the scan electrodes Y and the sustain electrodes Z. In the on-cell selected by the address discharge, the wall voltage within the cell is added to the sustain pulse SUS to generate the sustain discharge, i.e., display discharge, between the scan electrode Y and the sustain electrode Z whenever each sustain pulse SUS is applied.

[0179] On the other hand, the sustain pulse firstly applied to the scan electrode Y and the sustain electrode Z to generate the sustain discharge stably has its pulse width set to be wider than the normal sustain pulses thereafter. Further, the sustain pulse lastly applied to the scan electrode Y and the sustain electrode Z also has its pulse width set to be wider than the normal sustain pulses therebefore. Specifically, according to the experiment result, it is desirable to apply the last sustain pulse to the sustain electrode Z for each sub-field.

[0180] In a post-erase period that is allocated after completion of the sustain discharge, the post-erase signal, Pst-ers, of a ramp waveform is applied to at least one of the scan electrode Y and the sustain electrode Z in order to eliminate the wall charges generated by the sustain discharge. The post erase signal, Pst-ers, causes the erase discharge generated within the on-cell, thereby eliminating the remaining wall charges. On the other hand, the post-erase signal, Pst-ers, and the post-erase period can be omitted.

[0181] On the other hand, in the pre-erase period and the sustain period, the address electrode X is supplied with the positive DC voltage Vx-com that is substantially the same as the data voltage Vd, as shown in FIGS. 18 and 19 . If the positive DC voltage is applied to the address electrode X during the pre-erase period and the sustain period, the pre-erase discharge is generated more easily, the absolute value of the voltage of the pre-erase signal, Pre-ers, MSPre-ers, can be lowered more, and the sustain discharge is mostly generated between the scan electrode Y and the sustain electrode Z.

[0182] The rising ramp waveform, Ramp-up, simultaneously applied to the scan electrode Y and the sustain electrode Z can have its rising section increase linearly, in an exponential function type, i.e., a gentle curve shape as in FIGS. 20 and 21 , or in a sinusoid as in FIG. 22 in use of a resonance circuit.

[0183] FIG. 23 is a waveform diagram explaining a driving method for a PDP according to the fourteenth embodiment of the present invention. FIG. 24 illustrates a change of wall charge distribution over time within an on-cell in the event of the application of the waveform diagram of FIG. 23 . FIGS. 25A to 25 P are simulation results particularly representing a change of wall charge distribution of a cell when the driving waveforms of FIG. 23 are applied to the cell. In FIGS. 25A to 25 P, the axis of ordinates represents the amount of charge (C), and the horizontal axis represents distance (μm).

[0184] Referring to FIGS. 23 to 25 , in the driving method of the PDP according to the present invention, the scan electrodes Y and the sustain electrodes Z are continuously supplied with the rising ramp waveform, Ramp-up, and the falling ramp waveform, Ramp-dn, to initialize the cells of the full screen.

[0185] Further, in the driving method of the PDP according to the present invention, there are allotted the address period to select the on-cells in each sub-field and the sustain period to carry out the display of the selected on-cells.

[0186] In the initialization period (reset period), all the scan electrodes Y and sustain electrodes Z are simultaneously supplied with the rising ramp waveforms, Ramp-up, that rise substantially from the sustain voltage Vs to the setup voltage Vsetup at a designated slope. At the same time, the address electrodes X are supplied with 0 V or a ground voltage GND. By simultaneously applying the rising ramp waveforms to the scan electrodes Y and the sustain electrodes Z like this, dark discharges occur within the cells of the full screen, with the dark discharges generating almost no light. As a result, as shown in FIGS. 24 and 25 A to 25 D, the negative (−) wall charges are accumulated in each of the scan electrode Y and the sustain electrode Z, and the positive (+) wall charges are accumulated on the address electrode X. The amount of charge and the distribution characteristic of wall charges on the scan electrode Y and the sustain electrode Z, as shown in FIGS. 25A to 25 D, increase symmetrically. Because the same voltage is simultaneously applied to the scan electrode Y and the sustain electrode Z, there is no potential difference between the scan electrode Y and the sustain electrode Z. The same wall charge exists in each of the scan electrode Y and the sustain electrode Z as a result of the discharge caused by the rising ramp waveform, Ramp-up, even though the previous condition of the initialization period, i.e., initial condition, is different.

[0187] Subsequently to the rising ramp waveform, Ramp-up, the falling ramp waveform, Ramp-dn, falling substantially from the sustain voltage Vs to the negative scan voltage Vscan, is simultaneously applied to the scan electrode Y and the sustain electrode Z. At this moment, the address electrode X is sustained at 0V or the ground voltage GND. The falling ramp waveform, Ramp-dn, causes the dark discharge to be generated between the scan electrode Y and the address electrode X and between the sustain electrode Z and the address electrode X. As a result of the discharge, the excessive wall charges unnecessary for the address discharge are eliminated as shown in FIGS. 24 and 25 E to 25 G; uniform wall charges remain within all the cells.

[0188] Generally, sub-pixels of red, green and blue have deviation in their firing voltage depending on the characteristic of phosphorus. If the falling ramp waveform is applied into the cell to cause the erase discharge, the firing condition can be made uniform regardless of the deviation of the firing voltage of the sub-pixel. Accordingly, the erase discharge by the falling ramp waveform causes the discharge condition to be uniform within all the cells to increase the driving margin.

[0189] The address period is substantially the same as in the foregoing embodiment, thus repetitive description thereof will be omitted. Within the cell selected by the address discharge, the negative wall charges are accumulated on the address electrode X opposite to the scan electrode Y as in FIG. 24 . FIG. 25H represents the wall charge distribution on the scan electrode Y and the sustain electrode Z right after the address discharge.

[0190] In the sustain period, firstly, the scan electrode Y and the sustain electrode Z are sequentially supplied with the sustain pulses SUS having wide pulse width, and then the sustain electrode Z and the scan electrode X are alternately supplied with the normal sustain pulses SUS having narrow pulse width. The sustain pulses SUS having wide pulse width are sequentially applied to the scan electrode Y and the sustain electrode Z. In the on-cell selected by the address discharge, the sustain discharge, i.e., display discharge, is generated between the scan electrode Y and the sustain electrode Z whenever each sustain pulse SUS is applied, as the sustain pulse SUS is added to the wall voltage within the cell. FIGS. 25I to 25 N represent changes of the wall charge distribution on the scan electrode Y and the sustain electrode Z upon the sustain discharge generated whenever each sustain pulse is applied.

[0191] In the post-erase period, the post-erase signal, Pst-ers, of rising slope are alternately applied to the scan electrode Y and the sustain electrode Z, so as to eliminate the wall charges generated by the sustain discharge. The post-erase signal, Pst-ers, eliminates the remaining charges within the cell. FIGS. 25O and 25P represent changes of the wall charge distribution on the scan electrode Y and the sustain electrode Z right after the erase discharge is generated by the post-erase signal, Pst-ers.

[0192] On the other hand, the post-erase signal, Pst-ers, can be omitted.

[0193] FIG. 26 is a waveform diagram explaining a driving waveform of a PDP according to the fifteenth embodiment of the present invention.

[0194] Referring to FIG. 26 , in the driving method for the PDP according to the present invention, after applying the rising ramp waveforms, Ramp-up, to the scan electrodes Y and the sustain electrodes Z in each sub-field, the falling ramp waveforms, Ramp-dn, which drop down from the start voltage of the rising ramp waveform and another voltage, are applied to the scan electrodes Y and the sustain electrodes Z to initialize the cells of the full screen.

[0195] In the initialization period (reset period), the rising ramp waveforms, Ramp-up, which rise substantially from the sustain voltage Vs to the setup voltage Vsetup at a designated slope, are simultaneously applied to the scan electrodes Y and the sustain electrodes Z. At the same time, the address electrodes X are supplied with 0V or the ground voltage GND. By simultaneously applying the rising ramp waveform, Ramp-up, to the scan electrodes Y and the sustain electrodes Z like this, a dark discharge occurs which generates almost no light within the cells of the full screen. As a result, the negative (−) wall charges are accumulated in each of the scan electrode Y and the sustain electrode Z, and the positive (+) wall charges are accumulated on the address electrode X.

[0196] Subsequently to the rising ramp waveform, Ramp-up, the falling ramp waveform, Ramp-dn, falling from a voltage V1 between substantially the sustain voltage Vs and the scan bias voltage, Vscan-com, is simultaneously applied to the scan electrode Y and the sustain electrode Z. At this moment, the address electrode X is sustained at 0V or the ground voltage GND. The falling ramp waveform, Ramp-dn, causes the dark discharge to be generated between the scan electrode Y and the address electrode X and between the sustain electrode Z and the address electrode X. As a result of the discharge, the excessive wall charges unnecessary for the address discharge are eliminated; uniform wall charges remain within all the cells.

[0197] The falling ramp waveform, Ramp-dn, has its start voltage lower than the start voltage of the rising ramp waveform, Ramp-up, unlike the related art falling ramp waveform shown in FIG. 3 or the foregoing embodiment. Because of this, the period while the falling ramp waveform, Ramp-dn, is being applied is shortened to reduce the initialization period, while the address period and the sustain period can be commensurately lengthened as much.

[0198] The address period, the sustain period and the post-erase period are substantially the same as the waveform shown in FIG. 25 , thus repetitive description thereof will be omitted.

[0199] FIG. 27 is a waveform diagram representing waveforms, which are applied to a driving method for a PDP according to the sixteenth embodiment of the present invention.

[0200] Referring to FIG. 27 , in the driving method for the PDP according to the present invention, after applying the rising ramp waveforms, Ramp-up, to the scan electrodes Y and the sustain electrodes Z in each sub-field, the falling ramp waveforms, Ramp-dn 1 , Ramp-dn 2 , having different slopes from each other are applied to the scan electrodes Y and the sustain electrodes Z to initialize the cells of the full screen.

[0201] In the initialization period (reset period), the rising ramp waveforms, Ramp-up, which rise substantially from the sustain voltage Vs to the setup voltage Vsetup at a designated slope, are simultaneously applied to the scan electrodes Y and the sustain electrodes Z. At the same time, the address electrodes X are supplied with 0V or the ground voltage GND. The rising ramp waveform, Ramp-up, simultaneously applied to the scan electrodes Y and the sustain electrodes Z like this, causes the dark discharge, which generates almost no light, within the cells of the full screen. As a result, the negative (−) wall charges are accumulated in each of the scan electrode Y and the sustain electrode Z, and the positive (+) wall charges are accumulated on the address electrode X.

[0202] Subsequently to the rising ramp waveform, Ramp-up, a first falling ramp waveform, Ramp-dn 1 , falling substantially from the sustain voltage Vs is applied to the scan electrode Y and, at the same time, a second falling ramp waveform, Ramp-dn 2 , where a voltage falls down at its slope lower than that of the first falling ramp waveform, Ramp-dn 1 , is applied to the sustain electrode Z. An end voltage Vzr of the second falling ramp waveform, Ramp-dn 2 , is higher than that of the first falling ramp waveform, Ramp-dn 1 , because the slope of the second falling ramp waveform, Ramp-dn 2 , is lower than that of the first falling ramp waveform, Ramp-dn 1 . In other words, the absolute value of the end voltage of the second falling ramp waveform, Ramp-dn 2 , is less than that of the first falling ramp waveform, Ramp-dn 1 , because of the slope difference between the first falling ramp waveform, Ramp-dn 1 , and the second falling ramp waveform, Ramp-dn 2 . At this moment, the address electrode X is sustained at 0V or the ground voltage GND. The falling ramp waveforms, Ramp-dn 1 , Ramp-dn 2 , cause the dark discharge to be generated between the scan electrode Y and the address electrode X and between the sustain electrode Z and the address electrode X. As a result of the discharge, the excessive wall charges unnecessary for the address discharge are eliminated; uniform wall charges remain within all the cells.

[0203] The slope of the falling ramp waveform, Ramp-dn 2 , applied to the sustain electrode Z is slower than that of the falling ramp waveform, Ramp-dn 1 , applied to the scan electrode Y; thus the erase discharge between the sustain electrode Z and the address electrode X is generated to be in a small-scale as compared with the erase discharge between the scan electrode Y and the address electrode X. As a result, the negative wall charge remaining on the sustain electrode Z is greater than the wall charge remaining on the scan electrode Y until the sustain pulse is first applied to the scan electrode Y. Accordingly, when the sustain pulse is first applied to the scan electrode Y, the voltage difference between the scan electrode Y and the sustain electrode Z becomes larger, causing the sustain discharge to be generated more easily. Further, since the negative wall charge remaining on the sustain electrode Z is increased till the start of the sustain period, the sustain voltage Vs can be lowered more.

[0204] The address period, the sustain period and the post-erase period are substantially the same as the waveform shown in FIG. 25 , thus repetitive description thereof will be omitted.

[0205] FIG. 28 illustrates a simulation result of voltage and current characteristics when applying the waveforms of FIG. 27 .

[0206] FIG. 29 is a waveform diagram representing waveforms, which are applied to a driving method for a PDP according to the seventeenth embodiment of the present invention.

[0207] Referring to FIG. 29 , in the driving method for the PDP according to the present invention, after applying the rising ramp waveforms, Ramp-up, to the scan electrodes Y and the sustain electrodes Z in each sub-field, the falling ramp waveforms, Ramp-dn 1 , Ramp-dn 2 , having their end voltages Vscan, Vzr different from each other are applied to the scan electrodes Y and the sustain electrodes Z to initialize the cells of the full screen.

[0208] In the initialization period (reset period), the rising ramp waveforms, Ramp-up, which ri