DESCRIPTION OF EMBODIMENTS

[0030] The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout. It will be understood that when an element such as a layer, region or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

[0031] According to first embodiments of the present invention, a first electrode layer including tantalum nitride can be deposited on a semiconductor substrate using a tantalum precursor. The tantalum precursor can include tantalum elements and bonding elements that are chemically bonded to the tantalum elements. A portion and/or all of the bonding elements can include at least one ligand-bonded element, which is ligand-bonded to the tantalum element.

[0032] The tantalum precursor can include a tantalum amine derivative or a tantalum halide precursor. More particularly, the tantalum amine derivative can include Ta(NR ₁ )(NR ₂ R ₃ ) ₃ (where R ₁ , R ₂ , and R ₃ are selected from an H and/or C ₁ -C ₆ alkyl group and can be the same or different from each other), Ta(NR ₁ R ₂ ) ₅ , (where R ₁ and R ₂ are selected from an H and/or C ₁ -C ₆ alkyl group and can be the same or different from each other), Ta(NR ₁ R ₂ ) _x (NR ₃ R ₄ ) _5-x (where R ₁ , R ₂ , R ₃ and R ₄ are selected from an H and/or C ₁ -C ₆ alkyl group and can be the same or different from each other and x is selected from 1, 2, 3 or 4), and/or terbutylimido-tris-diethylamido tantalum (TBTDET:(Net ₂ ) ₃ Ta=NBu ^t ). Examples of a tantalum halide derivative include TaF ₅ , TaCl ₅ , TaBr ₅ and/or Tal ₅ .

[0033] When the first electrode layer is formed at a temperature above about 650° C. using a tantalum precursor, the first electrode layer may not be properly deposited on the substrate because the tantalum precursor may be completely decomposed and particles may be generated. On the other hand, when the first electrode layer is formed at a temperature less than about 100° C., the first electrode layer may not be properly deposited on the substrate because the tantalum precursor may not be decomposed. According to some embodiments, the first electrode layer may be deposited in a temperature in the range of about 100° C. to 650° C. According to additional embodiments, the first electrode layer can be deposited at a pressure in a range of between about 0.3 Torr and about 30 Torr when the temperature is in the range of about 100° C. to 650° C. In addition embodiments, the tantalum precursor can be introduced in a gaseous state using a bubbler or a liquid delivery system (LDS). The tantalum precursor can be deposited on the substrate using ALD (Atomic Layer Deposition) and/or CVD (Chemical Vapor Deposition).

[0034] Methods of forming a first electrode layer using ALD will be described with reference to the accompanying drawings. FIGS. 1A to 1 D are cross-sectional views illustrating methods of forming a capacitor electrode using atomic layer deposition (ALD) according to embodiments of the present invention.

[0035] A substrate on which the first electrode layer of the capacitor will be formed is placed in a processing chamber 100 . The processing chamber 100 is then maintained at a pressure in a range of about 0.3 Torr to about 30 Torr, and the substrate is heated to a temperature of less than about 650° C.

[0036] Referring to FIG. 1 A, the tantalum precursor 12 a is introduced into the processing chamber 100 , and then some of the tantalum precursor 12 a is chemisorbed (chemically absorbed) onto the substrate. As shown in FIG. 1 B, an inert gas is introduced into the processing chamber 100 . As a result, non-chemisorbed tantalum precursors 12 a are removed from the substrate and from the processing chamber. In some embodiments, a nitrogen (N ₂ ) gas or an argon (Ar) gas can be used as the inert gas. Referring to FIG. 1C, a removing gas (not shown) is introduced into the processing chamber 100 , and the ligand-bonded elements 13 of the chemisorbed tantalum precursors 12 are removed from the tantalum precursors 12 a . The ligand-bonded elements can be removed using H ₂ , N ₂ , NH ₃ , SiH ₄ , and/or Si ₂ H ₆ , for example, alone or in combination. These compounds can be activated through a remote plasma process that avoids damage to the substrate.

[0037] Finally, a purge gas (not shown) is introduced into the processing chamber 100 , and any removing gas remaining in the processing chamber 100 is displaced. As a result, an atomic layer 14 including tantalum nitride can be deposited on the substrate as shown in FIG. 1D . The first electrode layer including tantalum nitride can be deposited relatively easily on the substrate by repeating the deposition of the atomic layer 14 . In addition, removing the non-chemisorbed tantalum precursor from the substrate using the inert gas and removing the ligand-bonded elements from the tantalum precursor using the removing gas can be repeated many times so as to reduce inclusion of impurities in the tantalum nitride electrode layer. In other words, steps of forming the atomic layer 14 including tantalum nitride can be repeated to provide a desired thickness of the first electrode layer.

[0038] In addition, a post treatment process for the first electrode layer can be carried out using H ₂ , N ₂ , NH ₃ , SiH ₄ , Si ₂ H ₆ , or a combination thereof, which can be activated through a remote plasma process or a direct plasma process. After forming the first electrode layer, the post treatment process can be used to more completely remove any impurities remaining in the first electrode layer. While a remote plasma process can generate a radio frequency plasma gas outside of the processing chamber 100 and provide the plasma gas into the processing chamber 100 , a direct plasma process can generate the radio frequency plasma gas inside of the processing chamber 100 .

[0039] A method of forming the first electrode layer by using a direct plasma type CVD process will be described with reference to FIG. 2 . FIG. 2 is a diagram illustrating a chemical vapor deposition (CVD) apparatus for forming a capacitor electrode according to embodiments of the present invention.

[0040] A substrate 22 on which the first electrode layer will be formed is placed in a processing chamber 20 . The processing chamber 20 is set at a pressure in a range of about 0.3 Torr to about 30 Torr, and the substrate 22 is heated to a temperature less than about 650° C. Subsequently, tantalum amine derivatives (not shown) are introduced into the processing chamber 20 , and then gaseous reactants are also provided into the processing chamber 20 . According to additional embodiments, a hydrogen (H ₂ ) gas, a nitrogen (N2) gas or a compound gas including nitrogen (N) atom(s) can be used as the gaseous reactants, alone or in combination. These gaseous reactants can be used as activated. According to still additional embodiments, an NH ₃ gas or an N ₂ H ₂ gas can be used as the compound gas including nitrogen (N) atom(s).

[0041] Power is applied to electrodes 24 and 26 of the processing chamber 20 so that the tantalum amine derivatives are activated through the remote plasma process or the direct plasma process, and changed into plasma ions. Subsequently, the plasma ions react with each other onto the substrate 20 to thereby deposit the first electrode layer including tantalum nitride. As one embodiment of the present invention, the direct plasma process can be used in the CVD apparatus as shown in FIG. 2 .

[0042] A post treatment process for the first electrode layer can also be carried out using H ₂ , N ₂ , NH ₃ , SiH ₄ , Si ₂ H ₆ , and/or a combination thereof, which can be activated through the remote plasma process or the direct plasma process, after forming the first electrode layer to more completely remove any impurities remaining in the first electrode layer. Accordingly, a first electrode layer including tantalum nitride can be formed through ALD or CVD using the tantalum precursor.

[0043] A dielectric layer including a metal oxide is deposited on the first electrode layer. Examples of metal oxides for the dielectric layer may include Ta ₂ O ₅ , TiO ₂ , Al ₂ O ₃ , Y ₂ O ₃ , ZrO ₂ , HfO ₂ , BaTiO ₃ , SrTiO ₃ , etc. These layers may be formed alone or a composite layer thereof that includes at least two of these layers may be used.

[0044] A second electrode layer is deposited on the dielectric layer. Examples of the second electrode layer includes a polysilicon thin film, a ruthenium (Ru) thin film, a platinum (Pt) thin film, an iridium (Ir) thin film, a titanium nitride (TaN) thin film, a tantalum nitride (TaN) thin film, tungsten nitride (WN) thin film, etc. Furthermore, when the second electrode layer is not a tantalum nitride (TaN) thin film, a capping layer may be further deposited on the second electrode layer. The capping layer can include a tantalum nitride thin film. The second electrode layer can be deposited in the same manner as in the first electrode layer in case the second electrode layer includes tantalum nitride.

[0045] As a result, a capacitor can be manufactured to have a first electrode layer corresponding to a lower electrode, the dielectric layer, and a second electrode layer corresponding to an upper electrode on a semiconductor substrate. According to embodiments of the present invention, the first electrode layer may provide a storage electrode, and the second electrode layer may provide a plate electrode of a capacitor used in an integrated circuit device.

[0046] According to additional embodiments of the present invention, the first electrode layer and/or the second electrode layer can be formed to include tantalum nitride so that the metal oxide having a high dielectric constant can be used as the dielectric layer of the semiconductor capacitor. As a result, a storage capacitance of a capacitor can be increased.

[0047] A chemical reaction mechanism for forming electrode layers (the first and/or the second electrode layer) including tantalum nitride is described as follows according to embodiments of the present invention. Hereinafter, the chemical reaction for removing the tantalum precursor using an inert gas is referred to as a purification reaction, and the chemical reaction for removing the ligand-bonded element using the removing gas is referred to as a removing reaction. During the removing reaction, the removing gas reacts with the ligand-bonded element, and the ligand-bonded element is removed from the tantalum precursor, because the reactivity of the removing gas to the ligand-bonded element is higher than that of the ligand-bonded element to the tantalum precursor.

[0048] Terbutylimido-tris-diethylamido-tantalum ((NEt ₂ ) ₃ Ta=Nbu ^t , hereinafter simply referred to as “TBTDET”) can also be used as the tantalum precursor. A part of the TBTDET is chemisorbed onto the substrate, and the non-chemisorbed TBTDET is removed from the substrate during the purification reaction. The ligand-bonded elements are then removed through the removal reaction using the reactivity difference between the ligand-bonded elements and the removal gas to the tantalum precursor. During the removal reaction, the TBTDET is not influenced by the removing gas, since the TBTDET includes a double bond of Ta=N. Accordingly, the ligand-bonded elements are only removed during the removal reaction, so that an atomic layer comprising Ta=N can be deposited on the substrate.

[0049] A variety of deposition methods of depositing the tantalum nitride, (different from chemical reaction mechanisms according to embodiments of the present invention), are disclosed in U.S. Pat. No. 6,268,288 issued to Hautala et al., U.S. Pat. No. 6,203,613 issued to Gates et al.; Korean Patent Laid-Open Publication No. 2001-45960; Korean Patent Laid-Open Publication No. 1997-18573; and in an article by Kang et al., entitled “Plasma-Enhanced Atomic Layer Deposition of Tantalum Nitrides Using Hydrogen Radicals as a Reducing Agent”, Electrochemical and Solid-State Letters, 4(4) C17-19 (2001). The disclosures of each of these patents, publications, and articles are hereby incorporated herein in their entirety by reference.

[0050] According to embodiments of the present invention, removing the ligand-bonded element using the removing gas may be different than a substitution reaction using hydrogen radicals as a reducing agent. According to additional embodiments of the present invention, a power source may not need to be applied into the processing chamber when the tantalum nitride is deposited. Furthermore, deposition of a metal layer using CVD according to embodiments of the present invention can use tantalum amine derivatives as tantalum precursors, which may also be different from conventional deposition techniques using tantalum halide as tantalum precursors.

[0051] Hereinafter, examples of forming capacitors according to embodiments of the present invention are described with reference to the accompanying drawings.

EXAMPLE I

[0052] FIGS. 3A to 3 G are cross-sectional views illustrating methods of forming a capacitor according to embodiments of the present invention.

[0053] Referring to FIG. 3A, a trench structure 202 can be formed on a semiconductor substrate 200 using conventional field isolation techniques so that the substrate 200 is separated into active and a non-active areas. Impurities can then be partially implanted into the substrate 200 to provide P-wells and N-wells. Subsequently, a polysilicon layer 204 a , a tungsten silicide layer 204 b and a silicon nitride layer 204 c can be sequentially formed on the active area of the substrate 200 to form a gate pattern 204 corresponding to a word line of a DRAM cell. That is, the gate pattern 204 can have a polyside structure including a polysilicon layer 204 a doped with a relatively high concentration of impurities and a tungsten silicide layer 204 b formed on the polysilicon layer 204 a . In addition, spacers 206 comprising silicon nitride can be formed on side surfaces of the gate pattern 204 .

[0054] A source electrode 205 a and a drain electrode 205 b can be formed on a surface of the substrate 200 surrounding to the gate pattern 204 by implanting impurities using the gate pattern 204 as a mask. Accordingly, a transistor including the gate pattern 204 , the source electrode 205 a , and the drain electrode 205 b is formed on the substrate 200 . One of the source electrode 205 a and the drain electrode 205 b is connected to the lower electrode of the capacitor to provide a capacitor contact area, and the other is connected to a bit line structure of semiconductor device to provide a bit line contact area. According to some embodiments of the present invention, the source electrodes 205 a provide respective contact areas, and the drain electrode 205 b provides a bit line contact area.

[0055] Polysilicon can then be filled into spaces between the gate patterns 204 to provide capacitor contact pads 210 a that make electrical contact with respective lower capacitor electrodes of respective capacitors and a bit line contact pad 210 b that makes electrical contact with a bit line structure. The polysilicon 210 filling the capacitor contact areas corresponds to the capacitor contact pads 210 a , and the polysilicon 210 filling the bit line contact area corresponds to the bit line contact pad 210 b.

[0056] As shown in FIG. 3 B, the bit line structure 220 is electrically connected to the bit line contact pad 210 b . In particular, a first insulating interlayer 222 is deposited on the gate pattern 204 and the polysilicon 210 filled between the gate patterns 204 . Then, the first insulating interlayer 222 is selectively etched using a photolithography process so that the bit line contact pad 210 b is partially exposed to provide a bit line contact hole 223 . Subsequently, tungsten 220 a is deposited in the bit line contact hole 223 and on the first insulating interlayer 222 . As a result, the tungsten 220 a can completely fill the bit line contact hole 223 . Then, silicon nitride 220 b is deposited on the tungsten layer 220 a . After depositing the silicon nitride 220 b , the silicon nitride 220 b layer and the tungsten layer 220 a are selectively etched using a photolithography process to thereby form the bit line structure 220 including the tungsten 220 a and the silicon nitride 220 b.

[0057] Then, silicon nitride is deposited on the bit line structure 220 and the first insulating interlayer 222 , and the silicon nitride layer is selectively etched to provide silicon nitride spacers 224 on side surfaces of the bit line structures 220 . Accordingly, the tungsten 220 a in the bit line structure 220 is covered with the silicon nitride 220 b of the mask layer and surrounded with the silicon nitride of the spacers 224 .

[0058] A second insulating interlayer 230 can be deposited on the bit line structure 220 , the spacers 224 , and the first insulating interlayer 222 . The second insulating interlayer 230 can include silicon nitride, and can be deposited using high-density plasma deposition process.

[0059] Referring to FIG. 3 C, the second insulating interlayer 230 and the first insulating interlayer 222 can be selectively etched to partially expose capacitor contact pads to thereby provide self-aligned contact holes 232 . The etching rate on the silicon nitride of the bit line structure 220 and the spacer 224 may be different than the etching rate of the silicon nitride of the first and second insulating interlayers 222 and 230 , which may cause the etch to proceed more quickly on the second insulating interlayer 230 and the first insulating interlayer 222 than on the silicon nitride of the bit line structure 220 and the spacer 224 .

[0060] Referring to FIG. 3D, a lower electrode layer 234 of the capacitor can be formed by filling the self-aligned contact hole 232 using ALD or CVD according to some embodiments of the present invention, so that the lower electrode layer 234 can include tantalum nitride. A cylinder-shaped lower electrode 234 a of the capacitor can be formed using a photolithography process on the lower electrode layer 234 as follows.

[0061] A first lower electrode material can be filled in the self-aligned contact hole 232 , and then the first lower electrode material on the second insulating interlayer 230 can be polished through a chemical mechanical polishing (CMP) process. Accordingly, the first lower electrode material only fills the self-aligned contact hole 232 but does not extend onto the surface of the second insulating interlayer. Continuously, an oxide layer (not shown) can be successively deposited on the first lower electrode material that fills the self-aligned contact hole 232 . The oxide layer can be patterned into a cylinder shape, and then a second lower electrode material can be deposited on the cylinder-shaped oxide layer. The oxide layer can be etched, and then the cylinder-shaped lower electrode layer 234 a can be formed, as shown in FIG. 3E .

[0062] Referring to FIG. 3F, a dielectric layer 236 is formed on surfaces of the cylinder-shaped lower electrode layer 234 a . According to some embodiments of the present invention, metal oxide can be used as the dielectric layer 236 . Examples of materials for the dielectric layer 236 can include TA ₂ O ₅ , TiO ₂ , Al ₂ O ₃ , Y ₂ O ₃ , ZrO ₂ , HfO ₂ , BaTiO ₃ , and/or SrTiO ₃ . Combinations of the above referenced materials and/or layers thereof can also be used.

[0063] Referring to FIG. 3 G, an upper electrode layer 238 of the capacitor is formed on the dielectric layer 236 . The upper electrode layer 238 can include a thin film of tantalum nitride, polysilicon, ruthenium (Ru), platinum (Pt), iridium (Ir), titanium nitride (TaN), tantalum nitride (TaN), and/or tungsten nitride (WN). When including a thin film of tantalum nitride, the upper electrode layer 238 can be formed in the same manner as in the first electrode layer. Accordingly, the capacitor can include the lower electrode layer, the dielectric layer, and the upper electrode layer.

[0064] As described in the first example, the lower electrode layer and/or the upper electrode layer of the capacitor can be formed to include tantalum nitride, so that a capacitor according to embodiments of the present invention can use a metal oxide having a high dielectric constant as the dielectric layer.

EXAMPLE 2

[0065] A self-aligned contact hole can be formed on a substrate in the same manner as in the first example. A lower electrode layer of the capacitor can be formed on the second electrode layer by filling the self-aligned contact hole with a lower electrode material. According to additional embodiments of the present invention, the lower electrode layer may include a thin film of tantalum nitride, polysilicon, ruthenium (Ru), platinum (Pt), iridium (Ir), titanium nitride (TaN), tantalum nitride (TaN), and/or tungsten nitride (WN). When including a thin film of tantalum nitride, the lower electrode layer can be formed in the same manner as discussed in the first example.

[0066] Then, the lower electrode layer can be etched using a conventional photolithography process to thereby form a cylinder-shaped lower electrode layer. A dielectric layer is formed on a surface of the cylinder-shaped lower electrode layer. According to still additional embodiments of the dielectric layer, a metal oxide can be deposited on a surface of the cylinder-shaped lower electrode layer. Examples of materials for the dielectric layer can include TA ₂ O ₅ , TiO ₂ , Al ₂ O ₃ , Y ₂ O ₃ , ZrO ₂ , HfO ₂ , BaTiO ₃ , and/or SrTiO ₃ .

[0067] Continuously, an upper electrode layer of the capacitor can be deposited on the dielectric layer using ALD or CVD according to some embodiments of the present invention, so that the upper electrode layer includes tantalum nitride. Accordingly, integrated circuit capacitors according to embodiments of the present invention can be formed to include the lower electrode layer, the dielectric layer, and the upper electrode layer.

[0068] As described in the second example, the lower electrode layer and/or the upper electrode layer of the capacitor can be formed to include tantalum nitride, so that capacitors according to second embodiments of the present invention can use a metal oxide having a high dielectric constant as the dielectric layer.

[0069] Hereinafter, characteristics of capacitors according to embodiments of the present invention are described.

[0070] Leakage Current Characteristic

[0071] To provide an investigation into leakage current characteristics of capacitors according to embodiments of the present invention, three types of capacitor specimens were prepared.

[0072] Specimen I includes a lower electrode layer of 200 Å thickness, a dielectric layer having a TaO layer of 90 Å thickness and an O ₃ layer of 60 Å thickness, and an upper electrode layer of 100 Å thickness having tantalum nitride according to embodiments of the present invention. Specimen II includes a lower electrode layer of 200 Å thickness, a dielectric layer having a Ta ₂ O ₅ layer of 90 Å thickness and an O ₃ layer of 60 Å thickness, and an upper electrode layer of 800 Å thickness having tantalum nitride according to embodiments of the present invention. Specimen III includes a lower electrode layer of 200 Å thickness, a dielectric layer having a Ta ₂ O ₅ layer of 90 Å thickness and an O ₃ layer of 60 Å thickness, and an upper electrode layer of 800 Å thickness having titanium nitride.

[0073] A voltage in a range of −4V to 4V was applied to both electrodes of the respective specimen capacitors. FIG. 4 is a graph showing a leakage current characteristic of the capacitor of Specimen I. In FIG. 4 , curves I, II, and III show leakage current characteristics when the voltage is applied at temperatures of about 25° C., 85° C., and 125° C., respectively. Referring to FIG. 4 , the leakage current characteristics may be acceptable irrespective of the temperature. Particularly, the graph of FIG. 4 shows that the leakage current is in a range of about 10 ⁻¹⁷ A/cell to 10 ⁻¹⁵ A/cell when the voltage was applied in a range of about −1V to +1V.

[0074] FIG. 5 is a graph showing a leakage current characteristic of the capacitor of specimen III. The graph as shown in FIG. 5 shows that the leakage current of the capacitor of specimen III is allowable.

[0075] Even though not shown in the attached drawings, investigation of the capacitor of specimen II showed that the leakage current was also in a range of about 10 ⁻¹⁷ A/cell to 10 ⁻¹⁵ A/cell when the voltage was applied in a range of about −1V to 1V. That is, it was noted that the integrated circuit capacitors including the first electrode layer and/or the second electrode layer according to embodiments of the present invention have good leakage current characteristics.

[0076] Storage Capacitance Characteristic

[0077] An investigation of the storage capacitance showed that an electric thickness oxide (ETO) of the specimen II is 25 Å, and the ETO of the specimen III is 27 Å, which indicates that the capacitor including the first electrode layer and/or the second electrode layer according to embodiments of the present invention have a good storage capacitance.

[0078] According to embodiments of the present invention, a metal oxide having a high dielectric constant can be used as a capacitor dielectric layer without significant chemical reaction between the dielectric layer and the electrode layers, thereby increasing a storage capacitance of a capacitor and providing steady capacitor performance even though the metal oxide is used as the dielectric layer.

[0079] Methods according to embodiments of the present invention may include forming a capacitor including a tantalum nitride layer as a lower electrode layer. Methods according to additional embodiments of the present invention may include forming a capacitor including a tantalum nitride layer as an upper electrode layer.

[0080] According to embodiments of the present invention, methods of forming a capacitor on a semiconductor device can include forming a first electrode layer including tantalum nitride on a semiconductor substrate using a tantalum precursor. Moreover, the tantalum precursor can include tantalum elements and bonding elements that are chemically bonded to the tantalum elements, and at least a portion of the bonding elements can include at least one ligand bonded element which is ligand-bonded to the tantalum element. A dielectric layer can be formed on the first electrode layer, and a second electrode layer can be formed on the dielectric layer.

[0081] According to additional embodiments of the present invention, methods of forming a capacitor on a semiconductor device can include forming a first electrode layer on a substrate and then forming a dielectric layer on the first electrode layer. A second electrode layer including tantalum nitride can be formed on the dielectric layer using a tantalum precursor. The tantalum precursor can include tantalum elements and bonding elements that are chemically bonded to the tantalum elements, and at least a portion of the bonding elements can include at least one ligand-bonded element which is ligand-bonded to the tantalum element.

[0082] Electrode layers of a capacitor on a semiconductor device can thus include tantalum nitride, and therefore, chemical reaction between electrode layers and the dielectric layer can be reduced even when the dielectric layer comprises a metal oxide. In addition, a dielectric constant of the dielectric layer can be increased due to one or both electrodes including tantalum nitride, so that capacitance can be increased.

[0083] It should be noted that many variations and modifications might be made to the embodiments described above without substantially departing from the principles of the present invention. All such variations and modifications are intended to be included herein within the scope of the present invention, as set forth in the following claims.