BEST MODE FOR CARRYING OUT THE INVENTION

[0059] The present invention will be explained in accordance with the accompanying drawings to describe it in more details.

[0060] A configurational diagram for describing a method of setting a back bias of a MOS circuit according to the present invention is shown in FIG. 1 . An example of a back bias setting method with respect to an n channel type MOSFET that constitutes the MOS circuit, is shown in FIG. 1 (A). An example of a back bias setting method with respect to a p channel type MOSFET is shown in FIG. 1 (B). Thus, a CMOS circuit comprised of an n channel type MOSFET and a p channel type MOSFET makes use of a combination of the back bias setting methods shown in FIGS. 1 (A) and 1 (B).

[0061] In the present application, the term “MOS” is understood as a metal oxide semiconductor configuration originally called for simplicity or brevity. However, the recent generally-named MOSs include those obtained by changing a metal of essential portions of a semiconductor device to an electrical conductor such as polysilicon which does not belong to the metal and changing oxide to another insulator. Also CMOSs are now understood as having a wide technical meaning corresponding to a change in how to grasp the MOSs referred to above. MOSFETs are also similarly taken as the meaning including such a wide construction as substantially taken as an insulated-gate field effect transistor without being understood in a narrow sense. CMOSs, MOSFETs, etc. employed in the present invention follow general naming.

[0062] In FIG. 1 (A), a source S of an n channel type MOSFET is connected to a circuit's ground potential point. An input signal is supplied to a gate G of the n channel type MOSFET, and an output signal corresponding to the input signal supplied to the gate G thereof is obtained from a drain D thereof. A back bias voltage (substrate bias voltage) Vb is supplied to a p type semiconductor substrate or semiconductor region (well region) with a back gate of the n channel type MOSFET, i.e., the source S and drain D of the n channel type MOSFET formed thereon.

[0063] In FIG. 1 (B), a source S of a p channel type MOSFET is supplied with a circuit's operating voltage Vdd. An input signal is supplied to a gate G of the p channel type MOSFET, and an output signal corresponding to the input signal supplied to the gate G is obtained from a drain D thereof. A back bias voltage (substrate bias voltage) Vbp is supplied to an n type semiconductor substrate or semiconductor region (well region) with a back gate of the p channel type MOSFET, i.e., the source S and drain D of the p channel type MOSFET formed thereon.

[0064] A characteristic diagram for describing the relationship between a substrate bias voltage Vbn and a threshold voltage Vt with an n channel type MOSFET as an example is shown in FIG. 2 . In the back bias setting method according to the present invention, the substrate bias voltages Vbn supplied to the n channel type MOSFET are given as a positive voltage like +V 2 and a negative voltage like −V 1 . The positive voltage like +V 2 is set to a weak forward bias voltage equivalent to such an extent or level as not to cause such a forward current as to inhibit the corresponding circuit operation to flow into pn formed between the source of the n channel type MOSFET and a p type substrate or well region with the source formed thereon. Described specifically, the positive voltage is given as a micro or small voltage of about +0.3 in a state in which the source S of the n channel type MOSFET is being supplied with a circuit's ground potential like 0V.

[0065] In terms of the circuit operation, the negative voltage −V 1 can be set low within such a range that the pn does not cause breakdown. However, the negative voltage is set within such a range that a backward leak current produced in the pn presents no problem, to achieve such low power consumption as to be described later. When a gate length of a MOSFET is 0.2 μm, for example, the negative voltage is set to about −1.5V, whereas when the gate length is 0.12 μm, it is set to about −1.0V. A description will be made below of a case in which a MOSFET scaled down in gate length as in the case where the gate length is given as 0.12 μm, is used, as an illustrative example.

[0066] According to the back bias setting method of the invention of the present application, wherein the substrate bias voltage is changed as given as +V 2 and −V 1 as described above, a change width of the threshold voltage Vt of the n channel type MOSFET can be set high as given as Vt 2 and Vt 12 in the characteristic diagram shown in FIG. 2 . On the other hand, the change width of the threshold voltage Vt of the n channel type MOSFET at the time that the substrate bias voltage is changed as given as 0V and −V 1 as described in the above publications, for example, is reduced like Vt 2 and Vt 11 .

[0067] In order to make it easy to understand the back bias setting method according to the present invention, a threshold voltage Vt 2 in a state in which the bias voltage of +V 2 is being applied, is shown in FIG. 2 so as to become equal to the threshold voltage Vt 2 at the time that the conventional bias voltage of 0V is applied. Namely, the MOSFET according to the present invention means that the threshold voltage Vt at the time that the bias voltage is set to 0V, so-called true threshold voltage is formed so as to be higher than the threshold voltage Vt 2 of MOSFET to which the conventional bias voltage of 0V is applied.

[0068] A characteristic diagram for describing the relationship between a substrate bias voltage Vbn and a drain-to-source leak current Ibs with the n channel type MOSFET as an example is shown in FIG. 3 . Namely, the gate G and source S of the n channel type MOSFET shown in the same drawing are respectively brought into a state in which 0V like the circuit's ground potential is being applied thereto. The relationship between the substrate bias voltage Vbn and the leak current Ibs flowing through the source is shown.

[0069] When a positive voltage like +V 2 is applied as the substrate bias voltage Vbn supplied to the n channel type MOSFET in the above-described state, a leak current Ileak 22 flows. Further, the substrate bias voltage is reduced two digits or more as in the case of a leak current Ileak 2 at the time that a negative voltage like −V 1 is applied. On the other hand, in a MOSFET in which a leak current Ileak 11 at the time that the substrate bias voltage is set to 0V as in the prior art, is matched with the above leak current Ileak 22 , a leak current flowing when the same negative voltage V 1 is applied, is reduced about one digit alone as in the case of a leak current Ileak 1 . Thus, when compared in the state in which the same negative voltage V 1 is applied, the difference between the leak current Ileak 2 set by the above-described bias setting method according to the present invention and the leak current Ileak 1 set by the conventional bias switching or changeover is extensively improved over one digit or more.

[0070] The characteristic diagram shown in FIG. 3 also shows a limit of a negative-direction voltage of a back bias voltage Vbn supplied to an n channel type MOSFET of a MOS circuit operated at a positive voltage. Namely, when the negative voltage −V 1 is raised on an absolute-value basis, the threshold voltage increases and a so-called threshold leak current that flows between the drain and source, is reduced correspondingly. On the other hand, a leak current developed in pn between the source and the substrate or well region increases. Therefore, the increase in the leak current produced in such pn exceeds the reduction in the threshold leak current. Thus, when the back bias voltage Vbn exceeds a predetermined voltage and increases, the leak current Ibs increases. It has been found out by the present inventors that the optimum voltage value of the predetermined voltage (−V 1 ) is about −1V when the MOSFET scaled down in the above-described manner is used.

[0071] The leak current Ibs of the MOSFET as described above indicates one obtained by adding the threshold leak current that flows between the drain and source of the MOSFET and the leak current that flows in pn between the source of the MOSFET and the substrate or well. A leak current, which falls within a range between the back bias voltages +V 2 and −V 1 , makes up the majority of the threshold leak current. When the bias voltage Vbs is placed in a voltage region lower than the voltage −V 1 , the leak current produced in pn makes up the most part as described above and hence about −1V becomes most suitable as described above. When the substrate back bias voltage Vbn is set higher than the voltage +V 2 , the threshold leak current increases and exceeds a forward bias voltage (about 0.6V) of pn, a large forward current flows out in pn and hence the normal operation of the MOS circuit cannot be performed. Thus, the voltage value of the positive voltage +V 2 is limited to about +0.3V in consideration of the influence of noise produced in a grounding line or conductor upon the circuit operation and even the latch up of a CMOS circuit.

[0072] While the above description has been made with the n channel type MOSFET as an example, the p channel type MOSFET is also similar to it. However, since an operating voltage Vdd is supplied to the source in the case of the p channel type MOSFET, a description will be made with such an operating voltage Vdd as a reference. A weak forward voltage like Vdd−0.3V corresponding to the bias voltage +V 2 in the case of the n channel type MOSFET, and a reverse bias voltage like Vdd+1.0V corresponding to the bias voltage −V 1 in the case of the n channel type MOSFET are applied to an n type substrate or a well region on which the p channel type MOSFET is formed.

[0073] An operating speed of a digital circuit comprised of a CMOS circuit is made fast in proportion to an operating current that flows into an MOSFET placed in an ON state. The current that flows in the MOSFET, increases in inverse proportion to the threshold voltage if a gate voltage supplied to the gate, i.e., the operating voltage of the CMOS circuit is constant. Thus, it is advantageous to set the threshold voltage of the MOSFET as small as possible for the purpose of achievement in a high-speed operation. However, a leak current that flows in the MOSFET placed in an OFF state, also increases in inverse proportion to the threshold voltage. As a result, the speeding up of the CMOS digital circuit means that even when it is kept in a non-operated state, current consumption will occur due to the increase in the leak current. Since a portable electronic device is predicated on being battery-driven, the leak current limits a substantial operating time.

[0074] Therefore, an attempt to change the threshold voltage in association with a circuit state has heretofore been made. A change in the conventional back bias voltage is made by performing only switching between 0V and a weak bias voltage like +ΔV (small positive voltage) and between 0V and a reverse bias voltage like V (negative voltage) with 0V as the reference in either case. Therefore, even in the case of the switching between 0V and −V, the change width of the threshold voltage is small as shown in FIG. 2 and thereby the difference between leak currents at the circuit's operation and non-operation results in one digit at most as shown in FIG. 3 .

[0075] The invention of the present application is intended to perform the following contrivances for the purpose of making the high-speed operation and low power consumption of the digital circuit compatible. According to the present invention, when a voltage corresponding to an ON state is applied to the gate of the MOSFET in a state in which a weak forward bias voltage of +V 2 corresponding to such about +0.3V as not to influence the circuit operation is being applied to pn between the source of the MOSFET and the substrate (or well region), the intrinsic threshold voltage of the MOSFET is set so that a drain current is brought to a desired current value. Namely, upon design of a device structure, the intrinsic threshold voltage placed under the assumption that a potential identical to the source is applied to the substrate (or well region), is formed high. Further, a device size (principally channel length), a semiconductor impurity concentration (principally, substrate or well), and the thickness of a gate insulating film for the MOSFET are formed in such a manner that the drain current flowing at this time is also smaller than a desired drain current required in the circuit-operated state.

[0076] Thus, the intrinsic threshold voltage determined by the device structure of MOSFET is formed high as compared with an effective threshold voltage required upon an actual circuit operation. When it is desired to cause the CMOS circuit to perform its circuit operation, such a small positive voltage +V 2 that pn between the source of the MOSFET and the substrate (or well region) may be brought to a weak forward bias voltage, is applied. Further, its substrate effect is used to reduce the effective threshold voltage on a software basis based on, so to say, circuitry means, thereby obtaining a drain current necessary for the speeding up of the circuit operation.

[0077] When no circuit operation is done by the CMOS circuit, i.e., when an input signal remains unchanged, either the n channel type MOSFET or the p channel type MOSFET is brought to an off state. Therefore, no dc current would theoretically flow between the operating voltage and the circuit's ground potential. However, a tailing current or a subthreshold leak current is produced between the drain and source of the MOSFET kept in the OFF state, which in turn is used up or consumed as a dc current through the ON-state MOSFET.

[0078] The present invention is intended to, when the digital circuit is in the deactivated state as described above, apply such a negative voltage −V 1 that pn between the source of the MOSFET and the substrate (or well region) may be brought to a reverse bias voltage, and increase the effective threshold voltage through the use of its substrate effect on the software basis based on, so to say, the circuitry means, thereby reducing the leak current. Incidentally, the leak current can greatly be reduced one digit or more as compared with the conventional method for performing voltage switching within a range of 0V to −V 1 as shown in FIG. 3 .

[0079] It is to be noted that the simply switching of the substrate bias voltage to the weak forward bias voltage +V 2 and the back bias voltage −V 1 is not connected directly with a drastic reduction in the above-described leak current. Namely, the back bias setting method according to the invention of the present application will not miss that the intrinsic threshold voltage at the time that the source and the substrate are rendered identical in potential so that the effective threshold voltage in the weak forward bias state is brought to the threshold voltage necessary for the circuit operation, is formed greater.

[0080] It is also to be noted that the formation of the intrinsic threshold voltage greater as described above yields another advantage. When the operating voltage Vdd is reduced to achieve low power consumption, the level of the voltage supplied to the gate of the MOSFET is also reduced. It is thus possible to form thick the gate insulating film of the MOSFET at the time that a desired operating current, in other words, a desired operating speed is ensured, and to improve the reliability of each device.

[0081] The threshold-voltage characteristic diagram shown in FIG. 2 also exhibits another one. Namely, it shows that the substrate bias voltage can take a potential (0V) for causing the source and the substrate or well region to be identical in potential, in addition to the weak forward bias voltage like +V 1 and the back bias voltage like −V 1 , and three types of threshold voltages can be set correspondingly.

[0082] As signal processes executed by the digital circuit, may be mentioned, one which needs such a high-speed process as to determine the whole signal processing rate or speed, and one of a type wherein such a relatively low-speed process that it is subsidiarily done and as not to influence the whole processing speed so far will be enough. Accordingly, the weak forward bias voltage like +V 2 is supplied to a MOSFET of each circuit block for performing the high-speed process. As compared with it, 0V may be supplied to a MOSFET of each circuit block of such a type that the relatively low-speed process will be enough, when it is held in an operating state. Alternatively, a back bias voltage like −V 1 may be supplied to each MOSFET which constitutes a memory circuit or the like used to simply hold data.

[0083] Undershoot and overshoot exceeding an operating voltage are produced in an input signal supplied from an external terminal to an input/output circuit of a semiconductor integrated circuit device due to parasitic inductance components of a wiring formed on a printed circuit board, a bonding wire or the like of the semiconductor integrated circuit device. Thus, the CMOS circuit has the potential of causing latch up due to the undershoot and overshoot and a parasitic thyristor device of the CMOS circuit. It is therefore desirable that a fixed voltage corresponding to 0V or a source voltage is supplied to the substrate or well in the case of MOSFETs that constitute an input circuit for receiving the input signal supplied from the external terminal, and an output circuit for transmitting an output signal to the external terminal.

[0084] Thus, the digital circuit is divided into circuits according to the signal processing speed and operating conditions required of them. For each circuit, the threshold voltage may be selected from the three types of threshold voltages in combination in association with the respective circuits and circuit operating states, or any of them may be fixed. A MOSFET constituting one circuit may be switched to the three types of threshold voltages, in other words, it may be switched to three types on a time basis like +V 2 , 0V and −V 1 referred to above.

[0085] A block diagram showing a first embodiment of a processor chip to which the present invention is applied, is shown in FIG. 4 . In FIG. 4, a processor chip 101 is an LSI chip having a circuit of a CMOS structure, which includes a processor main circuit 102 , an operation mode controller 103 , and a substrate bias switching device 104 . The substrate bias switching device 104 receives therein a bias voltage 110 comprised of substrate bias voltages Vbp 1 and Vbp 2 for a p channel type MOSFET, and substrate bias voltages Vbn 1 and Vbn 2 for an n channel type MOSFET, outputs a bias voltage 111 for the p channel type MOSFET and a bias voltage 112 for the n channel type MOSFET, and transmits them to a bias voltage Vbp for a p channel type MOSFET of the processor main circuit 102 and a bias voltage Vbn for an n channel MOSFET thereof.

[0086] When the processor main circuit 102 is in a normal mode, the substrate bias switching device 104 sets the bias voltage Vbp for the p channel type MOSFET to Vbp 1 and sets the bias voltage Vbn for the n channel type MOSFET to Vbn 1 . When the processor main circuit 102 is in a standby mode, the substrate bias switching device 104 sets the bias voltage Vbp for the p channel type MOSFET to Vbp 2 and sets the bias voltage Vbn for the n channel type MOSFET to Vbn 2 . The substrate bias switching device 104 performs switching control corresponding to the operation mode and standby mode in accordance with a signal 107 outputted from the operation mode controller.

[0087] When the processor main circuit 102 is operated at such +1.8V and a ground voltage like 0V as given as an operating voltage Vdd of the processor main circuit 102 , the bias voltage Vbp 1 for the p channel type MOSFET is set to +1.5V, and the bias voltage Vbp 2 is set to +2.8V. Thus, the source of the p channel type MOSFET is supplied with the operating voltage Vdd like 1.8V referred to above. The substrate bias voltage Vbp is set to +1.5V in a circuit's operating state. A weak forward bias voltage of +0.3V is applied to pn between a source and a substrate (or well region). When the circuit is in a standby state, the substrate bias voltage Vbp is set to +2.8V, and a back bias voltage of −1.0V is applied to pn between the source and the substrate (or well region).

[0088] The bias voltage Vbn 1 for the n channel type MOSFET is set to +0.3V, and the bias voltage Vbp 2 is set to −1.0V. Namely, the source of the n channel type MOSFET is supplied with the operating voltage like 0V referred to above. The substrate bias voltage Vbn is set to +0.3V in the circuit's operating state. Thus, a weak forward bias voltage of +0.3V is applied to pn between the source and the substrate (or well region). When the circuit is in the standby state, the substrate bias voltage Vbn is set to −1.0V, and a back bias voltage of −1.0V is applied to pn between the source and the substrate (or well region).

[0089] Thus, when the processor main circuit 102 is in the normal operation mode for performing signal processing, pn between the sources of the n channel type MOSFET and the p channel type MOSFET and a well are brought to a weak forward bias state, and hence they are operated at low threshold voltages, respectively. Therefore, a large signal current flows to thereby allow the execution of a high-speed signal processing operation. When the processor main circuit 102 is in the standby mode free of any signal processing operation, pn between the sources of the n channel type MOSFET and the p channel type MOSFET and the well are brought to a back bias state, and hence they are brought into a high threshold voltage state, respectively. As a result, a threshold leak current that flows in each MOSFET kept in its OFF state, is suddenly reduced, so that current consumption in such a standby mode can greatly be reduced.

[0090] Incidentally, as will be described later, a well 302 with the processor main circuit 102 formed thereon is discretely formed independent of a well with the substrate bias switching device 104 and operation mode controller formed thereon.

[0091] Schematic cross-sectional views of device structures each showing a first embodiment of a semiconductor integrated circuit device like the processor chip 101 , to which the present invention is applied, are respectively shown in FIGS. 5 and 6 . In FIG. 5 , an n channel type MOSFET comprises an n type source and drain 202 formed in a p type substrate 201 , a gate insulating film 203 formed over a semiconductor region surface interposed between the source and drain 202 , and a gate electrode 204 formed over the gate insulating film 203 . On the other hand, a p channel type MOSFET comprises a p type source and drain 206 formed in an n type well region 205 formed in the p type substrate 201 , a gate insulating film 207 formed over a semiconductor region surface interposed between the source and drain 206 , and a gate electrode 208 formed over the gate insulating film 207 .

[0092] FIG. 6 is different from FIG. 5 in that a p well 302 is formed in an n type substrate 301 , and an n well 205 is formed in part of the surface thereof, i.e., a device having a triple well structure is formed. An n channel type MOSFET is formed in the surface of the p well 302 and a p channel type MOSFET is formed in the surface of the n well 205 to thereby constitute a CMOS circuit. FIG. 6 is similar to FIG. 5 in that as terminals for supplying substrate biases, the n well 205 of the p channel type MOSFET is provided with Vbp 209 and the p well 302 of the n channel type MOSFET is provided with Vbn 210 .

[0093] In the present embodiment, the processor main circuit 102 is formed within the p well 302 different from the operation mode controller 103 and the substrate bias switching device 104 . Thus, the influence of substrate bias control is effected on the processor main circuit 102 alone, and hence the operation mode controller 103 and substrate bias switching device 104 can avoid its influence. Schematic cross-sectional views of device structures each showing a second embodiment of a semiconductor integrated circuit device like the processor chip 101 , to which the present invention is applied, are respectively shown in FIGS. 7 and 8 . In the present embodiment, an SOI structure is used. Namely, an insulating layer (oxide) is formed in the surface of a semiconductor substrate, and a p type well region and an n type well region are formed in the surface of the insulating layer, thereby forming an n channel type MOSFET and a p channel type MOSFET in a manner similar to the above. Back bias voltage terminals Vbn and Vbp are respectively provided within the p type well region and the n type well region.

[0094] FIG. 8 is different from FIG. 7 in that a shallow groove isolation or insulator is formed between the p type well region and the n type well region, and an n channel type MOSFET portion and a p channel type MOSFET portion are perfectly electrically isolated from each other. Thus, since no parasitic thyristor device is formed when the n channel type MOSFET portion and the p channel type MOSFET portion are perfectly isolated from each other, particular latch-up measures can be made unnecessary. When the SOI structure is adopted, the parasitic capacitance as viewed from each of the back bias voltage terminals Vbn and Vbp provided within the p type well region and the n type well region is reduced, and hence the load placed upon such back bias voltage switching as described above can be reduced.

[0095] FIG. 9 is a flowchart for describing one example a substrate bias switching operation of the processor chip 101 shown in FIG. 4 , to which the present invention is applied. In the processor chip 101 according to the present embodiment, operation modes for the processor main circuit 102 include a normal mode for executing a normal command and a standby mode in which the execution of a command is not performed. The same drawing shows a process on the processor chip 101 where the operation mode transitions from the normal mode to the standby mode and from the standby mode to the normal mode.

[0096] First of all, the processor main circuit 102 is operated in the normal mode. At this time, the substrate bias switching device 104 selects Vbp 1 and Vbn 1 for the substrate biases Vbp 111 and Vbn 112 respectively. The voltage values of the substrate biases for the normal mode in the present embodiment are given as Vbp 1 =1.5V and Vbn 1 =+0.3V (Step 401 ).

[0097] When a sleep command is executed, the processor main circuit 102 bears a “standby request” on a signal 105 and outputs it therefrom, and transfers it to the operation mode controller 103 . Thereafter, the processor main circuit 102 suspends a command execution operation and proceeds to the standby mode (Step 402 ).

[0098] When the operation mode controller 103 has received the signal 105 from the processor main circuit, it outputs a signal 107 for switching the substrate bias of the processor main circuit 102 to a voltage for the standby mode. In response to the signal 107 , the substrate bias switching device 104 selects Vbp 2 and Vbn 2 for the substrate biases Vbp 111 and Vbn 112 from an input voltage 110 and outputs them, respectively (Steps 403 and 404 ). In the present embodiment, the voltage values of the substrate biases for the standby mode are given as Vbp 2 =2.8V and Vbn 2 =−1.0V.

[0099] When the operation mode controller 103 detects that a “standby release interrupt” is asserted over a signal 108 from the outside (Step 405 ) when the processor main circuit 102 is in the standby state, the operation mode controller 103 outputs a signal 107 for switching the substrate bias of the processor main circuit 102 to a voltage for the normal mode, and the substrate bias switching device 104 switches the substrate biases Vbp 111 and Vbn 112 to Vbp 1 (1.5V) and Vbn 1 (+0.3V) respectively in response to the signal 107 (Step 406 ).

[0100] Since some time is taken until each substrate bias voltage is stabilized after the switching of each substrate bias, there is a possibility that when the operation of the processor main circuit 102 is restarted immediately, it will malfunction. In order to avoid it, the operation mode controller 103 causes an onchip timer 109 to set a sufficient time necessary to stabilize the switched substrate bias voltage and start prior to the selection of the operation mode of the processor main circuit 102 (Step 407 ) and waits for the execution of a timeout (step 408 ).

[0101] After the timeout, the operation mode controller 103 bears a “standby release” on a signal 106 and outputs it therefrom, and transmits it to the processor main circuit 102 . In response to the signal 106 , the processor main circuit 102 proceeds to the normal mode, where it resumes a command execution operation (Step 409 ).

[0102] The substrate biases Vbp 111 and Vbn 112 for the processor main circuit 102 are controlled in the above-described manner. Upon its operation, the threshold voltage of each MOSFET constituting the processor main circuit is set low to cope with a high-speed operation. Upon its standby, the threshold voltage is set high to reduce a leak current.

[0103] A block diagram of a second embodiment of a processor chip according to the present invention is shown in FIG. 10 . In the present embodiment, an operation mode controller 103 is provided with a sensor 501 for detecting a bias voltage applied to a substrate of the processor main circuit 102 . When an operation mode of the processor main circuit 102 transitions from a normal mode to a standby mode, a routine procedure is identical to that shown in FIG. 9 . When the operation mode thereof transitions from the standby mode to the normal mode, the operation mode controller 103 controls a substrate bias switching device 104 in a manner similar to the first embodiment to thereby switch or change each substrate bias to a voltage for the normal mode. Thereafter, the operation mode controller 103 waits until the sensor 501 outputs, in the form of a signal 502 , that the switched substrate bias voltages have been stabilized at predetermined values, i.e., Vbp=1.5V and Vbn=+0.3V in the present embodiment. When the sensor 501 outputs the stability of the substrate biases as the output 502 , the operation mode controller 103 outputs a “standby release” in the form of a signal 106 and resumes the operation of the processor main circuit 102 .

[0104] A block diagram of a third embodiment of a processor chip according to the present invention is shown in FIG. 11 . The triple well structure shown in FIG. 6 or the SOI structures shown in FIGS. 7 and 8 is considered as a basic device structure of a processor chip 601 . In the processor chip 601 shown in FIG. 11, a processor main circuit comprises a plurality of function modules like a CPU 604 , a module A 606 and a module B 608 . The respective function modules exist on different well regions so as to be separated from one another and is placed under the uninfluence of substrate bias control of other function modules.

[0105] Each of the function modules includes ones given in smaller units such as a CPU, an FPU, a cache, or a computing unit, etc. Substrate bias switching devices 605 , 607 and 609 are respectively provided in association with the respective function modules 604 , 606 and 608 and respectively perform switching between substrate biases for the corresponding function modules in a manner similar to the above-described embodiment. The execution of a command is made with the CPU 604 corresponding to one of the function modules as the center. When a command for causing a function module unnecessary for the execution thereof to stand by is executed, the standby for the function module is transferred to an operation mode controller 602 .

[0106] The operation of the processor chip 601 according to the present embodiment will next be explained. Let's assume that all the function modules are first operated in a normal mode. When the CPU 604 executes a command for causing the module A to stand by, it bears this standby request on a signal 610 and outputs it therefrom. Thus, the present module is unavailable until the module A 606 is released from standing by subsequently.

[0107] In response to the signal 610 , the operation mode controller 602 outputs a signal 612 to the substrate bias switching device 607 to switch each substrate bias for the module A 606 to a voltage for a standby mode. When the operation mode controller 602 receives a signal for standby release of the module A 606 from the output signal of the CPU 604 or an external signal 613 supplied to the processor chip 601 when the module A 606 is placed in a standby state, the operation mode controller 602 outputs the signal 612 to the substrate bias switching device 607 and switches the substrate bias for the module A to a voltage for the normal mode. The operation mode control 602 waits for the stabilization of each switched substrate bias voltage through the use of an onchip timer 603 in a manner similar to the first embodiment of the present invention shown in FIG. 4 and notifies the release of the module A from standby to the CPU 604 through its stabilization. When the CPU 604 receives the signal 611 therein, it is capable of executing a command using the module A.

[0108] Standby control on the module B 608 and other function modules is similar to the above. Further, the CPU 604 per se is also an object to be subjected to the standby control. When, in this case, the CPU 604 proceeds to a standby mode, it suspends the execution of all commands. When the external signal 613 causes a signal for the release of the CPU 604 from standby to be asserted, the operation mode controller 602 causes the signal 611 to be asserted for the release of the CPU 604 from standby after the switching to each substrate bias of the CPU 604 has been completed. It is controlled in a manner similar to the case of the module A 606 except that the execution of the command by the CPU 604 is resumed. The standby control in the function module units employed in the present embodiment allows a reduction in leak current of each function module unnecessary upon the operation of the processor.

[0109] A block diagram of a fourth embodiment of a processor chip according to the present invention is shown in FIG. 12 . The present embodiment is different from the first embodiment shown in FIG. 4 in that the types of voltages 701 supplied from the outside to a substrate bias switching device 104 increase, and the substrate bias switching device 104 is capable of selecting suitable ones from those as substrate biases and applying the same to a processor main circuit 102 . The present embodiment is provided with means for dynamically changing an operating speed of a processor main circuit 102 , i.e., its operating frequency according to a command. Operation modes of the processor main circuit 102 include a high-speed mode and a low-speed mode.

[0110] In the present embodiment, Vbp 1 (for PMOS) and Vbn 1 (for NMOS) are selected as substrate biases corresponding to the high-speed mode, Vdd (for PMOS) and Vss (for NMOS) are selected as substrate biases corresponding to the low-speed mode, and Vbp 2 (for PMOS) and Vbn 2 (for NMOS) are selected as substrate biases corresponding to a standby mode. For example, the substrate biases for the high-speed mode are Vbp 1 =1.5V, Vbn 1 =+0.3V, the substrate biases for the low-speed mode are Vdd=1.8V and Vss=0V, and the substrate biases for the standby mode are Vbp 2 =2.8V and Vbn 2 =−1.0V.

[0111] The operation of the processor chip 101 according to the present embodiment will next be described. Now consider where the operation mode of the processor main circuit 102 is changed from the high-speed mode to the low-speed mode. While the processor main circuit 102 is being operated in the high-speed mode, the substrate bias switching device 104 selects Vbp 1 (1.5V) for Vbp 111 as the substrate bias of the processor main circuit and selects Vbn 1 (+0.3V) for Vbn 112 as the substrate bias. When a command for transition to the low-speed mode is executed by the processor main circuit 102 , the processor main circuit 102 bears its request on a signal 105 and outputs it therefrom to thereby interrupt a command execution operation. A clock supplied to the processor main circuit 102 is changed over to a low frequency under the execution of the command for transition to the low-speed mode. In response to the signal 105 , an operation mode controller 103 outputs a signal 107 to change the substrate biases for the processor main circuit 102 to voltages for the low-speed mode. In response to the signal 107 , the substrate bias switching device 104 switches the substrate biases Vbp 111 and Vbn 112 to Vdd (1.8V) and Vss (0V) respectively. The operation mode controller 103 waits for the stabilization of each switched substrate bias through the use of an onchip timer 109 in a manner similar to the above-described embodiment and notifies the completion of transition to the low-speed mode to the processor main circuit 102 . In response to the signal 106 , the processor main circuit 102 resumes the interrupted command execution operation in the low-speed mode.

[0112] Since operations at the switching from the low-speed mode to the high-speed mode, the switching from the high-speed mode or low-speed mode to the standby mode, or the switching from the standby mode to the high-speed mode or low-speed mode in the present embodiment are similar to the above, the details thereof will be omitted. In the present embodiment, the operating speed is further subdivided into parts, and substrate bias control associated therewith may be performed. As described in the third embodiment, the processor main circuit 102 is separated into the function module units through the use of the triple well structure or SOI structure for the device, and the substrate biases may be controlled according to the respective function modules in interlock with switching between their operating frequencies.

[0113] As in the present embodiment, the execution of substrate bias control suitable for each operating frequency of the processor makes it possible to reduce a leak current developed in the low-speed operation mode. Further, the present embodiment can obtain even the effect of reducing a through current at switching since the range of the input voltage in which both PMOS and NMOS transistors of the CMOS circuit are simultaneously brought into conduction in the low-speed mode, becomes narrow as compared with upon the high-speed operation mode.

[0114] FIG. 13 is a block diagram of a fifth embodiment of a processor chip according to the present invention. The present embodiment is different from the first embodiment shown in FIG. 4 in that the substrate bias switching device comprises a substrate bias generator 801 . The substrate bias generator 801 is controlled based on an output signal 802 of an operation mode controller 103 to thereby generate voltages for substrate biases thereinside and outputs the same to Vbp 111 and Vbn 112 .

[0115] The voltage values of the substrate biases Vbp 111 and Vbn 112 generated in association with an operation mode of a processor main circuit 102 under the control of the operation mode controller 103 are values similar to those employed in the first embodiment. Since the operations of the processor main circuit 102 and operation mode controller 103 are similar to the first embodiment, the details thereof will be omitted. Owing to the constitution of the substrate bias switching device employed in each of the second, third and fourth embodiments by the substrate bias generator 801 in a manner similar to the present embodiment, the substrate biases can be generated inside the processor chip and changed over according to the operation modes.

[0116] According to the respective embodiments as described above, since the timing provided to re-start the processor at the transition from the standby state to the operating state can accurately be controlled through the use of the timer or sensor, the most suitable substrate bias control corresponding to the operation mode of the processor can be carried out. Thus, the leak current can be reduced in the standby mode while the high speeding-up is being held when the operation mode of the processor is given as the normal mode. Controlling the substrate biases according to the operation modes set according to the function modules allows a reduction in leak current in each function module unnecessary for execution even if the processor is in operation. Also executing the substrate bias control suitable for the operating frequency of the processor yields the effect of reducing the through current at the switching as well as reducing the leak current in the low-speed mode. As a result, a microprocessor can be provided which is capable of effectively realizing a reduction in power consumption and combines a high-speed characteristic and a low power consumption characteristic.

[0117] An embodiment of a one-chip microcomputer will be described below specifically in connection with operation modes for controlling substrate biases. Now assume that a microprocessor has two power supplies or sources of 1.8V and 3.3V and performs substrate bias control based on 1.8V alone. A circuit for supplying 1.8V may preferably be comprised of a MOS transistor having a relatively low threshold value (e.g, Vth<about 0.4V) in a state in which the back bias voltages Vbp 1 and Vbn 1 in the high-speed mode are being supplied.

[0118] FIG. 14 shows one example illustrative of operation modes for a microcomputer. As the operation modes, may be mentioned, a normal operation mode 982 for performing a normal operation, and a reset mode 981 . As modes in which the microcomputer operates with low power consumption, may be mentioned, sleep mode 983 , deep sleep mode 984 , standby mode 985 , hardware standby mode 986 , and a RTC (Real Time Clock) battery backup mode. Further, an IDDQ measurement is used as a test mode.

[0119] Since a high-speed operation is required upon the normal operation 982 , such a voltage +V 2 that the source of each MOSFET and the well are brought to a weak forward bias state, is supplied as a substrate bias voltage. Since it is necessary to reset all the functions upon the rest 981 , such a voltage +V 2 that they are brought to the weak forward bias state, is supplied as the substrate bias voltage. In the low power consumption mode, such a voltage +V 2 that they are brought to the weak forward bias state, is supplied in the sleep mode 983 and deep sleep mode 984 short in recovery time as viewed from the low power consumption mode However, such a voltage −V 1 that the source of the MOSFET and the well are brought to a back bias state, is supplied in the case of the standby mode 985 and hardware standby mode 986 which places emphasis on a reduction in power consumption rather than on the recovery time.

[0120] The RTC battery backup mode is a mode for supplying only power for a RTC circuit operated at 3.3V. Since the transition to this mode is started from the low power consumption mode, such a voltage −V 1 that the source and well are brought to the back bias state, is supplied. Further, since the measurement of IDDQ is a mode for measuring a standby current and measuring a through current developed due to a short-circuit and failure in transistor, it is, in this case, necessary to assuredly supply such a voltage −V 1 that the source and well are brought to the back bias state to thereby reduce leak power of a chip and make it easy to find the failure.

[0121] A block diagram of one embodiment of a one-chip microcomputer according to the present invention is shown in FIG. 15 . Prior to the description of a low power consumption operation mode of the microcomputer according to the present invention, a description will be made of configurations of internal blocks in a processor main circuit 902 . As arithmetic or computing circuits, may be mentioned, a CPU (Central Processing Unit) 971 , and an FPU (Floating-Point Unit) 972 . There are also provided a cache 973 used as a memory built in a chip, a BSC (Bus Controller) 974 which performs interface to an external memory, a DMAC (DMA Controller) 975 which performs a DMA (Direct Memory Access), an SCI (Serial Controller) 976 which controls a serial port, an INTC (Interrupt Controller) 977 which controls an interrupt input, a CPG (Clock Controller) 978 which controls a clock, etc.

[0122] FIG. 16 shows the relationship between respective circuit blocks and operation modes for describing low power consumption modes of the one-chip microcomputer according to the present invention. As the low power consumption modes for the one-chip microcomputer according to the present invention, may be mentioned, three types of sleep mode 983 , deep sleep mode 984 , and standby mode 985 .

[0123] In the sleep mode 983 , only clocks for the computing devices such as the CPU 971 , FPU 972 , cache 973 , etc. are in a halt state, and such a voltage +V 2 that the source and well are brought into the weak forward bias state, is supplied as the substrate bias voltage. Therefore, although power consumption cannot greatly be reduced, the transfer of DMA by the DMAC 975 , and normal refreshes (1024 refreshes/16 milliseconds) of DRAM (Dynamic RAM) and SDRAM (Synchronous Dynamic RAM) by the BSC 974 can be carried out. Since the CPG 978 is in operation and such a voltage +V 2 as to bring about the above-described weak forward bias state is supplied, the recovery time from the sleep mode 983 to the normal operation mode 982 is made fast. Namely, the fast response of the computing device such as the CPU 971 , FPU 972 , cache 973 or the like can be implemented.

[0124] Since all the operation clocks are suspended and such a voltage −V 1 that the source and well are brought into the reverse bias state, is supplied as the substrate bias voltage in the standby mode 985 , power consumption is extremely low. The DMA transfer cannot be performed because no clocks are supplied. It is necessary that as to the refresh of the DRAM and SDRAM, control signals (RAS signal and CAS signal) for each individual memories are set by use of the BSC 974 so that the memories enter into such a self refresh mode that they per se perform refresh, prior to entering into the standby mode 985 . Since, however, the clocks are in the halt state, the recovery time from the standby mode 985 to the normal operation 982 becomes long because of standby or waiting for the stabilization of clock oscillations and the recovery time as viewed or counted from a substrate bias state.

[0125] The deep sleep mode 984 mode is a low power consumption mode placed between the sleep mode 983 and the standby mode 985 . As the substrate bias voltage, such a voltage +V 2 as to bring about the above-described weak forward bias state is supplied.

[0126] FIG. 17 shows the relationship between the respective circuit blocks and operation modes for describing the difference between sleep mode and deep sleep mode of the one-chip microcomputer according to the present invention. Since the BSC 973 , DMAC 974 and SCI 975 being activated upon the sleep mode 983 are deactivated upon the deep sleep mode 984 , power consumption can be reduced correspondingly. However, the DMA transfer cannot be performed in the deep sleep mode 984 , and the refresh for each memory also enters into self refresh. A recovery time from the deep sleep mode 984 to the normal operation mode 982 is made fast in a manner similar to the sleep mode. Setting the three types of low power consumption modes in this way allows fine low power consumption control according to uses.

[0127] A state transition diagram of one embodiment of the one-chip microcomputer according to the present invention is shown in FIG. 18 . A processor chip transitions from an off-state 980 of all powers to a reset state 981 in response to a RESET# 952 (or power-on reset) pin input. When the RESET# 952 is negated, the processor chip transitions to a normal operation 982 . It transitions from this state to a low consumption operation mode.

[0128] There are two transition methods. One of them is a command-based transition. This transition is made according to the execution of a sleep command by the CPU 971 . When the sleep command is executed, a mode register is set to allow the selection of the sleep mode 983 , deep sleep mode 984 and standby mode 985 and hence the transition to their modes is allowed. The recovery from the respective modes to the normal operation mode 982 corresponds to an interrupt 958 .

[0129] Another transition method is a transition based on a HARDSTB# 951 pin. When the pin is asserted, the processor chip transitions to a hardware standby state 986 . This state corresponds to a state in which all the clocks are suspended and substrate bias control is also in an executed state, in a manner similar to the standby mode 985 . When an input/output buffer is brought to high impedance in this mode, a 3.3V-system circuit can also avoid the action of a transistor into which a through current flows, whereby the measurement of IDDQ is allowed. If an input buffer of a RTC circuit placed in the 3.3V system is fixed, then a signal inputted to the RTC circuit is not brought to floating (intermediate level) even when power supplies other than that for the RTC circuit are turned off. It is therefore possible to prevent the RTC circuit from malfunctioning and activate only the RTC circuit.

[0130] An overall block diagram illustrating one embodiment of a microcomputer according to the present invention is shown in FIG. 19 . The same drawing shows a configuration of a processor chip 901 wherein hardware standby applied to all to thereby allow the replacement of a power supply 904 (battery) of the processor chip 901 , and a configuration of a power control circuit.

[0131] The processor chip 901 comprises a 1.8V region circuit 930 operated at 1.8V and a 3.3V region circuit 931 operated at 3.3V. The 1.8V region circuit 930 comprises a processor main circuit 902 and leveldown circuits 905 and 906 for performing level conversion of from 3.3V to 1.8V. The 3.3V region circuit 931 comprises a substrate bias generator 903 , a clock generator 908 , an IO circuit 909 , an operation mode controller 913 , a RTC circuit 914 , levelup circuits 904 and 910 for respectively performing level conversion of from 1.8V to 3.3V, and output fixing circuits 907 and 911 for respectively fixing signals from 3.3V to 1.8V. The power-system control circuit includes a power supply 904 , a power or voltage monitoring circuit 921 , a display 922 , and a voltage generator 920 for generating a 1.8V-system voltage.

[0132] The operation of the processor chip will he described below. When the processor chip 901 is in the normal operation mode 982 , the substrate bias generator 903 is supplied with such bias voltages Vbp 1 and Vbn 1 (equivalent to +V 2 referred to above) that substrate biases are brought to a weak forward bias state between the source of each MOSFET and the well in which it is formed, as described above. The clock generator 908 comprises a PLL (Phase Locked Loop) or the like. It generates a clock for each internal operation and transmits it to the processor main circuit 902 through the output fixing circuit 907 and the leveldown circuit 905 .

[0133] The IO circuit 909 takes in or captures a signal from outside and sends it to the processor main circuit 902 through the output fixing circuit 907 and the leveldown circuit 905 . Further, signals outputted from the processor main circuit 902 are outputted to the outside through the levelup circuit 904 . The RTC circuit 914 is operated at 3.3V and receives a control signal from the processor main circuit 902 through the levelup circuit 910 and transmits a control signal to the processor main circuit 902 through the leveldown circuit 906 and the output fixing circuit 911 . The operation mode controller 913 controls the substrate bias generator 903 in particular.

[0134] The voltage monitoring circuit 921 monitors the voltage level of the power supply 904 . When the voltage level falls below a predetermined level (the running down of the battery is detected) it brings HARDSTB# 951 to a low level. Simultaneously, the voltage monitoring circuit 921 causes the display 922 to display an alarm about the running down of the battery and notifies it to a user. Even when the voltage level is in a reduced state, the voltage holding circuit 923 is capable of holding the voltage level over a predetermined period (for a period from a few minutes to a few hours). During that period, the user is capable of replacing the power supply 904 with another.

[0135] A timing diagram for describing a power exchange sequence of a microcomputer system shown in FTG. 19 is shown in FIG. 20 .

[0136] (1) When the HARDSTB# 951 is brought to a low level, the operation mode enters a hardware standby mode 986 . Here, the operation mode controller 913 outputs a fixing 1.8V signal 953 or 1.8V signal fixing to fix a signal from 3.3V to 1.8V, and suspends a 1.8V clock too. Thus, since the 1.8V signal remains unchanged, a 1.8V-system circuit at the time that a substrate bias is drawn to or biased up to −V 1 , is prevented from malfunctioning.

[0137] (2) The operation mode controller 913 outputs a substrate bias control start signal 955 to the substrate bias generator 903 , based on the timing for the 1.8V signal fixing 953 . Between the signal fixing 953 and the substrate bias control start 955 , a signal is actually fixed and a time difference up to the suspension of the supply of the signal to the 1.8V region is set. The time difference can be measured by a timer, based on a RTC clock for the RTC circuit 914 .

[0138] (3) In response to the substrate bias control start signal 955 , the substrate bias generator 903 starts to bias a substrate bias for a 1.8V-system substrate up to −V 1 . During a period in which the substrate bias is being biased or settled down, the substrate bias generator 903 feeds back a signal 956 being under substrate bias control to the operation mode controller 913 .

[0139] (4) In a state in which the substrate bias is being biased up to −V 1 , the processor main circuit 902 is deactivated. Further, since a leak current is also less reduced, the amount of consumption of the current is small. Thus, the holding time of the voltage holding circuit 923 becomes also long.

[0140] (5) In this condition, the power supply 904 is replaced with another.

[0141] (6) Since the source voltage is returned to the normal level after its replacement, the HARDSTB# 951 is returned to a high level.

[0142] (7) Thereafter, a power-on reset circuit is operated to input RESET# 952 to the operation mode controller 913 . According to the reset input, the substrate bias control start signal 955 outputted from the operation mode controller 913 is released.

[0143] (8) In response to the release or cancellation of the substrate bias control start signal 955 , the substrate bias generator 903 starts to return the substrate bias of the 1.8V-system substrate to a potential (e.g., +V 2 in the case of PMOS, Vbn 1 (+0.3V) in the case of NMOS, and Vbp 1 (1.5V) in the case of PMOS) indicative of an operating state. A predetermined time is required to recover the substrate bias. When the substrate bias is brought back, the signal 956 being under substrate bias control is released or cancelled, so that its release is notified to the operation mode controller 913 .

[0144] (9) In response to the release of the signal 956 being under substrate bias control, the 1.8V signal fixing 953 outputted from the operation mode controller 913 is released, so that a signal is inputted to the 1.8V-system circuit such as the processor main circuit 902 or the like.

[0145] (10) After the completion of the reset state 81 , the processor chip 901 enters the normal mode 982 and hence the processor main circuit 902 starts its normal operation.

[0146] By using the low power consumption mode based on the hardware standby in the above-described manner, the power supply 904 can be replaced with another.

[0147] A timing diagram for describing a recovery sequence to a normal state of the microcomputer system shown in FIG. 19 is shown in FIG. 21 . The same drawing shows an example in which an operation mode enters a standby mode 985 through the use of a normal sleep command 959 , and the operation mode is recovered to a normal mode 982 according to an interrupt signal 958 .

[0148] (1) According to a sleep command 959 , the operation mode enters the standby mode 985 . Here, the operation mode controller 913 outputs 1.8V signal fixing 953 to fix a signal from 3.3V to 1.8V, and suspends a 1.8V clock too. Thus, a 1.8V-system circuit at the time that a substrate bias is drawn to or biased up to −V 1 corresponding to a low power consumption mode, is prevented from malfunctioning.

[0149] (2) Thereafter, the operation mode controller 913 outputs a substrate bias control start signal 955 to the substrate bias generator 903 , based on the timing for the 1.8V signal fixing 953 . Between the signal fixing 953 and the substrate bias control start 955 , a signal is actually fixed and a time difference up to the suspension of the supply of the signal to the 1.8V region is set. The time difference can be measured by a timer, based on a RTC clock for the RTC circuit 914 . (3) In response to the substrate bias control start signal 955 , the substrate bias generator 903 starts to bias a substrate bias for a 1.8V-system substrate up to −V 1 , e.g., to Vbp 2 (+2.8V) corresponding to −V 1 in the case of PMOS, and Vbn 2 (−1.0V) corresponding to −V 1 in the case of NMOS. During a period in which the substrate bias is being biased or settled down up to −V 1 , the substrate bias generator 903 feeds back a signal 956 being under substrate bias control to the operation mode controller 913 .

[0150] (4) In a state in which the substrate bias is being biased or settled down up to −V 1 , the processor main circuit 902 is deactivated. Further, since a leak current is also less reduced, the amount of consumption of the current is small.

[0151] (5) When the operation mode controller 913 receives the interrupt signal 958 via the IO circuit 909 through the use of a control signal 957 (external pin) in this condition, the operation mode controller 913 cancels or release the substrate bias control start signal 955 .

[0152] (6) In response to the release or cancellation of the substrate bias control start signal 955 , the substrate bias generator 903 starts to return the substrate bias of the 1.8V-system substrate to a potential indicative of an operating state, e.g., Vbp 1 (+1.5V) corresponding to +V 2 in the case of PMOS, and Vbn 1 (+0.3V) corresponding to +V