DESCRIPTION OF EMBODIMENTS

[0016] The following description and the drawings illustrate specific embodiments of the invention sufficiently to enable those skilled in the art to practice it. Other embodiments may incorporate structural, logical, electrical, process, and other changes. Examples merely typify possible variations. Portions and features of some embodiments may be included in or substituted for those of others. The scope of the invention encompasses the full ambit of the claims and all available equivalents.

[0017] FIG. 1 shows a delay locked circuit according to an embodiment of the invention. Delay locked circuit 100 includes an external node 102 for receiving an external signal XCLK and an internal node 104 for outputting and internal signal INTCLK. The XCLK signal propagates on two paths, a measuring path 106 and an output path 108 . Measuring path 106 has a measuring unit 110 for periodically performing a measurement to measure a timing of the XCLK signal. Output path 108 has an adjusting unit 112 for periodically adjusting a delay of output path 108 based on the measurement.

[0018] Measuring unit 110 includes a delay model circuit 114 and a converter 116 . During each measurement, delay model circuit 114 delays a signal by an amount of time T _DL . Converter 116 converts a reference time T _REF into a measured delay. T _REF is a measurement of time, whereas the measured delay is a quantity other than time but depending on T _REF .

[0019] Delay model circuit 114 is modeled after a combination of an input buffer 118 and an output buffer 120 so that a time delay of delay model circuit 114 , T _DL , equals the sum of a time delay of input buffer 118 , T _IN , and a time delay of output buffer 120 , T _OUT , (T _DL =T _IN +T _OUT ).

[0020] The XCLK signal has a cycle time T _CK . The sum of T _DL and T _REF equals one or more cycle times of the XCLK signal. MT _CK =T _DL +T _REF or T _REF =MT _CK −T _DL , where M is an integer equal to or greater than one.

[0021] Adjusting unit 112 includes a correction delay line 122 for applying a correction delay to the output path 108 based on the measured delay. The correction delay and the measured delay have an equal delay quantity.

[0022] On output path 108 , the XCLK signal propagates from node 102 through input buffer 118 , the correction delay line 122 , and output buffer 120 to become the INTCLK signal. The INTCLK signal and the XCLK signal are synchronized because the correction delay equals the measured delay. As shown in FIG. 1 , MT _CK =T _DL +T _REF where T _DL =T _IN +T _OUT , and the correction delay corresponds to T _REF . Thus, MT _CK =T _IN +T _OUT +T _REF . On output path 108 , T _IN +T _OUT +T _REF is the delay applied to the XCLK signal when it travels from node 102 to node 104 to become the INTCLK signal. Hence, the INTCLK signal is the XCLK signal delayed by T _IN +T _OUT +T _REF . Since MT _CK =T _IN +T _OUT +T _REF , the INTCLK signal is the XCLK signal delayed by MT _CK .

[0023] Delay locked circuit 100 further includes an interval controller 124 connected to measuring unit 110 . Interval controller 124 receives an input signal CLKIN and generates a measuring start signal START and a measuring stop signal STOP. The START and STOP signals control a time interval between one measurement and the next measurement and control the duration of each measurement. The START signal starts a measurement and the STOP signal stops the measurement. The START signal is a periodic signal. Interval controller 124 sets the time interval between one measurement and the next measurement to be equal to the cycle time of the START signal. Interval controller 124 sets the duration of each measurement to be one or more cycle times of the XCLK signal and less than the cycle time of the START signal.

[0024] FIG. 2 shows an example of a timing diagram for FIG. 1 . D 1 and D 2 indicate a time delay between the XCLK and INTCLK signals at time T0 and T3, respectively. Interval controller 124 activates the START signal (high) at time T0 to start a measurement and activates the STOP signal at times T1 to stop the measurement. Between these times, measuring unit 110 performs a measurement based on T _REF to obtain the measured delay. In FIG. 2 , the duration of the measurement is one cycle time of the XCLK signal. Therefore, M equals one and T _REF equals one T _CK minus T _DL . Between times T1 and T2, adjusting unit 112 applies a correction delay to output path 108 based on the measured delay. At time T2, the XCLK and INTCLK signals become synchronized. The process repeats between times T3-T4. At time T3, interval controller 124 activates the START signal again to start a new measurement. The XCLK and INTCLK signals may be out of synchronization at time T3. For example, at time T3, the XCLK and INTCLK signals have a delay D 2 . Adjusting unit 112 applies another correction delay based on the measured delay obtained by the new measurement.

[0025] The time interval between one measurement and the next measurement equals the cycle time of the START signal T _START . T _START =NT _CK , where N is greater than one. Thus, T _START is greater than T _CK . The STOP signal has a cycle time T _STOP . In FIG. 2, T _STOP equals T _START . In some embodiments, T _STOP is unequal to T _START .

[0026] The duration of each measurement equals the time interval between the activations of the START and STOP signals. This time interval equals MT _CK . In FIG. 2, M equals one. Therefore, the duration of each measurement equals one T _CK . In some embodiments, M is greater than one and less than N. Thus, the duration of each measurement equals more than one T _CK .

[0027] In FIG. 2 , since the time interval between one measurement and the next measurement equals T _START where T _START is greater than T _CK , the number of measurements based on T _START is less than the number of measurements based on T _CK . Therefore, using T _START instead of T _CK between one measurement and the next measurement saves power.

[0028] FIG. 3 shows more detail of the delay locked circuit of FIG. 1 . Converter 116 has a number of measuring delay elements (D) 302 . 1 - 302 .X connected to a number of storage elements (L) 304 . 1 - 304 X. Measuring delay elements 302 . 1 - 302 .X have output nodes to output signals M 1 -MX. A control logic 305 determines the contents of storage elements 304 . 1 - 304 .X to activate one of the select signals S 1 -SN. Correction delay line 122 having a number of correction delay elements (M) 306 . 1 - 306 .X, each being controlled by one of the S 1 -SN signals. The CLKIN signal enters correction delay line 122 at a variable entry point at any one of the inputs of correction delay elements 306 . 1 - 306 .X. The CLKIN signal exits the correction delay line 122 at fixed exit point at the output of correction delay elements 306 . 1 . Control logic 305 activates one of the select signals S 1 -SN to select the entry point.

[0029] Storage elements 304 . 1 - 304 .X can be flip flops, latches, registers, or other devices capable of storing a state (level) of a signal. Each of the measuring delay elements and each of correction delay elements delays a signal for an equal amount of delay.

[0030] In a measurement, interval controller 124 activates the START signal at a starting time of the measurement. For example, at starting time T0, the START signal is activated and propagates through delay model circuit 114 for a time equal to T _DL . At time T0+T _DL , the START signal enters measuring delay elements 302 . 1 and propagates through a certain number measuring delay elements for a time equal to T _REF . For example, the START signal propagates through three measuring delay elements during T _REF . At time T0+T _DL +T _REF , or after MT _CK from T0, the STOP signal is activated to enable storage elements 304 . 1 - 304 .X to latch the M 1 -MX signals.

[0031] Control logic 305 examines the contents of storage elements 304 . 1 - 304 .X to determine the last measuring delay elements reached by the START signal when the STOP signal is activated. Based on the contents of storage elements 304 . 1 - 304 .X, control logic 305 activates one of the S 1 -SN signals to select the entry point. The CLKIN signal enters the entry point and propagates through a number of correction delay elements equal to the number of measuring delay elements that the START signal propagates through during T _REF . The CLKIN signal becomes the INTCLK signal at node 104 .

[0032] In the example where the START signal propagates through three measuring delay elements during T _REF , control logic 305 activates the S 3 signal to select the entry point at correction delay element 306 . 3 . The CLKIN signal propagates from the entry point to node 104 through three correction delay elements 306 . 1 - 306 . 3 . Thus, the measured delay equals three measuring delay elements and the correction delay equals three correction delay elements. Since each of the measuring delay elements and each of correction delay elements delays a signal for an equal amount of delay, the correction delay equals the measured delay.

[0033] FIG. 4 shows another embodiment of correction delay line 122 of FIG. 3 . In FIG. 4 , the CLKIN signal enters correction delay line 122 at a fixed entry point at correction delay element 306 . 1 . The CLKIN signal exits correction delay line 122 at a variable exit point at any one of the outputs of correction delay elements 306 . 1 - 306 .X. Control logic activates one of the S 1 -SN signals to select the exit point. For example, when the S 3 signal is activated, the CLKIN signal exits correction delay line 122 at correction delay element 306 . 3 after propagating through three correction delay elements 306 . 1 - 306 . 3 .

[0034] FIG. 5 shows a delay locked circuit having counters according to an embodiment of the invention. Delay locked circuit 500 has measuring path 106 and output path 108 . Measuring path 106 has a measuring counter 502 . Output path 108 has a correction counter 504 . Measuring path 106 obtains a measured delay while counter 502 counts up during T _REF Output path 108 applies a correction delay equal to the measured delay while correction counter 504 counts down.

[0035] During time T _REF of a measurement, measuring counter 502 counts up from zero to a counted number. The START signal starts the count. The STOP signal stops the count. The counted number corresponds to the measured delay. Correction counter 504 loads the counted number and counts down from the counted number to zero. Based on the count down by correction counter 504 , output path 108 applies a correction delay to the CLKIN signal equal to the measured delay.

[0036] FIG. 6 shows a delay locked circuit having charge circuits according to an embodiment of the invention. Delay locked circuit 600 has measuring path 106 and output path 108 . Measuring path 106 has a measuring charge circuit 602 . Output path 108 has a correction charge circuit 604 . Measuring path 106 obtains a measured delay while measuring charge circuit 602 charges up during T _REF . Output path 108 applies a correction delay equal to the measured delay while correction charge circuit 604 discharges.

[0037] During time T _REF of a measurement, measuring charge circuit 602 charges up to a reference charge. The START signal starts the charging process. The STOP signal stops the charging process. The reference charge corresponds to the measured delay. The reference charge is transferred to correction charge circuit 604 , which discharges the reference charge. Based on the discharge by correction charge circuit 604 , output path 108 applies a correction delay to the CLKIN signal equal to the measured delay.

[0038] FIG. 7 shows an embodiment of interval controller 124 of FIG. 1 . Interval controller 124 includes a programmable frequency modifier 710 and a frequency shifter 712 . Programmable frequency modifier 710 divides the frequency of the CLKIN signal to generate the START signal. The cycle time of the START signal is greater than the cycle time of the CLKIN signal. Since the CLKIN signal is a delayed version of the XCLK signal, the CLKIN and XCLK signals have an equal cycle time. Therefore, the cycle time of the START signal is also greater than the cycle time of the XCLK signal.

[0039] Programmable frequency shifter 712 shifts the START signal by one or more cycle time of the XCLK signal.

[0040] Programmable frequency modifier 710 includes a plurality of flip flops 714 . 1 - 714 . n , each having two input nodes CLK and D, and two output nodes Q and Q*. In some embodiments, each of the flip flops 714 . 1 - 714 .N is a D-Q flip flop. Flip flops 714 . 1 - 714 . n form a frequency divider that divides the CLKIN signal into a plurality of selectable start signals ST 1 through STn. Each succeeding selectable start signal has a cycle time equal to twice the cycle time of the preceding selectable start signal. The STn signal has a cycle time equaled to 2″ times the cycle time of the CLKIN signal, where n is the total number of flip flops 714 . 1 - 714 . n.

[0041] A selector 716 selects one of the ST 1 -STn signals as the START signal based on a combination of select signals SEL 1 -SELx. In some embodiments, selector 716 is a n:1 multiplexor.

[0042] Programmable frequency shifter 712 includes a plurality of flip flops 718 . 1 - 718 . m , each having two input nodes CLK and D, and two output nodes Q and Q*. In some embodiments, each of the flip flops 718 . 1 - 718 . m is a D-Q flip flop. Flip flops 718 . 1 - 718 . m shift the START signal to provide a plurality of selectable stop signals SP 1 -SPm. Each succeeding selectable stop signal is shifted by one cycle time of the XCLK signal from the preceding selectable stop signal. The STm signal is shifted by m cycle time of the XCLK signal from the SP 1 signal, where m is the total number of flip flops 718 . 1 - 718 . m.

[0043] A selector 720 selects one of the SP 1 -SPm signals as the STOP signal based on a combination of select signals S 1 -Sy. In some embodiments, selector 716 is a m:1 multiplexor.

[0044] A programming circuit 722 connects to selectors 716 and 718 . Programming circuit 722 includes fuse devices, electrical fuse devices, laser fuse devices, storage elements, or other programmable elements. These elements are programmed to set a combination of the SEL 1 -SELx and S 1 -Sy signals to select the START and STOP signals.

[0045] FIG. 8 is a timing diagram for FIG. 7 . For clarity, FIG. 8 shows only the ST 1 , ST 2 , ST 3 , and STn signals. The XCLK signal has a cycle time T _CK . The ST 1 signal has a cycle time equaled to 2 ¹ times TCK (2 T _CK ). The ST 2 signal has a cycle time equaled to 2 ² times T _CK (4 T _CK ). The ST 3 signal has a cycle time equaled to 2 ³ times T _CK (8 T _CK ). The STn has a cycle time of 2 ⁿ times T _CK . In embodiments represented by FIG. 8 , the START signal is selected from the ST 2 signal as an example. In other embodiments, the START signal can be selected from any one of the ST 1 -STn signals.

[0046] FIG. 8 also shows only the SP 1 , SP 2 , and SPm signals for clarity. The SP 1 , and SP 2 signals are shifted from the START signal by one and two T _CK , respectively. The SPm signals are shifted from the START signal by mT _CK . In embodiments represented by FIG. 8 , the STOP signal is selected from the SP 1 signal as an example. In other embodiments, the STOP signal can be selected from any one of the SP 1 -SPm signals.

[0047] FIG. 9 shows memory device according to an embodiment of the invention. Memory device 900 includes a main memory 902 having plurality of memory cells arranged in rows and columns. The memory cells are grouped into a plurality of memory banks indicated by bank 0 through bank M (banks 0 -M). Row decode 904 and column decode 906 access the memory cells in response to address signals A 0 through AX (A 0 -AX) on address lines (or address bus) 908 . A data input path 914 and a data output path 916 transfer data between banks 0 -M and data lines (or data bus) 910 . Data lines 910 carry data signals DQ 0 through DQN (DQ 0 -DQN). A memory controller 918 controls the modes of operations of memory device 900 based on control signals on control lines 920 . The control signals include, but are not limited to, a Chip Select signal CS*, a Row Access Strobe signal RAS*, a Column Access Strobe CAS* signal, a Write Enable signal WE*, and an external signal XCLK.

[0048] Memory device 900 further includes a delay locked circuit 905 for delaying the XCLK signal to generate an internal signal INTCLK The INTCLK signal serves as a clock signal to control a transfer of data on data output path 916 . Delay locked circuit 905 periodically performs a measurement. The time interval between one measurement and the next measurement is unequal to the cycle time of the XCLK signal. Delay locked circuit 905 includes embodiments of delay locked circuit 100 ( FIG. 1 and FIG. 3 ).

[0049] In some embodiments, memory device 900 is a dynamic random access memory (DRAM) device. In other embodiments, memory device 900 is a static random access memory (SRAM), or flash memory. Examples of DRAM devices include synchronous DRAM commonly referred to as SDRAM (synchronous dynamic random access memory), SDRAM II, SGRAM (synchronous graphics random access memory), DDR SDRAM (double data rate SDRAM), DDR II SDRAM, and Synchlink or Rambus DRAMs. Those skilled in the art recognize that memory device 900 includes other elements, which are not shown for clarity.

[0050] FIG. 10 shows a system 1000 according to an embodiment of the invention. System 1000 includes a first integrated circuit (IC) 1002 and a second IC 1004 . IC 1002 and IC 1004 can include processors, controllers, memory devices, application specific integrated circuits, and other types of integrated circuits. In FIG. 10 , IC 1002 represents a processor and IC 1002 represents a memory device 1004 . Processor 1002 and memory device 1004 communicate using address signals on lines 1008 , data signals on lines 1010 , and control signals on lines 1020 .

[0051] Memory device 1004 includes embodiments of memory device 900 ( FIG. 9 ) including delay locked circuit 905 , which corresponds to delay locked circuit 100 ( FIG. 1 and FIG. 3 ).

[0052] System 1000 includes computers (e.g., desktops, laptops, hand-helds, servers, Web appliances, routers, etc.), wireless communication devices (e.g., cellular phones, cordless phones, pagers, personal digital assistants, etc.), computer-related peripherals (e.g., printers, scanners, monitors, etc.), entertainment devices (e.g., televisions, radios, stereos, tape and compact disc players, video cassette recorders, camcorders, digital cameras, MP3 (Motion Picture Experts Group, Audio Layer 3) players, video games, watches, etc.), and the like.

[0053] Although specific embodiments are described herein, those skilled in the art recognize that other embodiments may be substituted for the specific embodiments shown to achieve the same purpose. This application covers any adaptations or variations of the present invention. Therefore, the present invention is limited only by the claims and all available equivalents.