DETAILED DESCRIPTION OF THE INVENTION

[0032] Incorporation by Reference

[0033] The following patents and patent applications are hereby incorporated by reference as though fully and completely set forth herein:

[0034] U.S. Pat. No. 6,012,101 titled “Computer Network Having Commonly Located Computer Systems” issued on Jan. 4, 2000, whose inventors are Andrew Heller, Barry Thornton, Daniel Barrett, and Charles Ely;

[0035] U.S. Pat. No. 6,119,146 titled “Computer Network Having Multiple Remotely Located Human Interfaces Sharing a Common Computing System” issued on Sep. 12, 2000, whose inventors are Andrew Heller, Barry Thornton, Daniel Barrett, and Charles Ely;

[0036] U.S. Pat. No. 6,038,616 titled “Computer System With Remotely Located Interface Where Signals are Encoded at the Computer System, Transferred Through a 4-wire Cable, and Decoded at the Interface” issued on Mar. 14, 2000, whose inventors are Andrew Heller, Barry Thornton, Daniel Barrett, and Charles Ely;

[0037] U.S. Pat. No. 6,070,214 titled “Serially Linked Bus Bridge For Expanding Access Over A First Bus To A Second Bus” issued on May 30, 2000, whose inventor is Frank Ahern;

[0038] U.S. Pat. No. 5,764,924 titled “Method And Apparatus For Extending A Local PCI Bus To A Remote I/O Backplane” issued on Jun. 9, 1998, whose inventor is Soon Chul Hong;

[0039] U.S. Pat. No. 6,003,105 titled “Long-Haul PCI-to-PCI Bridge” issued on Dec. 14, 1999, whose inventors are Dominique Vicard, Jean-Paul Moiroux, and Pierre-Yves Thoulon;

[0040] U.S. patent application Ser. No. 09/728,667 titled “Computer On A Card With A Remote Human Interface” filed on Dec. 1, 2000, whose inventors are Andrew Heller and Barry Thornton; and

[0041] U.S. patent application Ser. No. 09/728,669 titled “A System Of Co-Located Computers In a Framework Including Removable Function Modules for Adding Modular Functionality” filed on Dec. 1, 2000, whose inventor is Barry Thornton.

[0042] U.S. patent application Ser. No. 09/619,989 titled “System and Method for Providing a Remote Universal Serial Bus” filed on Jul. 20, 2000, whose inventor is Barry Thornton.

[0043] U.S. patent application Ser. No. 09/680,760 titled “System and Method for Combining Computer Video and Remote Universal Serial Bus In An Extended Cable” filed on Oct. 6, 2000, whose inventor is Barry Thornton.

[0044] FIG. 2 —Computer System with Multiple Display Devices

[0045] FIG. 2 illustrates a computer system which supports multiple display devices, i.e., computer monitors, according to one embodiment of the present invention. The computer at the first location, the monitors and frame pods at the second location, and the human interface may include other devices not shown here. As FIG. 2 shows, in this approach, the computer 102 may couple to a first frame pod 206 A via the cable 104 . As FIG. 2 also shows, the first frame pod 206 A may couple to monitor 108 A. Additionally, the first frame pod 206 A may couple to a second frame pod 206 B, which may couple to monitor 108 B, as well as frame pod 206 C. Frame pod 206 C may couple to monitor 108 C and frame pod 206 D. Finally, frame pod 206 D may couple to monitor 108 D. Each frame pod 206 D may comprise a frame grabber as described below. In another embodiment, the frame pods may be implemented in each of their respective monitors, and hence separate frame pods may are not necessary. It should be noted that, although the system shown includes four monitors, that in various embodiments, the system may also include a greater or lesser number of monitors, and that the methods disclosed herein apply equally. Furthermore, other embodiments are possible and contemplated wherein each of the frame grabbers is stored within a single box. In general, a wide variety of configurations for arranging the frame pods/grabbers are possible and contemplated.

[0046] Thus, the frame pods 206 /monitors 108 may be linked to the computer 102 in serial fashion via the cable 104 . It should be noted that in another embodiment, the computer 102 may couple to the first frame pod 206 A through a network, such as the Internet.

[0047] In one embodiment, the computer 102 stores a video image or frame for each of the monitors 108 A-D. The computer 102 generates multiplexed video sequences, wherein the video frames are multiplexed together in a time-division multiplexed fashion. In another embodiment, the video frames may be multiplexed together using frequency division multiplexing. The multiplexed video signals may be transmitted from the computer 102 over the cable 104 to the first frame pod 206 A. The first frame pod 206 A may extract video signals targeted to the monitor 108 A, if any, and transmit the extracted signals to the monitor 108 A. The multiplexed video signals may then be sent by the first frame pod 206 A to the second frame pod 206 B. The second frame pod 206 B may similarly extract video signals targeted to the monitor 108 B, if any, and transmit the extracted signals to the monitor 108 B, sending the multiplexed signals on to the third frame pod 206 C, which, in turn, may extract video signals targeted to the monitor 108 C, if any, and transmit the extracted signals to the monitor 108 C, sending the multiplexed signals on to the fourth frame pod 206 D. The fourth frame pod 206 D may extract video signals targeted to the monitor 108 D, if any, and transmit the extracted signals to the monitor 108 D. The extraction of video signals for each monitor may be performed by a respective frame grabber in each frame pod 206 , as described below with reference to FIG. 3 .

[0048] It is further noted that the serial transmission of the multiplexed video signals to the respective frame pods 206 and monitors 108 may substantially reduce cabling requirements for the system, also resulting in a concomitant reduction in the number of cables which must be “pulled” through walls, ceilings, etc. in the installation of the system. Further details of this serial transmission of video signals from the computer to the succession of frame pods 206 and their respective monitors are described below with reference to FIGS. 3 - 13 .

[0049] FIG. 3 —Block Diagram of the Multiple Monitor System

[0050] FIG. 3 is a block diagram showing the primary functional elements of the multiple monitor system of FIG. 2 , according to one embodiment. As FIG. 3 shows, multiple images 302 A- 302 D may be provided, e.g., by the computer 108 . More specifically, FIG. 3 illustrates a series of (four) video images 302 A- 302 D, also referred to as ‘frames’, sequentially selected and transmitted some distance to a series of frame grabbers (comprised in the frame pods 206 of FIG. 2 ) over a single cable 104 . In other words, the images may be sequentially fed to multiple frame grabbers 306 and then fed to the associated monitors 108 . As used herein, the term frame grabber is intended to refer to a unit configured to identify frames targeted for an associated monitor, and to forward these frames to the associated monitor, where they may then be displayed.

[0051] As FIG. 3 also shows, the system may include a single cable distancing system 304 , which may be operable to extend the operational distance for a human interface, i.e., the multiple monitors and/or other human interface devices, located remotely from the computing system 102 . For more information regarding the extension of operation distance from the computer to a remote human interface, please see U.S. Pat. No. 6,038,616 titled “Computer System With Remotely Located Interface Where Signals are Encoded at the Computer System, Transferred Through a 4-wire Cable, and Decoded at the Interface” issued on Mar. 14, 2000, U.S. Pat. No. 6,070,214 titled “Serially Linked Bus Bridge For Expanding Access Over A First Bus To A Second Bus” issued on May 30, 2000, U.S. patent application Ser. No. 09/619,989 titled “System and Method for Providing a Remote Universal Serial Bus” filed on Jul. 20, 2000, and U.S. patent application Ser. No. 09/680,760 titled “System and Method for Combining Computer Video and Remote Universal Serial Bus In An Extended Cable” filed on Oct. 6, 2000, all of which were incorporated by reference above.

[0052] In one embodiment, each of the images in the sequence of images or frames 302 may include a unique identifier indicating a target display, e.g., a target monitor. Each frame grabber 306 may examine the frame identifier, and when the appropriate frame grabber 306 detects an appropriate frame 302 , the frame grabber 306 may grab or extract the frame from the serial signal and transmit the grabbed frame or image 302 to the corresponding monitor. Thus, each frame grabber 306 may be operable to analyze the multiplexed video signal, detect, and extract the appropriate frame 302 from the signal, and send the frame 302 to the associated monitor 108 .

[0053] FIG. 4 —Computer Blade Based System with I/O Device Signals

[0054] FIG. 4 illustrates one embodiment of a multi-monitor system where the computer 108 comprises a “computer on a card” or “blade computer” 102 A. As shown in FIG. 4 , the blade computer 102 A may serially couple to a series of frame pods 206 , as described above. As also described above, each of the frame pods 206 may couple to a respective computer monitor 108 . As is commonly known in the art, the blade computer 102 A includes most or all of the functional components of a computer, e.g., processor, memory, power supply, etc., packaged with a blade or drawer form factor, such that multiple computers (blades) 102 A may be co-located, e.g., in a rack or cage, thereby significantly reducing the space requirements for the computers. For more information on blade computers and co-located computer systems, please see U.S. patent application Ser. No. 09/728,667 titled “Computer On A Card With A Remote Human Interface” filed on Dec. 1, 2000, and U.S. patent application Ser. No. 09/728,669 titled “A System Of Co-Located Computers In a Framework Including Removable Function Modules for Adding Modular Functionality” filed on Dec. 1, 2000, which were incorporated by reference above. It should be noted that the use of a blade computer as the computer 102 is meant as an example only, and is not intended to limit the type of computer 102 used in the system to any particular type or form.

[0055] In this embodiment, a software driver executing in the blade computer 102 A may map images out of memory as sequential frames ( 302 A- 302 D). The frame pods 206 , i.e., the frame grabbers 306 A- 306 D, may each be operable to select or pick off an assigned frame of video and play it back to the respective monitor 108 at full refresh rate. It is noted that in one embodiment, the number of unique monitors supported in the system may be a function of video chip memory and a specified lowest acceptable rewrite rate, discussed in more detail below. Again, it is noted that the number of monitors/frames described herein is exemplary only, and is not intended to limit the number of monitors or frames to any particular value. Additionally, it is noted that in some embodiments of the system, the number of frames and the number of monitors may differ. For example, in an airport terminal application of the system, various monitors may display the same information. Thus, in a simple example, three images may be distributed over nine monitors, where the first two images may each be displayed on four monitors, and the third image may be displayed on the ninth monitor. This type of flexibility is provided by the ability of each frame pod 206 to examine the combined or multiplexed video signal and extract any video frame based on the frame identifier.

[0056] As FIG. 4 also shows, the final frame pod in the series, in this example, frame pod 206 B, may couple to a USB (universal serial bus) pod 208 . The USB pod 208 may couple to one or more I/O devices. also referred to as human interface devices, e.g., keyboard 410 , mouse 411 , included in the computer system's HI. The USB pod may thus terminate the line and process signals for all the HI devices. The USB pod may also be operable to receive user input from the HI devices and transmit the HI device signals through the cable 104 (and all of the frame pods 206 ) back to the computer 102 A.

[0057] FIGS. 5 A- 5 C—Video Frame Management

[0058] FIGS. 5 A- 5 C illustrate video frame management in a computer system, according to one embodiment. FIG. 5A shows a sequence of video frames delivered to the monitor at a selected refresh rate. In a typical computer video display system the CPU will map instructions to build a video image out of memory and into a video processor, e.g., a graphics card. The video processor may take these digital instructions from memory and create, along with proper synchronization information, a video image which may be output as a sequential series of image lines whose aggregation constitutes the video ‘frame’ 1 502 A, i.e., one complete screen or “Window” of video information. This process may continue unabated at a rate typically between 60 and 85 frames per second. This signaling is repetitious, in that the same block of video data is output for a single monitor installation. This block of video data is typically rewritten by the computer 102 as needed to keep the screen's or window's contents current. Several ‘screens’ may reside in the computer's memory and may be written over each other as selected from the active windows screen by either keystrokes or mouse clicks.

[0059] In a typical computer application the multiple window capabilities, e.g., of Microsoft Windows 2000 or XP are supported by a section of memory assigned to hold the data constituting the windows. FIG. 5B illustrates a simplified version of the process. As FIG. 5B shows, multiple windows 504 A- 504 C, i.e., video images, may be stored in computer memory 510 , each with a start and stop location in the memory address space. These data are typically selected by the video driver to be rendered to through the video card out to the monitor in a standard VESA protocol (component color video plus synchronization data signals). This process is essentially the selection of the start and stop memory locations for the window of choice. Thus, in response to user input, such as a mouse click activating or selecting a window as the active window, the video card may select one of the windows, i.e., memory locations, for display, as shown in FIG. 5B . The data at the selected memory location, i.e., the selected window 504 A, may then be converted by the video card 506 to an analog video signal 508 , as shown.

[0060] In one embodiment of the present invention, the stream of frames shown in FIG. 5A may be modified such that each frame may be displayed on a different monitor. In other words, the video driver/processor may be altered such that switching between windows 504 may be performed automatically on a frame basis. In other words, for a three-monitor example, the video processor 506 may first select and render a first frame, 6 1 For the sake of this RFQ it is assumed that the reader is fully familiar with the VESA defined VGA, SVGA, XVGA, and etc. video signaling protocols employed in contemporary Personal Computer Video Technology. comprising the data of window # 1 504 A. With the completion of the rendering of a frame of Window # 1 , the ‘switch’ may be advanced to the memory for Window # 2 and that frame rendered. Finally, the process may select the Window # 3 and render its frame, after which the process returns to Window # 1 . This process may be extended to support Window # 1 to Window #‘n’, where the value ‘n’ may be determined and stored in the system during setup or initialization, or may be modified later, and remembered by the computer until changed.

[0061] FIG. 5C illustrates an example video output stream for an “n-window” system. The n frames 512 A- 512 Z may be transmitted sequentially as shown, where the sequence cycles back to frame 1 512 A once all of the frames have been transmitted. As FIG. 5C shows, frames 1 512 A through frame n 512 Z may each have an associated frame ID 513 A- 513 Z. These IDs may be used to identify and select each frame from the combined or multiplexed video stream, as mentioned above. In one embodiment, each frame grabber 306 may have an ID which may be matched to the frame ID to indicate that the frame grabber 306 is to extract the frame for display on the respective monitor 108 . An example of the placement of this frame ID 513 is described below with reference to FIG. 6 .

[0062] FIG. 6 —Encoding Format for Frame ID

[0063] FIG. 6 illustrates frame timing, according to one embodiment, and more specifically, FIG. 6 illustrates one embodiment of a format for encoding the frame IDs mentioned above with reference to FIG. 5C . As FIG. 6 shows, for each rendered frame, a simple frame identifier may be inserted to tag the frame. In this example embodiment, the frame ID may be located in the first line of the ‘blue’ video stream 606 . In an embodiment where four different frames and/or displays are supported, the frame ID may comprise 2 bits, 3 microsecond long, starting 4 microseconds after the end 612 of the first Hsync 604 that occurs during Vsync 602 . Frame # 1 may be coded as ‘00’, frame # 2 as ‘01’ frame # 3 as ‘10’, and frame # 4 as ‘11’.

[0064] It is clear that in such a system the rate of refresh of the video driver may be independent of the refresh rate of the individual monitors. That is the video output of the computer can operate at the lowest rate possible in an effort to reduce the bandwidth of the signal being transferred down the cable connecting the computer and the monitors. The monitors can operate at their highest refresh rate for the user's satisfaction and viewing ease. Clearly a large number of monitors would significantly slow the actual frame data transfer rate and may produce a ‘jumpy’ image on the monitor when used with rapidly changing video data, i.e., ‘action video’. It is anticipated that for normal ‘business’ graphics and video this may not be of consequence. A further possible consequence of the distribution of the frame rate across multiple monitors is “mouse jump”, in which the cursor or mouse may appear to be ‘sticky’, remaining in one location for a period, then suddenly jumping to another location, skipping the mouse positions in between. This issue is addressed below with reference to FIG. 7 .

[0065] FIG. 7 —Video Frame Sequencing

[0066] FIG. 7 illustrates video frame sequencing, according to one embodiment. More specifically, FIG. 7 illustrates a video frame sequencing scheme which addresses the “sticky mouse” issue mentioned above. In this embodiment, the frame 702 containing the mouse/cursor information may be sent on an every-other-frame basis to eliminate the jerkiness of the mouse that would result from a too infrequent refresh. Such an output is illustrated in FIG. 7 for a 4 screen (frame) implementation with frame # 2 702 having the mouse in it. Thus, the frame sequence is frame 1 512 A, frame 2 512 B, frame 3 512 C, frame 2 512 B, frame 4 512 C, frame 2 512 B, frame 1 512 C, and so on, as FIG. 7 indicates, wherein frame 2 512 B is the mouse frame 702 .

[0067] FIG. 8 —Block Diagram of a Dual Monitor System Based on Nvidia GEForce Video Chip

[0068] The video Window data stream described above can be produced in at least three ways. The first is pure software, that is, the video processor driver software may be altered so that the video processor fully manufactures the data stream. A second approach is to perform the process in hardware. For example, several independent video processors may be used to create the images and to multiplex the signals for the images into a single line. FIG. 8 is a block diagram of this second approach, as applied to an Nvidia GEForce Video Chip, according to one embodiment. It is noted that the use of the Nvidia GEForce Video Chip is exemplary only, and is not intended to limit the video card or chipset used in the invention to any particular type. The third method is a combination of the two, that is most of the frame is created by the software and the video processor, the additional information (including but not limited to the frame ID) may be added by additional hardware.

[0069] As FIG. 8 shows, in this example, the system is a dual monitor drive system based on the Nvidia GEForce video chip. This device 804 has two independent outputs, analog and digital, managed by existing Nvidia software. The system may multiplex frames from these two outputs down a single cable 104 , e.g., a Category 5 cable, to be captured by a pair of frame stores (grabbers) 306 A and 306 B and distributed to respective monitors 108 A and 108 B, as illustrated.

[0070] More specifically, the Nvidia based video card 804 has two outputs, output # 1 , which is a digital signal converted to analog via an on-card DAC 816 , and output # 2 , which is analog. Based on the VSync, the output of the card 804 may be multiplexed between the two outputs on a frame-by-frame basis. This output may be based on an alternating presentation of the frames, e.g., a frame from output # 1 , then a frame from output # 2 , then a frame from output # 1 , and on. It is understood that this may cause some discontinuity in the signal output, that is frame # 2 may not be ready for transmittal at the end of frame # 1 .

[0071] FIG. 9 —Video Multiplexing Scheme for the Dual Monitor System of FIG. 8

[0072] In the embodiment of FIG. 8 , the NVidia chip has asynchronous outputs, in that the two channels are generated from independent clocks such that when both channels are refreshing at the same rate the actual V and H Sync signals have slightly different periods or frequencies, e.g., 5 to 10 Hz difference, which is the result of independent sources. This feature allows each output to operate at a different refresh rate without complex internal calculations or frequency synthesis.

[0073] FIG. 9 illustrates a video multiplexing scheme for the dual monitor system of FIG. 8 , according to one embodiment. The basic multiplexing scheme is to send every other frame down the line. In practice, there may be a gap between the frames of up to just less than two whole frames, thus, in a worst case scenario, the system may capture what is effectively every third frame rather than every other frame, as FIG. 9 indicates.

[0074] At the top of FIG. 9, a best or ideal case is illustrated, where a first video output 902 A and a second video output 904 A are shown with equal period or frequency. Thus, in the ideal case, the two video frame sequences may be multiplexed together seamlessly, with no frame losses or asynchronicities. In contrast, in the expected case, the frequencies of video # 1 902 B and video # 2 904 B may differ such that every third frame of each video stream is selected and multiplexed for transmission to the monitors, as shown by the video streams 902 C and 904 C, resulting in the video stream output 906 . Therefore, at 75 Hz refresh one may expect to see about 27 rewrites per second. This will probably not be noticeable when moving the mouse, although there will likely still be gaps in the video stream. As mentioned above, it is expected that for most applications, e.g., business applications, the slightly slower data presentation rate will be acceptable.

[0075] FIG. 10 —Video Encoding Scheme for the Dual Monitor System of FIG. 8

[0076] FIG. 10 illustrates a video encoding scheme for the dual monitor system of FIG. 8 , according to one embodiment. As FIG. 10 shows, frames from video input 1 1010 A and video input 2 1010 B may be multiplexed based on information included in the frame. Such frame data 1011 may include Vsync 1 1001 A, Hsync 1 1002 A, Vsync 2 1101 B, and Hsync 1 1002 B, as well as Blue 1 1003 A, Blue 2 1003 B, an identified output 1004 , and a switch signal slot 1005 . The particular data stored in each frame may occupy respective time slots in the transmitted frame signal.

[0077] In this process the vertical and horizontal synchronization signals for the two video streams, Vsync 1 1001 A, Hsync 1 1002 A, Vsync 2 1001 B, and Hsync 1 1002 B, are the operative stimulants for the system, controlling the sequencing of the two input video frame streams 1010 A and 1010 B. The lines to the blue signals, Blue 1 1003 A and Blue 2 1003 B may transition from a tri-stage or high impedance state to that of high (1 Volt) to indicate the presence of data. The time slot marked ‘ID’d Output' 1004 may differentiate the two videos for a given board. The time slot marked ‘SW’ may be used when 4 such frame grabbers are used and 4 video signals are present on the line, as indicated by the 2/4 mode switch 1006 . One example of process flow for the multiplexing process is described below with reference to FIG. 11 .

[0078] FIG. 11 —Flowchart for Generating Video Signals in a Dual Monitoring System

[0079] FIG. 11 is a flowchart of a method for generating video signals in the dual monitor system described above with reference to FIGS. 8 - 10 , according to one embodiment. As FIG. 11 shows, the same basic steps are performed for a frame from each video stream. In this example, a frame from video stream 1 1010 A is processed first, then the equivalent steps performed for a frame from video stream 2 1010 B.

[0080] In 1101 , the presence of the VSync 1 1001 A is tested. In other words, the method determines if the vertical sync signal for the first video stream 1010 A is present. If the VSync 1 1001 A is not present, the method step repeats, as shown, until the VSync 1 signal is detected.

[0081] Once the VSync 1 1001 A is detected, then in 1102 , the signal of the first video stream 1010 A may be output, as indicated. Then, as 1103 shows, the method may repeatedly check for the end of the Hsync 1 signal 1002 A, i.e., the end of the horizontal sync signal for the first video stream 1010 A. When the end of the Hsync 1 1002 A is detected, then in 1104 a delay time 1 may be inserted into the stream, and in 1105 , the blue 1 signal line set to low, as shown.

[0082] Then, in 1106 , a delay time 2 may be inserted into the stream, and the blue 1 signal line set to SW, as shown in 1107 . A delay time 3 may then be inserted into the stream, as indicated in 1108 , and the blue 1 signal line set to low again, 1109 shows. The method may then check for the presence of the VSync 1 signal, as 1110 shows. Once the VSync 1 signal is detected, the video 1 frame is complete.

[0083] Once the video 1 frame has been completed, then the above steps are effectively repeated, but with frame data from video 2 1010 B. Thus, in 1111 , the presence of the VSync 2 1001 B is tested, and if the VSync 2 1001 B is not present, the method step repeats until the VSync 2 signal is detected.

[0084] Once the VSync 2 1001 B is detected, then in 1112 , the signal of the second video stream 1010 B may be output, as indicated. Then, the method may repeatedly check for the end of the Hsync 2 signal 1002 B, i.e., the end of the horizontal sync signal for the second video stream 1010 B, as 1113 shows,. When the end of the Hsync 2 1002 B is detected, then in 1114 a delay time 1 may be inserted into the stream, and in 1115 , the blue 2 signal line set to low, as shown.

[0085] Then, in 1116 , a delay time 2 may be inserted into the stream, and the blue 2 signal line set to SW, as shown in 1117 . A delay time 3 may then be inserted into the stream, as indicated in 1118 , and the blue 2 signal line set to low again, 1119 shows. The method may then check for the presence of the VSync 2 signal 1001 B, as 1120 shows. Once the VSync 2 signal is detected, the video 2 frame is complete.

[0086] Thus, in one embodiment, the method may receive two video frame streams and multiplex the streams together on a frame by frame basis, based on information included in the frame data. Thus, each frame grabber may implement a method of saving a frame or window and then replaying it to the respective monitor. A more detailed block diagram of a frame grabber 306 is shown in FIG. 12 , described below.

[0087] FIG. 12 —Frame Grabber

[0088] FIG. 12 illustrates a process for receiving and distributing video frames in a multi-monitor system, according to one embodiment. In this process the video signal is fed to all the frame grabbers 306 , which then perform the extraction of the appropriate frame for sending to a respective monitor. As FIG. 12 shows, a video signal 1210 may be received by an equalizer and line interface 1202 . The video signal may be interfaced and equalized to compensate for cable issues of time and frequency.

[0089] The video signal 1210 may then be split and sent to a Phase Locked Loop (PLL) element 1204 and an analog/digital converter 1206 , as shown. In one embodiment, the basic pixel clock rate may be extracted by the PLL to operate as the local clock. The image may be converted from analog to digital by the analog/digital converter 1206 , and fed to the memory 1212 . As FIG. 12 also shows, the control module may access the frame data, examining the first line of each frame for its ID code. In one embodiment, all first lines may be the same, and so may simply be written over in the memory. If the frame ID is the same as the frame grabber ID then the rest of the video image may be saved.

[0090] Once the video image is saved, the video image or frame may be sent to a digital/analog converter 1208 which converts the digital frame to an analog signal. The control module 1220 may then send the resulting signal to the associated monitor 108 .

[0091] FIG. 13 —Frame Grabber Input and Output

[0092] FIG. 13 illustrates the relationship between the first frame-grabber's input 1302 and output 1304 , according to one embodiment. As FIG. 13 shows, a sequential video stream 1302 may be received from the computer 102 . In this example, the video sequence comprises frame 1 A 1312 A, frame 2 A 1314 A, frame 3 A 1316 A, and frame 4 A 1318 A, followed by frame 1 B 1312 B, frame 2 B 1314 B, frame 3 B 1316 B, and so on. In other words, video frames from 4 inputs are multiplexed together. Once the frames for a given cycle, e.g., ‘A’, for the inputs are input, then frames for the next cycle, e.g., ‘B’, are input.

[0093] As FIG. 13 shows, the frame grabber 306 A identifies and ‘grabs’ frame 1 A 1312 A, based on the frame's ID (by matching it with the frame grabber's ID). The frame grabber 306 A may then send the grabbed frame 1 A 1312 A repeatedly to the monitor 108 A, as shown in the first four frames of the output stream 1304 . Then, once the frame grabber 306 A detects the next frame from the first video source, i.e., frame 1 B 1312 B, the frame is extracted and sent to the monitor 108 A, as shown. In one embodiment, the output frames may be sent to the monitor 108 A at the monitor's refresh rate. Thus, the rates of the input and the output may differ, e.g., the frame grabber 306 A may receive frames at a first rate, e.g., 60 Hz, while sending the output frames to the monitor 108 A at a different rate, e.g., 75 Hz.

[0094] Thus, various embodiments of the systems and methods described herein may provide means for driving multiple monitors with a single computer, where multiplexed video frames may be transmitted over a single serial cable, and extracted sequentially by frame grabbers associated with respective monitors. Some of the points of novelty of various embodiments discussed herein include, but are not limited to, the following:

[0095] 1. The video data stream is a sequence of complete image frames or windows;

[0096] 2. A unique frame identification is attached to each frame;

[0097] 3. Frames are totally independent of each other and are fully unique and complete images;

[0098] 4. Frames need not be contiguous or continuous;

[0099] 5. Frames are refreshed to the monitor independent of the how often they are rewritten to the frame grabber;

[0100] 6. The frame grabber is an independent and complete frame reception node;

[0101] 7. The system is scaleable from 2 to N nodes; and

[0102] 8. The image (window) that contains the human interaction devices (typically the visually critical items such as the mouse) are rewritten more often to reduce the apparent ‘jerkiness’ of their perceived movement.

[0103] Further modifications and alternative embodiments of various aspects of the invention will be apparent to those skilled in the art in view of this description. Accordingly, this description is to be construed as illustrative only and is for the purpose of teaching those skilled in the art the general manner of carrying out the invention. It is to be understood that the forms of the invention shown and described herein are to be taken as the presently preferred embodiments. Elements and materials may be substituted for those illustrated and described herein, parts and processes may be reversed, and certain features of the invention may be utilized independently, all as would be apparent to one skilled in the art after having the benefit of this description of the invention. Changes may be made in the elements described herein without departing from the spirit and scope of the invention as described in the following claims.