DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0054] The operation of this invention and other benefits will be made clear by the embodiments explained below. The embodiments of this invention will be explained below with reference to the drawings.

[0055] (Transistor Circuit)

[0056] First, the embodiment of a transistor circuit of this invention is explained with reference to FIG. 1 and FIGS. 2 (A)- 2 (B). FIG. 1 is a circuit diagram of a transistor circuit in the embodiment, and FIG. 2 (A) and FIG. 2 (B) are timing charts showing the timing and voltage of various signals in the transistor circuit respectively.

[0057] In FIG. 1, a transistor circuit 100 may consist of a driving TFT 110 (P channel type), a compensating TFT 120 (P channel type), a resetting TFT 130 (N channel type) and a switching TFT 140 (N channel type). The structure of each transistor will be sequentially explained below.

[0058] First, the driving TFT 110 , as an example of driving transistors, is constructed so as to control conductance between a source 112 and a drain 113 in response to a gate voltage Vg applied to a gate 111 based on input signals supplied through the switching TFT 140 and the compensating TFT 120 .

[0059] The compensating TFT 120 , as an example of compensating transistors, has its gate 121 connected to one of a source 122 and a drain 123 (drain 123 in the case of FIG. 1 ). In other words, the compensating TFT 120 is so-called diode-connected. Moreover, the compensating transistor 120 is connected to the gate 111 in an orientation so as to supply input signals to the gate 111 through the source 122 and the drain 123 and to allow the gate 111 to move electric charge into a direction to lower conductance (the side of drain 123 in FIG. 1 ).

[0060] The resetting TFT 130 , an example of resetting devices, has one of a source 132 and a drain 133 (drain 133 in FIG. 1 ) connected to the gate 111 , and reset signals at voltage Vrsig (called reset signals Vrsig hereafter) are supplied to the gate 111 through the source 132 and the drain 133 when reset scanning signals at voltage Vrscan (called reset scanning signals Vrscan hereafter) are supplied to the gate 131 as an example of reset timing signals before the supply of input signals Vsig.

[0061] Also, the switching TFT 140 , an example of switching transistors, is connected between an input signal source and the compensating TFT 120 so as to supply input signals at voltage Vsig (called input signals Vsig hereafter) to the compensating TFT 120 through a source 142 and a drain 143 when scanning signals at voltage Vscan (called scanning signals Vscan hereafter) are supplied to the gate 141 as an example of switching timing signals.

[0062] Moreover, one terminal of a current-controlled (current-driven) element 500 such as an EL element is connected to the source 112 of the driving transistor 110 , and negative power source −Vc with a predetermined electric potential is connected to another terminal of this current-controlled element 500 . In addition, positive power source +Vc with a predetermined electric potential is connected to the drain 113 of the driving transistor 110 . Therefore, when conductance between the source 112 and the drain 113 is controlled at the driving transistor 110 , driving current Id flowing through the current-controlled element 500 is controlled (in other words, driving current Id varies in response to conductance fluctuation).

[0063] Furthermore, a storage capacitor 160 is connected to the gate 111 of the driving transistor 110 . As a result, the once applied gate voltage Vg is held by the storage capacitor 160 .

[0064] Then, the operation of the transistor circuit 100 constructed as above is explained with reference to FIG. 1 along with FIGS. 2 (A)- 3 .

[0065] As shown in FIG. 2 (A) (this figure shows that a P channel type TFT is applied to both the driving TFT 110 and the compensating TFT 120 ), the resetting TFT 130 will be in conductance when reset scanning signals Vrscan are input to the resetting TFT 130 ; and resetting signals Vrsig are then supplied to the gate 111 of the driving TFT 110 , so that the gate voltage Vg of the gate 111 becomes almost the same as the voltage Vrsig of these reset signals Vrsig. As a result, without being dependent on the level of voltage of input signals Vsig, the gate voltage Vg of the driving TFT 110 can be reset at a fixed voltage (in other words, voltage Vrsig) by the supply timing of reset scanning signals Vrsig.

[0066] Then, as scanning signals Vscan are supplied to the switching TFT 140 after this resetting period, the switching TFT 140 will be in conductance and the driving signals Vsig are supplied to the gate 111 of the driving TFT 110 through the compensating TFT 120 . In this embodiment, the gate 121 is connected (in other words, diode-connected) to the drain 123 particularly in the compensating TFT 120 herein, so that gate voltage Vg in the driving TFT 110 , the P channel type TFT that will be in conductance by the application of negative voltage to the gate 111 , is made lower than the voltage Vsig of data signals Vsig to the negative voltage side only by a threshold voltage Vth2 level of the compensating TFT 120 . Then, the gate voltage Vg lowered as mentioned above will be held in a driving period by the storage capacitor 160 even after the supply of scanning signals Vscan and input signals Vsig is stopped.

[0067] In addition, the period in which gate voltage Vg becomes the voltage Vrsig of reset signals Vrsig is sufficient for the resetting period. Thus, the driving period can be set much longer than the resetting period, so that even if the driving TFT 110 is in conductance by resetting signals Vrsig in the resetting period, the effect on the driving current Id flowing through the source 112 and the drain 113 of the driving TFT 110 in this period can be minimized to a negligible degree.

[0068] As described above, according to this embodiment, gate voltage Vg relative to input signals Vsig can rise only by a threshold voltage Vth 2 level of the compensating TFT 120 , so that it becomes possible to carry out the same conductance control in the driving TFT 110 by using a lower input signal voltage Vsig compared with the case with no compensating TFT 120 .

[0069] Also, FIG. 2 (B) is a timing chart where an N channel type TFT is applied to both the driving TFT 110 and the compensating TFT 120 . In this case, the gate voltage Vg at the driving TFT 110 , the N channel type TFT that will be in conductance by the application of positive voltage to the gate 111 , is made higher than the voltage Vsig of input signals Vsig to the positive voltage side only by a threshold Vth 2 level of the compensating TFT 120 after being set at the voltage Vrsig of reset signals Vrsig during resetting.

[0070] If input signals Vsig are directly input to the driving TFT 110 without going through the compensating TFT 120 , in other words, when the voltage Vsig of input signals Vsig is the same as the gate voltage Vg, the driving current Id is boosted from a threshold voltage Vth 1 of the driving TFT 110 as shown in FIG. 3 (A) (in this case, the driving TFT 110 is an N channel TFT). For example, if the design standard value of this threshold voltage Vth 1 is 2V, a variance in thresholds will be about several ±V. Then, a variance in threshold voltage Vth 1 in the driving TFT 110 will appear directly as a variance in driving current Id.

[0071] On the contrary, in this embodiment, since input signals Vsig are input to the driving TFT 110 through the compensating TFT 120 , in other words, when the voltage Vsig of input signals Vsig is boosted only by the threshold voltage Vth 2 level of the compensating TFT 120 to become gate voltage Vg, the threshold voltage Vth 2 of the compensating TFT 120 and the threshold voltage Vth 1 of the driving TFT 110 are offset as shown in FIG. 3 (B) (in this case, both the driving TFT 110 and the compensating TFT 120 are N channels TFTS) and the threshold voltage Vth of the input signals Vsig to the entire transistor circuit 100 then becomes approximately zero. Moreover, particularly when both threshold voltages Vth 1 and Vth 2 are nearly the same, this threshold voltage Vth becomes approximately zero. Thus, equalizing threshold voltage Vth 1 to Vth 2 can be relatively easily carried out e.g., by applying the same conductive type TFT to the driving TFT 110 and the compensating TFT 120 in an adjoining position on the same semiconductor substrate.

[0072] As constructed above, in both TFTs, the thickness of thin gate insulating films, semiconductor films, and the like, the planar shapes of each component such as a channel length, impurity concentration in regions for forming channels, source regions and drain regions, temperature during operation and the like can easily become the same, so that the threshold voltage Vth 1 and Vth 2 of both TFTs can be completely or almost completely equalized. In addition, in making threshold characteristics similar, it is better to make channel lengths the same, but channel widths do not have to be the same.

[0073] Thus, according to this embodiment, by setting the threshold characteristics and voltage/current characteristics of the driving TFT 110 and the compensating TFT 120 close to each other (ideally the same), it is possible to set the threshold voltage Vth of input signals Vsig supplied to the driving current Id to approximately zero (ideally equal to zero).

[0074] Moreover, as seen from FIG. 3 (A) and FIG. 3 (B), in manufacturing a plurality of transistor circuits 100 , even if threshold voltage Vth 1 at each driving TFT 110 varies from each other, the threshold voltage Vth of each transistor circuit 100 is approximately zero by the operation of each compensating TFT 120 without being dependent on the level of this threshold voltage Vth 1 . In other words, a plurality of transistor circuits 100 with a constant threshold voltage Vth can be manufactured. This is particularly useful for a display panel and the like where a variance in threshold voltage Vth among a plurality of transistor circuits 100 is a problem as described below. Also, it is much easier to equalize the threshold voltage Vth 1 of the driving TFT 110 and the threshold voltage Vth 2 of the compensating TFT 120 that are a mutually adjoining pair at each transistor circuit 100 than to equalize the threshold voltage Vth 1 of two driving TFTs 110 that are separately arranged with a gap therebetween, so that it is possible to say that the structure of compensating threshold voltage Vth 1 in each transistor circuit 100 by the compensating TFT 120 is extremely effective, so as to reduce a variance in threshold voltage Vth among a plurality of transistor circuits 100 from each other.

[0075] As described above, according to this embodiment, even if a plurality of driving TFTs 110 with different threshold voltage Vth 1 from a threshold voltage (for example, 2.5V) as a design standard level is used in preparing a plurality of transistor circuits 100 , it becomes possible to provide a plurality of circuits 100 with little or no variance in threshold voltage Vth. Therefore, the requirements for TFTs regarding voltage/current characteristics are made easy, and it becomes possible to improve yields and lower manufacturing costs.

[0076] In addition, as seen from FIG. 3 (A) and FIG. 3 (B), by equalizing threshold voltages Vth 1 and Vth 2 , the first effect where conductance control at each driving TFT 110 can be carried out by using a higher gate voltage Vg than the voltage Vsig of input signals Vsig and the second effect where a variance in threshold voltage Vth among a plurality of transistor circuits 100 are clearly achieved. However, even without completely equalizing the threshold voltage Vth 1 of the driving TFT 110 and the threshold voltage Vth 2 of the compensating TFT 120 in each transistor circuit 100 , both threshold voltages characteristically will offset each other, so that these first and second effects are achieved to some degree, based on the similarity of both threshold voltages.

[0077] In this embodiment, particularly, it is constructed so as to supply reset signals Vrsig having a voltage in response to a higher conductance than the maximum conductance controlled in response to input signals Vsig to the gate 111 . Therefore, it becomes possible to supply input signals Vsig to the gate 111 through the compensating TFT 120 that is connected to the gate 111 in an orientation, to permit electric charge to move into a direction so as to lower this conductance after resetting, without being dependent on the level of voltage Vsig of input signals Vsig. Also, in this embodiment, reset signals Vrsig are set at a higher voltage than the maximum voltage of input signals Vsig by the threshold voltage Vth 2 level of the compensating TFT 120 . Therefore, when input signals Vsig are input after resetting, a voltage higher than the voltage Vsig of input signals Vsig only by the threshold voltage Vth 2 level of the compensating TFT 120 can always be supplied to the gate 111 without being dependent on the level of the voltage Vsig of input signals Vsig and the threshold voltage Vth 2 of the compensating TFT 120 .

[0078] Moreover, when the inversion of input signals Vsig is carried out as frequently applied in conventional liquid crystal display elements, it is desirable that the above-noted reset signal Vsig relations are achieved in all input signals Vsig, including inverse input signals.

[0079] The effects of these reset signals Vrsig by voltage setting are examined with reference to FIGS. 4 - 5 (B). Herein, FIG. 4 respectively shows the fluctuation in driving current relative to a variance ΔVth in threshold voltage from a design standard level that is, for instance, −2.5V (1) when input signals Vsig are supplied directly to the driving TFT 110 without the compensating TFT 120 (characteristic curve C 1 ), (2) when input signals Vsig are supplied to the driving TFT 110 through the compensating TFT 120 at 5V of reset signal Vrsig (characteristic curve C 2 ), and (3) when input signals Vsig are supplied to the driving TFT 110 through the compensating TFT 120 with reset signal Vrsig at 0V (characteristic curve C 3 ). Also, FIG. 5 (A) shows the fluctuation range of the gate voltage Vg corresponding to the characteristic curve C 2 , and FIG. 5 (B) shows the fluctuation range of the gate voltage Vg corresponding to the characteristic curve C 3 . In addition, herein, Vsig is 7.5V; +Vc is 10V; and −Vc is 5V.

[0080] In FIG. 4 , as indicated with the characteristic curve C 1 , the variance ΔVth in threshold voltage clearly appears directly as the variance in driving current Id in the case of having no compensating TFT 120 .

[0081] As illustrated with the characteristic curve C 2 , when the compensating TFT is used at 5V of reset signal Vrsig, the variance ΔVth in threshold voltage is significantly compensated on the plus side, but appears as the variance in driving current Id at the minus side. This is because, as shown in FIG. 5 (A), on the minus side, the gate voltage Vg cannot be made lower (or compensated) than the input signals Vsig by the threshold voltage Vth 2 level to the negative voltage side, when the input signals Vsig are input after resetting. This is because the compensating TFT 120 acting as a diode can make the gate voltage Vg closer to the input signals Vsig from the reset signals Vrsig, but cannot do the opposite.

[0082] Also, as shown with the characteristic curve C 3 , when the compensating TFT is used with 0V of reset signal Vrsig, the variance ΔVth of threshold voltage hardly appears as the variance in driving current Id. This is because, as shown in FIG. 5 (B), the gate voltage Vg can be made lower (or compensated) than the input signals Vsig only by threshold voltage Vth level to the negative voltage side, when the input signals Vsig are input after resetting. Moreover, if Vsig=7.5V applied herein is considered as the minimum electric potential of input signals Vsig, the above-noted examination is realized to make sure that all Vsig can be compensated.

[0083] As described above, in this embodiment, without being dependent on the level of input voltage Vsig and threshold Vth 2 of the compensating TFT 110 , a voltage Vg that is lower than the voltage of the input signals Vsig only by the threshold voltage Vth 2 level of the compensating TFT 120 can be applied to the gate 111 of the driving TFT 110 .

[0084] In addition, in FIG. 2 (A) and FIG. 2 (B), the gate voltage Vg is held by the storage capacitor capacity 160 during the driving period. Therefore, by the storage capacitor 160 , a variance in holding characteristics of the gate voltage Vg among a plurality of transistor circuits 100 can be also reduced (compensated).

[0085] As explained with reference to FIG. 1 to FIG. 5 B, according to the transistor circuit 100 of this embodiment, the current-controlled element 500 such as an EL element can be current-driven by input signals Vsig at a relatively low voltage; and moreover, without being dependent on a variance in voltage/current characteristics and threshold characteristics among a plurality of driving TFTs 110 , a plurality of current-controlled elements 500 can be current-controlled with good precision in accordance with the voltage of input signals Vsig.

[0086] Moreover, the example shown in FIG. 1 is constructed with the mixture of a P channel type TFT and an N channel type TFT, however, every TFT can be N channel type TFTs or all TFTs can be P channel type TFTs. However, in consideration that the voltage/current characteristics and threshold characteristics of the driving TFTs 110 are compensated by the compensating TFT 120 , it is advantageous to construct these driving TFTs 110 and compensating TFTs 120 by the same process as the same type TFTs. Particularly, if both TFTs are formed in the same film forming process, the degree of characteristic similarities between both TFTs generally increases, so that it becomes possible to provide the transistor circuit 100 on the same substrate with little or no variance in voltage/current characteristics and threshold characteristics. On the other hand, the resetting TFT 130 and the switching TFT 140 can be either a P channel type TFT or an N channel type TFT without being dependent on whether the driving TFT 110 is a P channel type TFT or N channel type TFT. However, it is often advantageous in manufacturing when all TFTs are of the same type.

[0087] Also, each type of TFTs 110 - 140 in this embodiment may be any type of field effect transistor (FET) such as joining type, parallel/serial connection type, and the like.

[0088] Furthermore, as shown in FIG. 6 , the above-noted transistor circuit may consist of bipolar transistors. In this case, by corresponding the above-mentioned gate, source and drain to a base, an emitter and a collector respectively, a driving transistor 110 ′ is constructed from a bipolar transistor, and at the same time, a compensating transistor 120 ′ is constructed from a bipolar transistor, thus providing a transistor circuit 100 ′. Generally, in the case of bipolar transistors, the variance in threshold voltage with e.g., 0.7V as a center is smaller than that of TFTs, however, even if constructed as above, the effect of variance in voltage/current characteristics and threshold characteristics in the driving transistor 110 ′ on the driving current Id can be compensated by the compensating transistor 120 ′. Furthermore, driving can be carried out by the driving transistor 110 ′ at a relatively low voltage. Particularly, when the driving transistor 110 ′ and the compensating transistor 120 ′ are manufactured in the same manufacturing process, the degree of characteristic similarities between both transistors generally increases, so that it becomes possible to provide a plurality of transistor circuits 100 ′ with little or reduced variance in voltage/current characteristics and threshold characteristics.

[0089] As the current-controlled element 500 in the embodiment mentioned above, various elements including current-controlled light-emitting elements such as an organic EL element and an inorganic EL element, a current-controlled heat transfer element, and the like, are included.

[0090] (Display Panel)

[0091] The embodiments of a display panel of this invention is explained with reference to FIG. 7 to FIG. 10 . FIG. 7 is a block diagram showing the entire structure of a display panel; FIG. 8 is a planar view of one picture element in the display panel; FIG. 9 (A), FIG. 9 (B) and FIG. 9 (C) are respectively a cross-sectional view on line A-A′, a cross-sectional view on line B-B′ and a cross sectional view on line C-C′ thereof; and FIG. 10 is a circuit diagram of four picture elements adjoining each other.

[0092] The display panel in this embodiment includes the above-noted transistor circuits of this invention, respectively, and a plurality of picture elements arranged in a matrix; and at the plurality of picture elements, EL elements 50 are arranged respectively as an example of current-controlled light-emitting elements.

[0093] As shown in FIG. 7, a display panel 200 has a TFT array substrate 1 , a plurality of data lines 11 extending in the Y direction and arranged in the X direction in a picture display area wherein a plurality of picture elements 2 are arranged in a matrix on the TFT array substrate, a plurality of scanning lines 12 extending respectively in the X direction and arranged in the Y direction, and a plurality of common electric wires 13 arranged in parallel to the plurality of data lines 11 . The display panel 1 further has a data line driving circuit 21 around the picture display area for supplying data signals to each data line 11 , a pair of scanning line driving circuits 22 for supplying scanning signals to each scanning line 12 , and an inspecting circuit 23 for inspecting conductance failure, insulation failure, defects of elements, and the like in each picture element 2 . In addition, in this embodiment, each driving circuit is formed on the TFT array substrate 1 along with a picture element 2 in the same process, but it can be a circuit that is not formed on the TFT array substrate 1 or may be formed in a different process from the picture element 2 .

[0094] As shown in FIG. 8 , at each picture element 2 , the driving TFT 110 , the compensating TFT 120 , the resetting TFT 130 , the switching TFT 140 and the storage capacitor 160 that are explained above with reference to FIG. 1 to FIG. 6 are arranged. Moreover, a scanning line 12 b in a previous stage becomes the wiring for reset scanning signals Vrscan in FIG. 1 ; a scanning line 12 a in this stage becomes the wiring for scanning signals Vscan and for reset signals Vrsig in FIG. 1 ; and a data line 11 a in this stage becomes the wiring for input signals Vsig (data signals) in FIG. 1 . Furthermore, the common electric wire 13 is connected to a positive power source +V; an EL element 50 is connected between the driving TFT 110 and a counter electrode to be mentioned later; and the counter electrode is connected to a negative power supply −V.

[0095] As shown in FIG. 9 (A), the switching TFT 140 , the compensating TFT 120 and the storage capacitor 160 , along an A-A′ cross section in FIG. 8 , consist of a semiconductor film (polysilicon film) 4 on the TFT array substrate 1 , a gate insulating film 5 consisting of a silicon oxide film or a silicon nitride film, a Ta (tantalum) film 6 , a first interlayer insulating film 7 consisting of a silicon oxide film or a silicon nitride film, and an Al film 8 . In addition, instead of the Ta film for forming gate electrodes, a low-resistance polysilicon film may be formed.

[0096] More specifically, the switching TFT 140 is a top gate type TFT having a gate 141 made of the polysilicon film 6 , and is formed as an N channel type TFT having a semiconductor layer 4 countering the gate 141 through the gate insulating film 5 as a channel forming area and having a source 142 and a drain 143 that are doped at high concentration in the n type on both sides of the area. Also, the source 142 is connected to a data line 11 a made of an Al film 8 through contact holes formed in the gate insulating film 5 and the first interlayer insulating film 7 . Moreover, the drain 143 is connected to the compensating TFT 120 through contact holes formed in the gate insulating film 5 and the first interlayer insulating film 7 as well as the Al film 8 .

[0097] The compensating TFT 120 is a top gate type TFT having a gate 121 made of a Ta film 6 , and is formed as a P channel type TFT having a semiconductor film 4 countering the gate 121 through the gate insulating film 5 as a channel forming area and having a source 122 and a drain 123 that are doped at high concentration in the p type on both sides of the area. Also, the TFT is connected to the switching TFT 140 , the storage capacitor 160 and the gate 111 of the driving TFT 110 through the contact holes formed in the gate insulating film 5 and the first interlayer insulating film 7 and the Al film 8 .

[0098] In addition, the storage capacitor 160 , so as to have a double capacitor structure, is formed in that the semiconductor film 4 , the Ta film 6 and the Al film 8 are counter-arranged with the gate insulating film 5 and the first interlayer insulating film 7 respectively therebetween. Also, the semiconductor film 4 constituting a storage capacitor is connected to the Al film 8 through the contact holes formed in the gate insulating film 5 and the first interlayer insulating film 7 ; and the Ta film 6 constituting a storage capacitor is connected to the Al film 8 through the contact holes formed in the first interlayer insulating film 7 .

[0099] As shown in FIG. 9 (B), the resetting TFT 130 , along a B-B′ cross section in FIG. 8 , consists of a semiconductor film 4 , a gate insulating film 5 , a Ta film 6 , a first interlayer insulating film 7 and an Al film 8 on a TFT array substrate 1 .

[0100] More specifically, the resetting TFT 130 is a top gate type TFT having a gate 131 made of a Ta film 6 , and is formed as an N channel type TFT having a semiconductor layer 4 facing the gate 131 through the gate insulating film 5 as a channel forming area and having a source 132 and a drain 133 that are doped at high concentration in the n type on both sides of the area. Also, the source 132 and the drain 133 are connected respectively to a scanning line 12 a in this stage made of a Ta film 6 and the gate 111 of the driving TFT 110 through the contact holes formed in the gate insulating film 5 , the first interlayer insulating film 7 and the Al film 8 .

[0101] Moreover, as shown in FIG. 9 (C), the driving TFT 110 , along a C-C′ cross section in FIG. 8 , consists of a semiconductor film 4 , a gate insulating film 5 , a Ta film 6 , a first interlayer insulating film 7 and an Al film 8 on a TFT array substrate 1 . Also, on a second interlayer insulating film 9 , an ITO film 51 is formed that is connected to the drain 113 of the driving TFT 110 through contact holes and the Al film 8 , and an EL element 50 is formed thereon. On the other hand, the source 112 of the driving TFT 110 is connected to a common electric wire 13 made of the Al film 8 through contact holes. Also, EL elements 50 at adjoining picture elements 2 are separated from each other by electrically insulating banks 52 . Preferably, the banks have a shielding property. The banks 52 are made of, for instance, a shielding resist, and the bank 52 may be provided even at a peripheral parting area surrounding the picture display area of the display panel 200 . In addition, on the EL element 50 , a counter electrode (top electrode) 56 is arranged that is made of a low-resistance metal such as Al or ITO, and the like.

[0102] As shown in FIG. 10 , the display panel 200 particularly has a structure wherein positive power source +V is supplied to both picture elements 2 which are mutually adjoining in the X direction by the common electric wire 13 ; and compared with the case wherein power source wiring for supplying positive power source +V is simply provided for each of picture elements 2 , the number of power source wiring is about ½. Moreover, having a structure wherein reset scanning signals Vrscan input to the gate 131 of the resetting TFT 130 are supplied by a scanning line 12 b in the previous stage and reset signals Vrsig input to the resetting TFT 130 are supplied by a scanning line 12 b in the current stage, the number of signal wiring is reduced compared with the case wherein wiring only for reset scanning signals Vrscan and wiring only for reset signals Vrsig are provided. Therefore, without increasing the number of power source wiring and signal wiring, a space for the compensating TFT 120 and the resetting TFT 130 that is not provided in conventional display panels can be kept. There is no doubt that the ideas of this invention are applicable to the ones, different from this embodiment, wherein patterns are made the same for each picture element by providing a common electric wire per picture element or wherein wiring only for reset scanning signals Vrscan and wiring only for reset signals Vrsig are provided.

[0103] In addition, in the case of the display panel 200 wherein the EL elements 50 are used as current-driven light-emitting elements as in this embodiment, unlike liquid crystal panels, and the like, the panel emits its own light in response to the increase in electric current supplied to the light-emitting elements without increasing the entire area of picture elements, so that brightness necessary for picture image display can be obtained. Thus, as in this embodiment, it is possible to maintain a space for forming various TFTs in a picture element 2 by saving a wiring area, or a space for forming various TFTs in a picture element 2 may be kept by reducing the size of each EL element 50 .

[0104] Next, the operation of the display panel 200 of this embodiment is explained with reference to FIG. 7 and FIG. 10 .

[0105] When scanning signals Vscan are supplied to a scanning line 12 b in a previous stage from a scanning line driving circuit 22 , they are input to the gate 131 of the resetting TFT 130 in the current stage as reset scanning signals Vrscan in the current stage. At the same time, reset signals Vrsig are supplied from the scanning line driving circuit 22 to a scanning line 12 a in the current stage, and the gate voltage Vg of the driving TFT 110 in the current stage becomes the electric potential of reset signals Vrsig (see FIG. 2 (A)). At this time, the reset signals Vrsig may be the same as the OFF-state electric potential of scanning signals Vscan. When the scanning signals Vscan are continuously supplied from the scanning line driving circuit 22 to the scanning line 12 a in the current stage, they are then input to the gate 141 of the switching TFT 140 in the current stage. At the same time, input signals Vsig (data signals) are supplied from a data line driving circuit 21 to a data line 11 a in the current stage, and this voltage Vsig is dropped only by a threshold voltage Vth 2 of the compensating TFT 120 through the switching TFT 140 and the compensating TFT 120 , and is then supplied as a gate voltage Vg to the gate 111 of the driving TFT 110 in the current stage (see FIG. 2 (A)). As a result, in response to this dropped gate voltage Vg, conductance between the source 112 and the drain 113 of the driving TFT 110 is controlled between positive power source +V and negative power source −V.

[0106] The driving current Id flowing to the EL element 50 is then controlled. Therefore, a variance in threshold voltage Vth 1 of the driving TFT 110 at each picture element 2 is compensated by a threshold Vth 2 of the compensating TFT 120 , and the variance in thresholds of data signals Vsig in response to the driving current Id among a plurality of picture elements 2 is almost gone, so that even picture images are displayed with even brightness over the entire picture display area of the display panel 200 . It is also possible to control the driving current Id with data signals Vsig having a relatively small voltage due to the dropping voltage operation of the compensating TFT 120 .

[0107] In the above-noted embodiment, the gate voltage Vg is reset by the resetting TFT 130 before input signals Vsig are supplied, however, for instance, in the display period of a static picture, the control of driving current Id can be carried out over a plurality of frames by the same input signals Vsig, so that it is unnecessary to carry out resetting operations for each scanning. Also, instead of these electrically reset signals Vrsig, the gate voltage Vg may be reset (to be a predetermined reset voltage) by light irradiation. Furthermore, instead of the resetting TFT 130 , reset signals Vrsig may be supplied through the switching TFT 140 and the compensating TFT 120 . On the other hand, of course, the switching TFT 140 and switching operations will be unnecessary if switching such as active matrix driving is not carried out.

[0108] (Electronic Apparatus)

[0109] Next, the electronic apparatus of the embodiment having the display panel 200 which was explained above in detail will be explained with reference to FIG. 11 to FIG. 13 .

[0110] First, FIG. 11 shows the schematic structure of an electronic apparatus having the display panel 200 as mentioned above.

[0111] In FIG. 11 , the electronic device includes a display information output source 1000 , a display information processing circuit 1002 , a driving circuit 1004 , a display panel 1006 , a clock generating circuit 1008 and a power source circuit 1010 .

[0112] The display panel 200 in the above-noted embodiment is equivalent to the display panel 1006 and the driving circuit 1004 in this embodiment. Therefore, the driving circuit 1004 may be installed on a TFT array substrate of the display panel 1006 , and moreover, the display information processing circuit 1002 , and the like may be installed. Alternatively, the driving circuit 1004 may be fixed externally onto a TFT array substrate on which the display panel 1006 is installed.

[0113] The display information output source 1000 includes a memory such as ROM (Read Only Memory), RAM (Random Access Memory) and an optical disk device, a tuning circuit for tuning television signals and then outputting the signals, and the like; and based on clock signals from the clock generating circuit 1008 , display information such as the picture image signals of a predetermined format is output to the display information processing circuit 1002 . The display information processing circuit 1002 includes various conventional processing circuits such as an amplifying/inversion circuit, a phase developing circuit, a rotation circuit, a gamma control circuit and a clamp circuit; and digital signals are sequentially formed from display information that is input based on clock signals and are then output to the driving circuit 1004 along with clock signals CLK. The driving circuit 1004 drives the display panel 1006 . The power source circuit 1010 supplies a predetermined power source to each circuit mentioned above.

[0114] Next, the specific examples of the electronic apparatus prepared as above are shown respectively in FIG. 12 and FIG. 13 .

[0115] In FIG. 12 , as another example of the electronic apparatus, a multimedia laptop personal computer (PC) 1200 has the above-noted display panel 200 in a top cover case 1206 , and further includes a main body 1204 having a CPU, a memory, a modem, and the like and a built-in keyboard 1202 .

[0116] Also, as shown in FIG. 13 , in the case of a display panel 1304 with no built-in driving circuit 1004 and display information processing circuit 1002 , an IC1324 containing the driving circuit 1004 and the display information processing circuit 1002 is physically and electrically connected to a TCP (Tape Carrier Package) 1320 through an anisotropic conductive film 1322 arranged at the periphery of the TFT array substrate 1 , and can be manufactured, sold, used, etc. as a display panel.

[0117] As explained above, according to this embodiment, various electronic apparatuses are provided that can be driven at a relatively low voltage and with little unevenness in brightness over the entire surface of a display panel.

[0118] According to the transistor circuits of this invention, the gate voltage can be reduced or increased relative to the voltage of input signals only by a threshold voltage of a compensating transistor, so that conductance control in the driving transistor can be carried out by a dropped voltage of input signals. Moreover, by making the threshold characteristics and voltage/current characteristics of a compensating transistor and a driving transistor similar, the threshold voltage of input signals to driving current can become approximately zero. Furthermore, in the case a plurality of the transistor circuits is prepared by applying a plurality of driving transistors with different threshold characteristics, even if a plurality of driving transistors with many different threshold voltages are applied, in other words, a plurality of driving transistors having various threshold voltages relative to a design standard level, it is also possible to provide a plurality of transistor circuits with almost no variance or no variance at all in threshold voltage in the plurality of transistor circuits.

[0119] According to the display panel of this invention, a picture image display with reduced unevenness in brightness is achieved by applying low voltage input signals.

INDUSTRIAL APPLICABILITY

[0120] A display panel is provided that can display picture images with reduced unevenness in brightness, from the transistor circuits of this invention; and the display panel is useful for electronic devices such as laptop personal computers (PC), televisions, view finder or monitor display-type video tape recorders, car navigation devices, electronic notebooks, calculators, word processors, engineering workstations (EWS), cellular phones, TV telephones, POS terminals, pagers, devices with touch panels, and the like.