DETAILED DESCRIPTION

[0026] Referring now to FIG. 1, a highly simplified block diagram of a typical integrated circuit memory 10 such as a DRAM chip or an embedded memory includes two mirror-image memory array portions 12 and 16 , and associated row control circuitry 14 including an instruction decoder 22 with /RAS, /CAS, /WE, and /CS inputs, a row control logic block 24 including an RA (row address) input, which is in turn coupled to a row predecoder 26 . The outputs of the instruction decoder 22 and row predecoder 26 are coupled to array portions 12 and 16 . The row predecoder 26 “pre-decodes” the externally applied address, which are in turn completely decoded by row decoders 20 . Each memory array portion 12 and 16 includes a number of memory arrays 18 (four are shown in FIG. 1 , but any number can be used as desired), and associated shared sense-amplifier blocks 28 , and end sense-amplifier blocks 30 . The memory 10 of FIG. 1 is only shown as a simplified typical example of an integrated circuit memory and therefore many typical functional blocks are not shown. Additionally, the architecture and layout of the memory can be changed if desired and still use the row address buffer circuit of the present invention, which is described in further detail below.

[0027] Referring now to FIG. 2 a block diagram shows further detail of the row control circuitry of the integrated circuit memory 10 of FIG. 1 . A Pad Buffer & Clock Driver block 32 receives the CLKPD (clock pad) signal and generates a MCLK (master clock) signal. A Pad Buffer & Half Cycle Latch block 34 receives the MCLK signal and the RAPD (row address pad inputs) signal and generates an RAIN (row address input) signal. A Refresh Address Counter block 36 receives the MCLK signal, as well as the REFB (complementary refresh command) and PREB (complementary precharge command) signals, and an output for generating a REFADR (refresh address) signal. A Pad Buffer & Half Cycle Latch block 38 receives the MCLK signal and a CONTROL signal including the /RAS, /CAS, /WE, and /CS signals and generates the RAS, CAS, WE, and CS signals. The instruction decoder 22 receives the RAS, CAS, WE, and CS signals and the MCLK signal, and generates the REFB, PREB, ACTB (complementary active command), and WRITEB (complementary write command), READB (complementary read command) control signals. The ROW ADDRESS MUX & LATCH block 40 receives the MCLK, RAIN, REFADR, ACTB, and REFB signals and generates the LRA (latched row address) signal. Often, the address multixplexer includes a burst counter for sequential burst accesses. The burst counter is not shown in FIG. 2 in order to simplify the diagram.

[0028] Referring generally to FIGS. 3 - 5 three circuit diagrams of known row address multiplexer circuits are shown that form a portion of the row control circuitry of the integrated circuit memory 10 of FIG. 1 .

[0029] FIG. 3 illustrates a common circuit and method for selecting the source to be used for a row address within a DRAM memory. The refresh counter 36 is selected when a REFRESH command has been executed and the external address is selected when an ACTIVE command has been executed. Prior art allowed either a REFRESH command or an ACTIVE command to occur on the same clock cycle. When this is done, the on-chip control logic block 42 must determine what type of a command was issued. If the command was an ACTIVE command, the control logic 42 activates a signal, shown in FIG. 3 as “/ACTIVE”, which selects the external address path as the input signal for the Row Address Latch block 44 . If the command was a REFRESH command, the control logic activates a signal, shown in FIG. 3 as “/REFRESH”, which selects the on-chip Refresh Counter 36 as the input signal for the Row Address Latch 44 . It takes time for the Control Logic 42 to determine which type of command has been issued which delays the selection of the input source for the Row Address Latch 44 . In the past, this has not been a major performance inhibitor. However, as the performance demands increase, this delay becomes more significant and it becomes necessary to find a selection method that does not slow the row address path for either an active command or for a refresh command.

[0030] The row address latch 44 includes a first switch including coupled transistors M 6 and M 8 , and inverter U 4 . The gates of transistors M 6 and M 8 are controlled by the CLK and /ACTIVE signals, gated through logic gate U 2 . The signal input to the switch is provided by the ADDRESS INPUT through the pad buffer U 1 . A second switch includes coupled transistors M 7 and M 9 , and inverter U 5 . The gates of transistors M 6 and M 8 are controlled by the CLK and /REFRESH signals, gated through logic gate U 3 . The signal input to the switch is provided by the output of the refresh counter 36 . The output of the two switches are latched by the latch circuit including coupled inverters U 10 and U 11 . The output of the latch is coupled to the row address circuitry.

[0031] If the control logic 42 takes a long time to select the correct cycle operation (ACTIVE or REFRESH) relative to the setup and hold time of the ADDRESS INPUT signal, then it may be necessary to add an Address Pre-Latch 46 , as shown in FIG. 4 . Pre-Latch 46 includes a clocked switch including coupled transistors M 12 and M 13 , and inverter U 14 for receiving a CLK signal. The latch portion includes cross-coupled inverters U 15 and U 16 . The addition of the Pre-Latch 46 is likely to further undesirably impact performance. With the additional Pre-Latch 46 , the combination of the Pre-Latch 46 and the Row Address Latch 44 becomes a full-cycle latch. This prevents the Row Addresses to “ripple-through” further in the Row Address path.

[0032] Referring now to FIG. 5, a more detailed version of the row address buffer and latch circuit is shown, including a latch circuit including P-channel transistors M 3 and M 4 , N-channel transistors M 5 and M 6 , and inverters U 12 and U 3 for generating a latched row address signal LRA and a complementary latched row address signal LRAB.

[0033] Referring now to FIG. 6, a simplified schematic diagram showing the essentially functionality of the row address buffer circuits shown in FIGS. 3 - 5 . In a first signal path, an input signal latch 48 provides a signal to the transmission gate 56 which is controlled by the RAEN row enable signal at node 52 . In a second signal path, a refresh counter 50 provides a signal to the transmission gate 58 which is separately and independently controlled by the REFEN refresh enable signal at node 54 . The outputs of transmission gates 56 and 58 are coupled together and latched by the cross-coupled inverters 60 and 62 . The latch output is then delivered to additional row control circuitry, specifically the row predecoders.

[0034] Referring now to FIG. 7 a simplified timing diagram associated with the active and refresh operation of the row address buffer circuits of FIGS. 3 - 5 is shown. The enabling of the row selection circuitry must be delayed until the source (external address) can be determined. The READ and WRITE commands are omitted in FIG. 7 to simplify the diagram. The PRECHARGE command precharges the selected row and bank in the memory array. Similarly, enabling of the row selection circuitry must be again delayed until the source (internal address from the refresh counter) can be determined.

[0035] Referring now to FIG. 8, a timing diagram of a refresh cycle for the row address buffer circuits of FIGS. 3 - 5 is shown. The CLKPD (clock pad), CMDPD/RAPD (command pad/row address pad), REFB, REFEN, and LRA signals are shown. It should be noted that LRA(0:N) are not valid until the refresh command, REF, has been decoded. This results in the REFEN signal going active in order to selecte the refresh counter address (REFADR) path through the multiplexer in the row address latch circuit. Similarly, FIG. 9 shows a timing diagram of an active cycle for the row address buffer circuit of FIGS. 3 - 5 . The CLKPD, CMDPD/RAPD, REFB, REFEN, and LRA signals are shown. It should be noted that LRA(0:N) are not valid until the active command, ACT, has been decoded. This results in the RAEN signal going active in order to select the external address path through the multiplexer in the row address latch circuit.

[0036] Referring now to FIG. 10 a block diagram shows further detail of the row control circuitry of the integrated circuit memory 10 of FIG. 1 according to the present invention. While the overall structure of the row control circuitry is the same, the pad buffer circuit 34 ′ does not include a latch circuit portion, and the row address mux and latch circuit 40 ′ is modified according to the present invention as is described in further detail below.

[0037] Referring now to FIG. 11 a circuit diagram of the row address buffer and latch circuit is shown that form a portion of the row control circuitry of the integrated circuit memory 10 of FIG. 1 , but modified according to the present invention. The latch portion includes P-channel transistors M 3 and M 4 , N-channel transistors M 5 and M 6 , and inverters U 12 and U 3 for generating a latched row address signal LRA and a complementary latched row address signal LRAB. A first transmission gate includes transistors M 7 and M 8 , and inverter U 8 . The input of the transmission gate is coupled to the complementary RAIN (row address input) signal received via the output of inverter U 10 . The gate control nodes of transistors M 7 and M 8 are controlled by the RAEN and RAENB signals that are generated by NOR gate U 9 , which receives the master clock MCLK and refresh clock REFCLK signals. Similarly, a second transmission gate includes transistors M 9 and M 10 , and inverter U 7 . The input of the transmission gate is coupled to the complementary REFADR signal received via the output of inverter U 4 . The gate control nodes of transistors M 7 and M 8 are controlled by the REFEN and REFENB signals that are generated by inverter U 5 , which receives the refresh clock REFCLK signal.

[0038] It is important to note that in FIG. 11 , while the two transmission gates M 7 /M 8 and M 9 /M 10 are respectively controlled by the RAEN and REFEN signals, both of these signals are derived from the REFCLK signal and are not independently generated signals as in the memory architecture discussed above with reference to FIGS. 3 - 5 . The circuit described in FIG. 11 allows the externally generated addresses to ripple through to the row predecoders without the intervening delay of an additional clock cycle.

[0039] Referring now to FIG. 12, a simplified schematic diagram showing the essential functionality of the row address buffer circuit shown in FIG. 11 . In a first signal path, an input signal buffer 49 provides a signal to the transmission gate 56 . Transmission gate is controlled by the REFENB signal at node 55 , which is the REFEN signal inverted through inverter 64 . In a second signal path, the refresh counter 50 provides a signal to the transmission gate 58 which is also controlled by the REFEN refresh enable signal at node 54 . The outputs of transmission gates 56 and 58 are coupled together and latched by the cross-coupled inverters 60 and 62 . The latch output is then delivered to additional row control circuitry, specifically the row predecoders as before.

[0040] The main difference in the circuit of the present invention is that the external addresses are no longer latch in the first signal path, and the two transmission gates 56 and 58 are not separately controlled, but are both controlled with a look-ahead REFEN signal. In this way, the external addresses can be rippled through to the row predecoder if a REFENB signal is present at transmission gate 56 .

[0041] Referring now to FIG. 13 a simplified timing diagram associated with the active and refresh operation of the row address buffer circuits of FIG. 11 is shown. The row active command does not have to wait to determine the source of the row address. As before, the READ and WRITE commands have been omitted to simplify the timing diagram, and the PRECHARGE command precharges the selected row and bank in the memory array. The refresh command is delayed by one clock cycle. The refresh cycle can therefore start immediately after the clock because there is no need for waiting to determine the source of the address (internal or external).

[0042] Referring now to FIG. 14 a timing diagram of an active cycle for the row address buffer circuit of FIG. 11 is shown. The CLKPD, CMDPD, REFCLK, RAEN, RAPD, and LRA signals are shown. It should be noted in FIG. 14 that the latched row address signal LRA is immediately available after the rising edge of the RAEN signal without an additional wait to determine the source of the address.

[0043] Referring now to FIG. 15, a timing diagram of a refresh cycle for the row address buffer circuit of FIG. 11 is shown. The same memory address and control signals shown in the timing diagram of FIG. 14 are shown. It should be noted in FIG. 8 that from the start of the internal reference clock, the reference address from the internal refresh counter is available before the internal reference clock starts since a look-ahead REFEN signal is provided.

[0044] Having described and illustrated the principle of the invention in a preferred embodiment thereof, it is appreciated by those having skill in the art that the invention can be modified in arrangement and detail without departing from such principles. Although a preferred method and circuit has been shown, the exact details of the preferred method and circuit can be changed as desired as required for a particular application. For example, it is not necessary to wait for a command to occur in order to preemptively select the row address multiplexer. We therefore claim all modifications and variations coming within the spirit and scope of the following claims.