DETAILED DESCRIPTION OF THE INVENTION

[0039] The following detailed description of the invention refers to the accompanying drawings which show, by way of illustration, specific aspects and embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. In the following description, the terms wafer and substrate are interchangeably used to refer generally to any structure on which integrated circuits are formed, and also to such structures during various stages of integrated circuit fabrication. Both terms include doped and undoped semiconductors, epitaxial layers of a semiconductor on a supporting semiconductor or insulating material, combinations of such layers, as well as other such structures that are known in the art. The term “horizontal” as used in this application is defined as a plane parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term “vertical” refers to a direction perpendicular to the horizontal as defined above. Prepositions, such as “on”, “side” (as in sidewall), “higher”, “lower”, “over” and “under” are defined with respect to the conventional plane or surface being on the top surface of the wafer or substrate, regardless of the orientation of the wafer or substrate. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.

[0040] The present subject matter provides nonvolatile memory devices that incorporate a band-gap engineered gate stack with asymmetric tunnel barriers. The gate stack is designed with appropriate energy barriers, in conjunction with a predetermined control gate metallurgy, such that the memory device is capable of being programmed primarily through charge transport between the control gate and the floating charge-storage medium (i.e. floating gate or floating plate) using field emissions that are selective either to electrons or holes. The gate stack is further designed with appropriate energy barriers to retain the stored charge. The gate stack is further designed with appropriate stack geometry to further limit carrier flow from and to the substrate by providing the appropriate capacitive coupling (k<0.5). The gate stack is further designed with material selected and combined to significantly enhance field emission at a reduced field.

[0041] FIG. 1 illustrates one embodiment of a floating gate embodiment of the nonvolatile device of the present invention. The device 100 is formed on a substrate 102 . In one embodiment, the substrate 102 includes p− silicon. A first source/drain region 104 and a second source/drain region 106 are formed in the substrate 102 between isolation regions 108 . The source/drain regions 104 and 106 are separated by a channel region 110 of the substrate 102 . In one embodiment, each of the source/drain regions 104 and 106 include n− silicon positioned to define the channel region 110 in the substrate 102 , and n+ silicon used to provide a drain contact and a source contact.

[0042] An asymmetric gate stack 112 is formed over the channel region 110 of the substrate 102 . The gate stack 112 separates a control gate 114 from the substrate 102 . According to one embodiment, the control gate 114 includes aluminum, and is connected to an aluminum word line. One embodiment of the asymmetric gate stack 112 includes a first set of insulator region 116 , a conventional silicon floating gate 118 that functions as a floating charge-storage region, and a second insulator region 120 . The gate stack 112 is engineered to provide the desired asymmetric barrier energies for charge transport between the three nodes (substrate, floating charge-storage region, and control gate) of the device, and is further engineered to provide the desired electric fields between the three nodes of the device.

[0043] In one embodiment of the asymmetric gate stack, the first insulator region 116 includes a layer of Silicon Dioxide (SiO ₂ ) 122 disposed over the channel region, and a layer of Tantalum Oxide (Ta ₂ O ₅ ) 124 disposed over the layer of SiO ₂ 122 . One embodiment of the layer of SiO ₂ 122 includes approximately 2 nm of NH ₃ -treated SiO ₂ . Another embodiment of the layer of SiO ₂ 122 includes approximately 2 nm of NO-treated SiO ₂ . In one embodiment, the layer of Ta ₂ O ₅ 124 has an equivalent oxide thickness (t _ox.eq. ) of approximately 3 to 5 nm. In one embodiment, the layer of Ta ₂ O ₅ has an equivalent oxide thickness (t _ox.eq. ) of approximately 4 nm. The silicon floating gate 118 is disposed on the layer of Ta ₂ O ₅ 124 . Conventional silicon floating gates may be approximately 1,000 to 2,000 Å (100 to 200 nm) thick. The invention is not so limited, however, to any particular dimension of the silicon floating gate. A layer of Zirconium Oxide (ZrO ₂ ) 126 is disposed on the silicon floating gate. In one embodiment, the layer of ZrO ₂ 126 has an equivalent oxide thickness (t _ox.eq. ) of approximately 3-5 nm. An Oxide-Nitride-Oxide (ONO) sidewall 128 surrounds the asymmetric gate stack and isolates the device from other integrated circuit devices.

[0044] It is noted that the nonvolatile device is capable of being viewed as three nodes that define two capacitors. The three nodes include the control gate, the floating gate, and the substrate. The two capacitors include the control gate/floating gate capacitor and the floating gate/substrate capacitor. Programming potentials are capable of being applied to the control gate and the substrate to produce desired electric fields, i.e. desired electromotive force (EMF), to allow for the desired transport of charge (holes and/or electrons) between the various nodes of the device. Further, it is noted that charge (holes or electrons) is capable of being accumulated and stored on the floating gate. The charge on the floating gate provides a built-in potential that either raises or lowers the threshold voltage of the device. In an NFET device, for example, accumulated holes reduce the threshold voltage of the device so that the device is in a conducting state, and accumulated electrons increase the threshold voltage of the device so that the device is in a nonconducting state.

[0045] FIG. 2 is a band diagram illustrating one embodiment of an asymmetric band-gap gate stack incorporated in the device of FIG. 1 . The band diagram is useful for illustrating the charge transport and charge storage during device operation. The band diagram includes representations for the silicon substrate 202 , the aluminum control gate 214 , and the asymmetric gate stack 212 between the substrate and the control gate. One embodiment of the asymmetric gate stack 212 includes ˜2 nm of SiO ₂ 222 , ˜3-5 nm t _ox.eq. of Ta ₂ O ₅ 224 , a silicon floating gate 218 , and ˜3-5 nm t _ox.eq. of ZrO ₂ 226 .

[0046] The band diagram of FIG. 2 shows various energy barriers between the materials. From the viewpoint of the silicon substrate 202 , for example, electrons encounter a 3.2 ev energy barrier and holes encounter a 4.7 ev energy barrier attributable to the SiO ₂ 222 when they are transported from the silicon substrate 202 to the silicon floating gate 218 . From the viewpoint of the control gate 214 , electrons encounter a 3.8 ev energy barrier and holes encounter a 1.9 ev energy barrier attributable to the ZrO ₂ 226 when they are transported from the aluminum control gate 214 to the silicon floating gate 218 . From the view point of the floating gate 218 , electrons encounter a 1.5 ev energy barrier and holes encounter a 3.1 ev energy barrier attributable to the ZrO ₂ 226 when they are transported from the floating gate 218 to the control gate 214 . Additionally, electrons encounter a 1.0 ev energy barrier and holes encounter a 2.9 ev energy barrier attributable to the Ta ₂ O ₅ 224 as well as electrons encountering an additional 2.2 ev energy barrier and hole encountering an additional 1.8 ev attributable to the SiO ₂ when they are transported from the floating gate toward the substrate. It is noted that electrons exhibit finite probability of directly tunneling from the Ta ₂ O ₅ 224 through the SiO ₂ 222 to the substrate 202 . However, due to lower mobility, holes exhibit reduced probability to directly tunnel from the Ta ₂ O ₅ 224 through the SiO ₂ 222 to the substrate 202 compared to the electrons. In any event, the SiO ₂ 222 provides an additional barrier to charge transport off of the floating gate 218 toward the substrate 202 .

[0047] Programming voltages are capable of being applied to the silicon substrate 202 and the control gate 214 to provide sufficient field strength for achieving the desired charge transport. FIGS. 3 and 4 illustrate the charge transport that occurs when these programming voltages are applied. For simplicity, field induced band bending has not been shown. One should be mindful of the following points when viewing these diagrams. The floating gate 218 is capable of storing charge so as to provide a built-in potential between the floating gate 218 and the substrate 202 and between the floating gate 218 and the control gate 214 . This built-in potential is capable of affecting the charge transport during voltage transients that occur when the programming voltage is first applied or switched. Further, positive and negative programming voltages have a large magnitude. In an NFET device which has a p− substrate, negative programming voltages are applied to the substrate 202 so that the PN junctions of the device are reversed biased (within the tolerance of the junction), and positive programming voltages are applied to the control gate 214 . Also, it is possible to engineer the asymmetric gate stack geometry (for example capacitive area), and in particular to vary the equivalent oxide thicknesses of the first insulator region and the second insulator region, to modify the capacitive divider effects between the control gate/floating gate capacitor and the floating gate/substrate capacitor. As such, the gate stack 212 is capable of being engineered to apply the majority of the EMF that is associated with the applied programming voltage across the second insulator region disposed between the control gate 214 and the floating gate 218 rather than across the first insulator region disposed between the floating gate 218 and the substrate 202 . Higher EMFs provide higher energy to the charges so as to promote charge emission and transport.

[0048] FIG. 3 illustrates charge transport for an Erase Process, defined as a transition from a nonconducting high threshold (1) to a conducting low threshold (0), using the band diagram of FIG. 2 . Thicker arrows represent primary charge transport. During the erase process, a +12V programming voltage is applied to the control gate, and the substrate is grounded to 0 V as shown in FIG. 5 . The primary charge transport involves the emission and transport of holes, designated as 330 , from the aluminum control gate through the ZrO ₂ and to the silicon floating gate because of the low 1.9 ev hole barrier height from the aluminum control gate to the ZrO ₂ of the second insulator region and because of the comparatively higher EMF across the floating gate/control gate capacitor as compared to the silicon substrate/floating gate capacitor part of the gate stack. These holes 330 tunnel through the ZrO ₂ and are collected at the floating gate. Holes are not likely to be injected and transported from the silicon floating gate because of the high hole energy barriers associated with the charge transport from the silicon floating gate through the Ta ₂ O ₅ and the SiO ₂ to the silicon substrate. The collection of holes at the floating gate lowers the threshold voltage of the NFET device and programs the device to a conducting or “0” state. That is, the NFET device is erased. At the same time, a complimentary charge transport occurs as electrons, designated as 332 , are emitted and transported from the silicon floating gate through the ZrO ₂ to the aluminum control gate because of the low 1.5 ev electron barrier height from the silicon floating gate to the ZrO ₂ and because of the comparatively higher EMF across the floating gate/control gate capacitor as stated above. Together, hole trapping and electron detrapping at the floating gate enhance the erase process.

[0049] Two additional charge emission and transport processes are also identified in FIG. 3 . Electron emission and transport from the silicon substrate is identified as 334 while hole emission and transport from the floating gate is identified as 336 . However, such mechanisms are dramatically suppressed due to large barrier energies (3.2 ev for electrons and 4.7 ev (2.9 ev+1.8 ev) for holes), and reduced programming field (E) between silicon substrate and the floating gate (k<0.5 by design) as discussed with the carrier field emission equation previously provided in the section entitled Background of the Invention. These smaller charge transports 334 and 336 are generally represented by thinner arrows.

[0050] FIG. 4 illustrates charge transport for a Write Process defined as a transition from a conducting low threshold (0) to a nonconducting high threshold (1), using the band diagram of FIG. 2 . During the write process, a +12 V programming voltage is applied to the substrate via the drain diffusion as shown in FIG. 6 , while the control gate is grounded to 0 V. It is noted that the programming voltage is brought into the specific cell via its drain (n+) diffusion while the substrate is made to float. During such process, the channel of the specific cell gets capacitively coupled and rises to the same potential as the drain. In one embodiment, if a block of cells to be written simultaneously, the relevant substrate block and drain nodes are held together during such writing process. Prior to the writing onset, the specific cell holds a built-in positive potential at the floating gate due to the trapped holes (being in the erased conducting state). During writing, the substrate potential rises to +12 V and with coupling coefficient of the cell designed to be k<0.5, more than half of the 12 Volts is imposed between te floating gate and the control gate. This potential is further enhanced by the built-in potential of the holes in the floating gate. As a result, the field (EMF) between the floating gate and the control gate attains significantly higher value as compared to that between the substrate and the floating gate at the onset of the writing process. This high field induces hole emission and transport 436 from the floating gate to the control gate. Simultaneously, this high field also induces complementary electron injection and transport 438 from the control gate to the floating gate as shown in FIG. 4 . Mechanism 436 involves the positive charge removal from the floating gate while mechanism 438 involves positive charge neutralization and or negative charge storage into the floating gate. Both of these involves positive charge neutralization and or negative charge storage into the floating gate. Both of these mechanisms are expected to dominate during the writing process resulting in net negative charge storage in the floating gate and transition of the cell to the non-conducting high threshold state. Some loss of electrons from the silicon floating gate to the silicon substrate defined as mechanism 440 is feasible at the initial transient period when the field associated with the floating gate and the substrate is maximum. But this mechanism is relatively weak due to the low field (k<0.5) between the floating gate and the substrate. This is represented by an arrow of intermediate thickness. The remaining mechanism 442 , as shown in FIG. 4 , is insignificant due to the high hole energy barrier of 4.7 ev and the low field across SiO ₂ -Ta ₂ O ₅ between the silicon substrate and the silicon floating gate. This is represented by a thinner arrow. Therefore, primary charge transport between the silicon floating gate and the aluminum control gate is also maintained by this invention during the write process.

[0051] The band diagrams of FIGS. 2 - 4 are useful to show the retention enhancement and read-disturb immunity of the nonvolatile device of the present invention. Typically, for a device design employing a power supply of 2.5 V to 3.3 V (Vdd), the threshold differential between the states 0 and 1 is around 2-3 V. For a worst case stack design of K=0.5, the built-in potential is less than 1.5 V and therefore the associated internal field due to the stored hole charge may not exceed 2.5 E6 V/CM. Hole emission is negligible since the hole barrier is high to both the first insulator region and also the second insulator region (3.1 ev to ZrO ₂ and 2.9 ev to Ta ₂ O ₅ ). Additionally, electron emission from the substrate and from the control gate are negligible since the electron barrier is high (3.2 ev from the substrate to the first insulator region and 3.8 ev from the control gate to the second insulator region). Therefore, the charge retention for the nonvolatile device of the present invention is expected to be excellent.

[0052] With respect to the read-disturb immunity, a positive potential of Vdd is applied to the control gate and the bit line while the substrate and the source is held to the ground potential during a read pulse as shown in FIG. 7 . For those word line bits at 0 state in which the floating gate is storing holes and is providing a built-in potential, the peak field may exceed 4E6 V/CM. However, lower mobility of holes and higher barrier height would prevent any significant charge loss compared to a conventional design. On the other hand, for bits at 1 state, the field is reduced to less than 2.5 E6 V/CM. Therefore, electron emission and tunneling from the floating gate is expected to be negligible even with a relatively lower 1.5 ev barrier height from the floating gate to the ZrO ₂ of the second insulator region. As such, the read-disturb immunity for the nonvolatile device of the present invention is expected to be significantly enhanced.

[0053] FIGS. 5 - 7 generally illustrate the operating conditions for one embodiment of the nonvolatile device of the present invention. The equivalent oxide thickness (t _ox.eq. ) of the gate stack is approximately 10 nm, wherein the thickness of SiO ₂ is approximately 2 nm, the t _ox.eq. of Ta ₂ O ₅ is approximately 4 nm, and the t _ox.eq. of ZrO ₂ is approximately 4 nm. In this embodiment, the power supply voltage is approximately 2.5 V, the threshold voltage in the nonconducting state (VT(1)) is approximately 2.5-3.0 V and the threshold voltage in the conducting state (VT(0)) is approximately 0.5-1.0 V.

[0054] FIG. 5 illustrates operating conditions for erasing an NFET nonvolatile device of FIG. 1 . Erasing the NFET nonvolatile device involves a transition from a nonconducting state 1 to a conducting state 0. As such, holes are to be transported into and/or electrons are to be transported off the floating gate to lower the threshold voltage from VT(1) to VT(0). The drain voltage (Vdd), the source voltage (Vss), and the substrate voltage (Vsx) are pulled to the ground potential. A positive programming pulse is applied to the control gate as the control gate voltage (Vcg). In one embodiment, the programming pulse is approximately +12 V. In one embodiment, the +12 V programming pulse has a duration approximately in the range of 1 to 10 msec. One of ordinary skill in the art will understand that this programming pulse is capable of being produced from the 2.5 V power supply using charge pumps.

[0055] FIG. 6 illustrates operating conditions for writing an NFET nonvolatile device of FIG. 1 . Writing the NFET nonvolatile device involves a transition from a conducting state 0 to a nonconducting state 1. As such, electrons are to be transported into and/or holes are to be transported off of the floating gate to raise the threshold voltage from VT(0) to VT(1). The substrate voltage (Vsx) is allowed to float, and the source voltage (Vss) and the control gate voltage (Vcg) are pulled to the ground potential. A positive programming pulse is applied to the drain to enable the substrate voltage (Vsx) to float up by capacitive coupling. In one embodiment, the programming pulse is approximately +12 V. In one embodiment, the duration of the +12 V programming pulse is approximately 1 to 10 msec. One of ordinary skill in the art will understand that this programming pulse is capable of being produced from the 2.5 V power supply using charge pumps.

[0056] FIG. 7 illustrates operating conditions for reading an NFET nonvolatile device of FIG. 1 . The power supply voltage (Vdd), e.g. 2.5 V, is applied at both the drain node as well as at the control gate (Vcg). The substrate voltage (Vsx) and the source voltage (Vss) are pulled to the ground potential. Current (I) is sensed between the source and the drain to determine if the NFET nonvolatile device is in a conducting low threshold state 0 or in a nonconducting high threshold state 1.

[0057] FIG. 8 illustrates one embodiment of a floating plate embodiment of the nonvolatile device of the present invention. The device is similar to that shown in FIG. 1 , except that a floating plate replaces the floating gate as the floating charge-storage region. As will be explained in more detail below, the floating plate has silicon nano crystals that enhance field emissions and at least an order of magnitude thinner (<10 nm) than the thickness of the floating gate.

[0058] The device 800 is formed on a substrate 802 . In one embodiment, the substrate includes p− silicon. A first source/drain region 804 and a second source/drain region 806 are formed in the substrate between isolation regions 808 . The source/drain regions are separated by a channel region 810 of the substrate. In one embodiment, each of the source/drain regions include n− silicon source/drain extensions positioned to define the channel region in the substrate, and n+ silicon used to provide regions for a drain contact and a source contact.

[0059] An asymmetric gate stack 812 is formed over the channel region of the substrate. The gate stack separates a control gate 814 from the substrate. According to one embodiment, the control gate includes aluminum, and is connected to an aluminum word line. One embodiment of the asymmetric gate stack 812 includes a first insulator region 816 , a floating plate 818 that functions as a floating charge-storage region, and a second insulator region 820 . The gate stack is engineered to provide the desired asymmetric barrier energies for charge transport between the three nodes (substrate, floating charge-storage region, and control gate) of the device, and is further engineered to provide the desired electric fields between the three nodes of the device.

[0060] In one embodiment of the asymmetric gate stack, the first insulator region 816 includes a layer of Silicon Dioxide (SiO ₂ ) 822 disposed over the channel region, and a layer of Tantalum Oxide (Ta ₂ O ₅ ) 824 disposed over the layer of SiO ₂ . One embodiment of the layer of SiO ₂ includes approximately 2 nm of NH ₃ -treated SiO ₂ . Another embodiment of the layer of SiO ₂ includes approximately 2 nm of NO-treated SiO ₂ . In one embodiment, the layer of Ta ₂ O ₅ has an equivalent oxide thickness (t _ox.eq. ) of approximately 3 to 5 nm. In one embodiment, the layer of Ta ₂ O ₅ has an equivalent oxide thickness (t _ox.eq. ) of approximately 4 nm. A layer of Zirconium Oxide (ZrO ₂ ) 826 is disposed on the silicon floating plate. In one embodiment, the layer of ZrO ₂ has an equivalent oxide thickness (t _ox.eq. ) of approximately 4 to 5 nm. An Oxide-Nitride-Oxide (ONO) sidewall 828 surrounds the asymmetric gate stack 812 and isolates the device from other integrated circuit devices.

[0061] One embodiment includes a thin layer of silicon-rich-oxide (SRO) as the floating plate 818 . Another embodiment includes a thin layer of silicon-rich-nitride (SRN) as the floating plate 818 . The actual thickness of the floating plate is approximately between 3 nm to 10 nm. The equivalent oxide thickness (t _ox.eq. ) of the floating plate is approximately between 1.5-5 nm. In one embodiment, the floating plate has a thickness of about 5 nm and an equivalent oxide thickness (tox.eq) of about 2.5 nm. The characteristics of SRO and SRN will be described in more detail below with respect to FIGS. 9 - 13 .

[0062] As an overview, SRO and SRN contain silicon nano crystals that are capable of storing charge. These silicon nano crystals are capable of simultaneously acting as charge trapping centers as well as charge emission centers. The silicon nano crystals modulate the local potential distributions and enhance the field emission. For effective charge storage, one embodiment includes a desired composition for SRO that has a refractive index of 1.6, and a desired composition for SRN that has a refractive index of 2.2. Other embodiments employ a wider range of composition of SRO or SRN. The refractive index of SRO and SRN is developed below with respect to FIGS. 9 - 13 . The enhanced field emissions allow floating plate devices to be programmed at a significantly reduced average field of approximately 7E6 V/CM as compared to the floating gate device programming field of 12E6 V/CM. The endurance (write-erase cycles before failure) of the device is enhanced by many orders of magnitude by the lower effective programming field. The programming voltage for the floating plate embodiment of FIG. 8 is +/−9 V for a total gate stack equivalent oxide thickness (tox.eq) of 13 nm including the SRO/SRN layer; whereas the programming voltage for the floating gate embodiment of FIG. 1 is +/−12 V.

[0063] FIGS. 9 - 13 show relevant properties of silicon rich insulators (SRI) from the standpoint of charge trapping and charge injection or emission. FIG. 9 is a graph showing refractive index of silicon-rich silicon nitride films versus SiH ₂ Cl ₂ /NH ₃ flow rate ratio (R). This graph is provided herein to illustrate the known relationship between the silicon amount and the refractive index. The graph indicates that the index of refraction increases linearly with increasing silicon content. As such, the index of refraction of the films can be used as an indication of the silicon content of the films.

[0064] FIG. 10 is a graph showing current density versus applied field for silicon-rich silicon nitride films having different percentages of excess silicon. The current density (J) is represented in amperes/cm ² , and log J is plotted against the electric field E (volts/cm) for Si ₃ N ₄ layers having a SiH ₂ Cl ₂ /NH ₃ flow rate ratio R of 0.1, 3, 5, 10, 15 and 31. This graph is provided herein to illustrate the known relationship between the amount of silicon and the conductivity of the film. The plot shows that the Si ₃ N ₄ layers having small additions of silicon (R=3 and 5) exhibit a relatively small conductivity increase over stoichiometric Si ₃ N ₄ . The plot further shows that increasing silicon content at or above R=10 substantially increases or enhances the conductivity.

[0065] FIGS. 11 and 12 provide graphs that illustrate the known relationship between the flatband shift and applied fields for films having varying percentages of excess silicon as represented by the SiH ₂ Cl ₂ /NH ₃ flow rate ratio R. FIG. 11 is a graph showing flatband shift versus time at an applied field of 4×10 ⁶ volts/cm for silicon-rich silicon nitride films having varying percentages of excess silicon. For R=3, the flatband shift is greater than the shifts produced by films having an R of 0.1, 10 or 15. The film having an R of 10 provides a greater flatband shift than a film having an R of 15. FIG. 12 is a graph showing flatband shift versus time at an applied field of 7×10 ⁶ volts/cm for silicon-rich silicon nitride films having varying percentages of excess silicon. The flatband shift produced by the R=3 film is even greater than that shown in FIG. 11 , while the shifts produced by the R=10 and R=15 films do not change as appreciably. FIGS. 11 and 12 are provided to illustrate the characteristics of a charge storing medium and a more conductive charge injector medium as further explained below.

[0066] The graphs of FIGS. 9 - 12 , which were described above, indicate that at low additional silicon content, silicon-rich Si ₃ N ₄ films function as a charge storing medium as they exhibit appreciably enhanced trapping characteristics (as shown by the high flatband shifts at moderate and high applied electric fields in FIGS. 11 and 12 , respectively) without exhibiting appreciably enhanced conductivity characteristics as shown in FIG. 9 .

[0067] Silicon-rich silicon nitride films deposited at an R of 3 or 5 (for a refractive index of 2.10 and 2.17, respectively) will possess enhanced charge storing characteristics. This family of silicon rich nitride is identified herein as charge storing SRN or CS-SRN. In general, silicon-rich nitride films having an R greater than 0.1 and less than 10 (or, more specifically, having an index of refraction between approximately 2.10 and 2.30) will provide appreciably enhanced charge trapping or charge storing properties without providing appreciably enhanced charge conduction. This charge trapping is characteristic of a charge storing medium that can be used as a floating plate within a gate stack of a NV device as illustrated in FIG. 8 .

[0068] Silicon-rich nitride films having an R greater than 10 (or, more specifically, having an index of refraction greater than 2.3) are referred to as an injector medium. Silicon nitride injectors are preferred over silicon oxide injectors because of the superior high temperature stability of the former material. Silicon readily diffuses within silicon oxide at elevated processing temperatures, which disrupts the injection threshold by reducing the localized field distortions. However, even at higher processing temperature, silicon does not readily diffuse within Si ₃ N ₄ . A silicon-rich Si ₃ N ₄ (SRN) injector provides appreciably enhanced charge conductance without providing appreciably enhanced charge trapping over stoichiometric Si ₃ N ₄ . This is illustrated in FIGS. 3 and 4 , which shows progressively reduced flatband shifts for R=10 and R=15 with progressively increased conduction. The family of materials acting as injector material is identified as “i-SRN.”

[0069] FIG. 13 is a graph showing apparent dielectric constant K versus refractive index for both Silicon Rich Nitride (SRN) and Silicon Rich Oxide (SRO). The SRN and SRO plotted in this graph were provided using a Low Pressure Chemical Vapor Deposition (LPCVD) process. The SRO was fabricated at approximately 680° C., and the fabricated structure included 100 Å oxide and 150 Å SRO. The SRN was fabricated at approximately 770° C., and the fabricated structure included 45 Å oxide and 80 Å SRN. As shown in the graph, the dielectric constant of silicon is around 12. Materials with a higher K than silicon are conventionally termed a high K material, and materials with a lower K than silicon are conventionally termed a low K material. SRN that has a refractive index of 2.5 or greater and SRO that has a refractive index of 1.85 or greater have apparent dielectric constants that are greater than 12. Injector SRI includes these high K SRO and high K SRN family of materials. In the present invention, injector SRI layers are employed in the gate stack to further lower the programming field and enhance endurance.

[0070] In one embodiment, the floating plate embodiment of FIG. 8 is modified by incorporating an additional thin layer of “injector” SRN (i.e. SRN having a refractive index greater than 2.5) between the aluminum control gate and the ZrO ₂ . In another embodiment, the floating plate embodiment of FIG. 8 is modified by incorporating an additional thin layer of “injector” SRN between the SiO ₂ and the Ta ₂ O ₅ . In another embodiment, the floating plate embodiment of FIG. 8 is modified by incorporating one additional thin layer of “injector” SRN between the aluminum control gate and the ZrO ₂ , and another additional thin layer of “injector” SRN between the SiO ₂ and the Ta ₂ O ₅ . In one embodiment, the thickness of these thin layers of injector SRN is approximately 2-3 nm. These structures lower the programming field. This concept is generally described and illustrated below in FIGS. 14 - 19 . Applicant discusses this concept in detail in the U.S. patent application entitled “Scalable Flash/NV Structures and Devices With Extended Endurance,” Ser. No. 09/944,985, filed on Aug. 30, 2001, which has been incorporated by reference into the present application.

[0071] FIG. 14 is a cross-section view of a conventional nonvolatile field effect transistor (NV FET) device. The illustrated device is fabricated on a silicon substrate 1412 such as a p silicon substrate or p-well in which case it is referred to as a source electrode (SE), and is separated from other devices by the isolation trenches 1414 . The device 1410 further includes diffused regions that function as a drain region 1416 and a source region 1418 , such as the illustrated n+ diffused regions in the p substrate. A field effect transistor (FET) channel 1420 is formed in the substrate between the drain and source regions. A source contact 1422 is formed to electrically couple with the source region 1418 , and a bit contact 1424 is formed to electrically couple with the drain region 1416 . A floating polysilicon gate 1426 is formed over the FET channel 1420 , and is separated from the FET channel 1420 by tunnel oxide 1428 . A control gate 1430 , referred to as a program electrode (PE) for the illustrated embodiment, is formed over the floating polysilicon gate 1426 . An oxide/nitride/oxide (ONO) interpoly dielectric 1432 is provided around and between the PE 1430 and the floating gate 1426 . A bit line is connected to the bit contact, and a word line is connected to the PE. An oxide 1433 is formed around the NV FET device.

[0072] Common dimensions for a typical NV FET device in the 0.13 to 0.15 μm technology generations are provided below. The cell size for a NAND gate is approximately 0.15 μm ² . The FET channel is approximately 150 nm wide. Both the floating gate and the PE are approximately 150 nm wide and about 250 nm thick. The tunnel oxide separating the floating gate from the FET channel is approximately 8 nm thick. The ONO interpoly dielectric separating the PE and the floating gate is approximately 15 nm thick. The programming voltage applied to the PE is about 16 volts, and the pulse width of a programming pulse is approximately 1 ms. The field generated across the tunnel oxide is approximately 12×10 ⁶ V/cm. The minimum program window (V _T (“1”)-V _T (“0”)) is approximately 2 V. The minimum program window is defined as the difference in the threshold voltages for a device with a stored one and a device with a stored zero. The endurance for a typical NV FET device is about 10 ⁵ write/erase cycles. The power supply V _DD is 3.3 V.

[0073] FIG. 15 illustrates the capacitive coupling for a conventional NV FET device. Again, the device 1510 includes a control gate or PE 1530 , a floating gate 1526 , and a substrate or SE 1512 . A programming voltage VP ₁ of 16 V is applied to the control gate. The electric field across about 8 nm of tunnel oxide 1528 (E _TUN.OX ) is approximately 12×10 ⁶ V/cm, which reflects a coupling efficiency of about 60%. The low efficiency is attributable to the geometry and capacitor divider effects of the cell.

[0074] FIG. 16 illustrates the capacitive coupling for a nonvolatile floating plate device. The device 1640 includes a control gate 1630 separated from a substrate by a gate insulator stack 1642 . The gate insulator stack 1642 includes a tunnel insulator 1644 , charge centers 1646 that form a floating plate capable of storing charge, and a charge blocking dielectric 1648 . A programming voltage VP ₂ of 9.6 V is applied to the control gate 1630 . As there is no separate floating gate, the coupling efficiency is 100%. The average electric field E _AVG between the control gate 1630 and the substrate 1612 is between about 6 to 7×10 ⁶ V/cm.

[0075] FIG. 17 illustrates the average field enhancement due to the incorporation of a top injection layer in a gate stack for a nonvolatile floating plate device. In this illustration, the gate insulator stack 1740 , which is interposed between the control gate 1730 and the substrate 1712 , includes a tunnel layer 1750 that includes SiO ₂ and Ta ₂ O ₅ , a charge blocking layer 1752 that includes charge centers (CS-SRN) 1746 that form a floating plate or a charge storing medium, a charge blocking layer that includes ZrO ₂ , and an injector layer (i-SRN) 1754 . The injector layer (i-SRN) 1754 enhances the average electric field by a factor of about 1.5 (1.5×) across the entire gate stack. A programming voltage VP ₃ of 5.5 to 6.5 V is applied to the control gate 1730 . The resulting average electric field E _AVG between the control gate 1730 and the substrate 1712 is reduced to about 4×10 ⁶ V/cm.

[0076] FIG. 18 illustrates the average field enhancement due to the incorporation of a bottom injection layer in a gate stack for a nonvolatile floating plate device. In this illustration, the gate insulator stack 1840 , which is interposed between the control gate 1830 and the substrate 1812 , includes an injector layer (i-SRN) 1856 over SiO ₂ , a tunnel layer of Ta ₂ O ₅ 1850 , and a charge blocking layer of ZrO ₂ 1852 that includes charge centers (CS-SRN) 1846 to form a floating plate or a charge storing medium. In this embodiment, a programming voltage VP ₃ of 5.5 to 6.5 V is applied to the control gate 1830 . The resulting average electric field E _AVG between the control gate 1830 and the substrate 1812 is reduced to about 4×10 ⁶ V/cm. This illustrates that the same general results are achieved whether the injector layer is on top of the gate insulator stack or on the bottom of the gate insulator stack. That is, the injector layer (i-SRN) enhances the electric field by a factor of about 1.5×.

[0077] FIG. 19 illustrates the average field enhancement due to the incorporation of both a top injection layer (i-SRN) and a bottom injection layer (i-SRN) in a gate stack for a nonvolatile floating plate device. In this illustration, the gate insulator stack 1940 , which is interposed between the control gate 1930 and the substrate 1912 , includes a first injector layer SRN 1956 over a thin SiO ₂ layer, a tunnel layer of Ta ₂