Title:
Semiconductor integrated circuit device and process for manufacturing the same
Document Type and Number:
Kind Code:
A1

Abstract:
A disadvantage upon heat treatment in an oxygen atmosphere of a dielectric film formed on a lower electrode of capacitance device of DRAM that oxygen permeating the lower electrode oxidizes a barrier layer to form an oxide layer of high resistance and low dielectric constant is prevented. An Ru silicide layer is formed on the surface of a plug in a through hole formed below a lower electrode for an information storage capacitance device C and an Ru silicon nitride layer is formed further on the surface of the Ru silicide layer. Upon high temperature heat treatment in an oxygen atmosphere conducted in the step of forming a dielectric film on the lower electrode, the Ru silicon nitride layer is oxidized sacrificially into an Ru silicon oxynitride to prevent progress of oxidation in the Ru silicide layer.
Inventors:
Iijima, Shinpei (Akishima, JP)
Ohji, Yuzuru (Hinode, JP)
Kunitomo, Masato (Ome, JP)
Hiratani, Masahiko (Akishima, JP)
Matsui, Yuichi (Kokubunji, JP)
Ohta, Hiroyuki (Tsuchiura, JP)
Kumagai, Yukihiro (Chiyoda, JP)
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Sponsored by:
Flash of Genius
Application Number:
10/321614
Publication Date:
06/12/2003
Filing Date:
12/18/2002
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Referenced by:
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Export Citation:
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Assignee:
Hitachi, Ltd.
Primary Class:
257/E21.019
Other Classes:
257/E21.011, 257/296
International Classes:
(IPC1-7): H01L027/108; H01L029/94; H01L029/76; H01L031/119
Attorney, Agent or Firm:
Miles & Stockbridge P.C. (Suite 500, McLean, VA, 22102-3833, US)
Claims:

What is claimed is:



1. A semiconductor integrated circuit device in which a capacitance device constituted with a first electrode comprising a first metal, a dielectric film and a second electrode comprising a second metal is formed on a main surface of a semiconductor substrate, and in which a first semiconductor region formed in the semiconductor substrate and the first electrode of the capacitance device are electrically connected by way of a silicon plug inside a first contact hole formed in a first insulating film over the first semiconductor region, wherein a metal silicide layer is formed on the surface of the silicon plug, and at least one of a metal silicon nitride layer or a metal silicon oxynitride layer is formed on the surface of the metal silicide layer.

2. A semiconductor integrated circuit device in which a capacitance device constituted with a first electrode comprising a first metal, a dielectric film and a second electrode comprising a second metal is formed on a main surface of a semiconductor substrate, and in which a first semiconductor region formed in the semiconductor substrate and the first electrode of the capacitance device are electrically connected by way of a silicon plug in the inside of a second contact hole formed in a second insulating film over the first semiconductor region, and a metal plug inside a first contact hole formed in a first insulating film over the second insulating film, wherein a metal silicide layer is formed on the surface of the silicon plug, and at least one of a metal silicon nitride layer or a metal silicon oxynitride layer is formed on the surface of the metal silicide layer.

3. A semiconductor integrated circuit device according to claim 1, wherein the first electrode of the capacitance device is formed inside a groove formed in a third insulating film over the first insulating film.

4. A semiconductor integrated circuit device according to claim 1, wherein the first electrode for the capacitance device comprises a columnar body formed over the first contact hole.

5. A semiconductor integrated circuit device according to claim 1, wherein an oxygen absorption layer is formed in the first electrode for the capacitance device.

6. A semiconductor integrated circuit device according to claim 2, wherein the metal plug inside the first contact hole contains Ru, Pt or Ir as a main ingredient.

7. A semiconductor integrated circuit device according to claim 1, wherein the first metal constituting the first electrode contains Ru as the main ingredient.

8. A semiconductor integrated circuit device according to claim 1, wherein the first metal constituting the first electrode contains Pt or Ir as the main ingredient.

9. A semiconductor integrated circuit device according to claim 1, wherein the metal silicide layer formed on the surface of the silicon plug comprises Ru silicide, Pt silicide, Ti silicide or Co silicide.

10. A semiconductor integrated circuit device according to claim 1, wherein the metal silicon nitride layer formed on the surface of the metal silicide layer comprises Ru silicon nitride, Pt silicon nitride, Ti silicon nitride or Co silicon nitride, and the metal silicon oxynitride layer comprises an oxide thereof.

11. A semiconductor integrated circuit device according to claim 1, wherein the second metal constituting the second electrode comprises W, Ru, Pt, Ir, TiN or a laminate thereof,

12. A semiconductor integrated circuit device according to claim 1, wherein the oxygen absorption layer comprises W silicide, Ti silicide, Ru silicide, Co silicide, Al or TaN.

13. A semiconductor integrated circuit device according to claim 1, wherein the dielectric film contains tantalum oxide as the main ingredient.

14. A semiconductor integrated circuit device according to claim 1, wherein the dielectric film contains one of titanium oxide, barium titanate, strontium titanate, barium strontium titanate or lead titanate as the main ingredient.

15. A method of manufacturing a semiconductor integrated circuit device comprising the following steps of: (a) forming a first insulating film on a main surface of a semiconductor substrate formed with a first semiconductor region and then forming a first contact hole to the first insulating film over the first semiconductor region, (b) forming a silicon plug inside the first contact hole, (c) forming a third insulating film over the first insulating film, and then etching the third insulating film over the first contact hole, thereby forming a groove in which the surface of the silicon plug is exposed at the bottom thereof, (d) forming a metal silicide layer on the surface of the silicon plug and then forming a metal silicon nitride layer on the surface of the metal silicide layer, (e) forming a first electrode for the capacitance device comprising a first metal inside the groove, and electrically connecting the first electrode and the first semiconductor region through the first contact hole, (f) forming a dielectric film for the capacitance device over the first electrode and then applying a heat treatment to the dielectric film in an oxygen-containing atmosphere, and (g) forming a second electrode comprising a second metal for the capacitance device over the dielectric film.

16. A method of manufacturing a semiconductor integrated circuit device comprising the following steps of: (a) forming a second insulating film on a main surface of a semiconductor substrate formed with a first semiconductor region and then forming a second contact hole on the second insulating film over the first semiconductor region, (b) forming a silicon plug in the second contact hole, (c) forming a first insulating film over the second insulating film, and then etching the first insulating film over the second contact hole thereby forming a first contact hole in which the surface of the silicon plug is exposed at the bottom thereof, (d) forming a metal silicide layer on the surface of the silicon plug and then forming a metal silicon nitride layer on the surface of the metal silicide layer, (e) forming a metal plug inside the first contact hole, (f) forming a third insulating film over the first insulating film and then etching the third insulating film over the first contact hole thereby forming a groove in which the surface of the metal plug is exposed at the bottom thereof, (g) forming a first electrode comprising a first metal for the capacitance device inside the groove, and electrically connecting the first electrode and the first semiconductor region through the first contact hole and the second contact hole, (h) forming a dielectric film for the capacitance device over the first electrode and then applying a heat treatment to the dielectric film in an oxygen-containing atmosphere, and (i) forming a second electrode comprising a second metal for the capacitance device over the dielectric film.

17. A method of manufacturing a semiconductor integrated circuit device comprising the following steps of: (a) forming a first insulating film on a main surface of a semiconductor substrate formed with a first semiconductor region and then forming a first contact hole on the first insulating film over the first semiconductor region, (b) forming a silicon plug in the first contact hole, (c) forming a third insulating film over the first insulating film, and then etching the third insulating film over the first contact hole thereby forming a groove in which the surface of the silicon plug is exposed at the bottom thereof, (d) forming a metal silicide layer on the surface of the silicon plug and then forming a metal silicon nitride layer on the surface of the metal silicide layer, (e) forming a first metal film on the third insulating film including the inside of the groove thereby burying the first metal film inside the groove and then removing the first metal film outside of the groove, (f) removing the third insulating film by etching to form a columnar first electrode comprising the first metal for the capacitance device over the first contact hole and electrically connecting the first electrode and the first semiconductor region by way of the first contact hole, (g) forming a dielectric film for the capacitance device over the first electrode and then applying a heat treatment to the dielectric film in an oxygen-containing atmosphere, and (h) forming a second electrode comprising a second metal for the capacitance device over the dielectric film.

18. A method of manufacturing a semiconductor integrated circuit device comprising the following steps of: (a) forming a second insulating film on a main surface of a semiconductor substrate formed with a first semiconductor region and then forming a second contact hole on the second insulating film over the first semiconductor region, (b) forming a silicon plug inside the second contact hole, (c) forming a first insulating film over the second insulating film, and then etching the first insulating film over the second contact hole thereby forming a first contact hole in which the surface of the silicon plug is exposed at the bottom thereof, (d) forming a metal silicide layer on the surface of the silicon plug and then forming a metal silicon nitride layer on the surface of the metal silicide layer, (e) forming a metal plug inside the first contact hole, (f) forming a third insulating film over the first insulating film and then etching the third insulating film over the first contact hole thereby forming a groove in which the surface of the metal plug is exposed at the bottom thereof, (g) forming a first metal film on the third insulating film including the inside of the groove thereby burying the first metal film inside the groove and then removing the first metal film outside of the groove, (h) etching to remove the third insulating film to form a columnar first electrode comprising the first metal film for a capacitance device over the first contact hole, and electrically connecting the fist electrode and the first semiconductor region through the first contact hole and the second contact hole, (i) forming a dielectric film for the capacitance device over the first electrode and then applying a heat treatment to the dielectric film in an oxygen-containing atmosphere, and (j) forming a second electrode comprising a second metal for the capacitance device over the dielectric film.

19. A method of manufacturing a semiconductor integrated circuit device according to claim 15, wherein the step of forming the first electrode for the capacitance device comprising the first metal inside the groove includes a first step of forming a first metal film on the third insulating film including the inside of the groove by a sputtering method, a second step of forming the first metal film on the third insulating film including the inside of the groove by a CVD method after the first step, and a third step of removing the first metal film of the two layers formed on the third insulating film after the second step.

20. A method of manufacturing a semiconductor integrated circuit device according to claim 17, wherein the step of burying the first metal film inside the groove by forming the first metal film on the third insulating film including the inside of the groove comprises a first step of forming the first metal film on the third insulating film including the inside of the groove by a sputtering method and a second step of forming the first metal film on the third insulating film including the inside of the groove by a CVD method after the first step.

21. A method of manufacturing a semiconductor integrated circuit device according to claim 15, wherein the step of forming the first electrode comprising the first metal for the capacitance device inside the groove includes a first step of forming a first metal film on the third insulating film including the inside of the groove, a second step of forming a first conductive film on the third insulating film including the inside of the groove after the first step, a third step of forming the first metal film on the third insulating film including the inside of the groove after the second step, and a fourth step of removing the two layers of the first metal films and the first conductive film put between them on the third insulating film thereby forming an oxygen absorption layer comprising the first conductive film inside the first electrode.

22. A method of manufacturing a semiconductor integrated circuit device according to claim 17, wherein the step of forming the first metal film on the third insulating film including the inside of the groove thereby burying the first metal film inside the groove and then removing the first metal film outside of the groove comprises a first step of forming the first metal film on the third insulating film including the inside of the groove, a second step of forming the first conductive film on the third insulating film including the inside of the groove after the first step, a third step of forming the first metal film on the third insulating film including the inside of the groove after the second step and a fourth step of removing the two layers of the first metal films and the first conductive film put between them on the third insulating film after the third step, and the step of forming the columnar first electrode comprising the first metal film for the capacitance device over the first contact hole comprises a step of forming an oxygen absorption layer comprising the first conductive film inside the first electrode.

23. A method of manufacturing a semiconductor integrated circuit device according to claim 16, wherein the step of forming the metal plug inside the first contact hole comprises a first step of depositing a metal film constituting the metal plug and a first conductive film over the first insulating film including the inside of the first contact hole and a second step of removing the metal film and the first conductive film over the first insulating film thereby forming an oxygen absorption layer comprising the first conductive film inside the metal plug after the first step.

24. A method of manufacturing a semiconductor integrated circuit device according to claim 17, wherein the step of burying the first metal film inside the groove and then removing the first metal film outside of the groove comprises a first step of forming a first metal film on the third insulating film including the inside of the groove, a second step of forming a silicon film on the third insulating film including the inside of the groove after the first step, a third step of removing the silicon film on the third insulating film after the second step, a fourth step of reacting the first metal film and the silicon film inside the groove by a heat treatment to form an oxygen absorption layer comprising a metal silicide inside the groove after the third step, a fifth step of forming the first metal film on the third insulating film including the inside of the groove after the fourth step and a sixth step of removing the two layers of the first metal films outside of the groove after the fifth step.

25. A method of manufacturing a semiconductor integrated circuit device according to claim 15, wherein the step of forming the metal silicide layer on the surface of the silicon plug comprises a first step of depositing a metal film over the third insulating film including the inside of the groove by a sputtering method and a second step of reacting the silicon plug and the metal film by a heat treatment after the first step.

26. A method of manufacturing a semiconductor integrated circuit device according to claim 15, wherein the metal silicide layer formed on the surface of the silicon plug comprises Ru silicide, Pt silicide, Ti silicide or Co silicide.

27. A method of manufacturing a semiconductor integrated circuit device according to claim 15, wherein the metal silicon nitride layer on the surface of the metal silicide layer is formed by heat treating the metal silicide layer in an ammonia gas atmosphere.

28. A method of manufacturing a semiconductor integrated circuit device according to claim 15, wherein the metal silicon nitride layer on the surface of the metal silicide layer is formed by heat treating the metal silicide layer in a plasma atmosphere containing active nitrogen.

29. A method of manufacturing a semiconductor integrated circuit device according to claim 27, wherein the thickness of the metal silicon nitride layer is from 0.5 nm to 1.0 nm.

30. A method of manufacturing a semiconductor integrated circuit device according to claim 15, wherein the step of forming the dielectric film for the capacitance device over the first electrode and then heat treating the dielectric film in the oxygen containing atmosphere conducts formation of the dielectric film and the heat treatment therefor each twice separately.

31. A method of manufacturing a semiconductor integrated circuit device according to claim 15, wherein the metal silicide layer formed on the surface of the silicon plug comprises Ru silicide, Pt silicide, Ti silicide or Co silicide.

32. A method of manufacturing a semiconductor integrated circuit device according to claim 15, wherein the metal silicon nitride layer formed on the surface of the metal silicide layer comprises Ru silicon nitride, Pt silicon nitride, Ti silicon nitride or Co silicon nitride.

33. A method of manufacturing a semiconductor integrated circuit device according to claim 15, wherein the first metal constituting the first electrode contains Ru as the main ingredient.

34. A method of manufacturing a semiconductor integrated circuit device according to claim 15, wherein the first metal constituting the first electrode contains Pt or Ir as the main ingredient.

35. A method of manufacturing a semiconductor integrated circuit device according to claim 15, wherein the dielectric film contains tantalum oxide as the main ingredient.

36. A method of manufacturing a semiconductor integrated circuit device according to claim 15, wherein the dielectric film contains one of titanium oxide, barium titanate, strontium titanate, barium strontium titanate or lead titanate as the main ingredient.

37. A method of manufacturing a semiconductor integrated circuit device according to claim 15, wherein the second metal constituting the second electrode is W, Ru, Pt, Ir, TiN or a laminate thereof.

38. A method of manufacturing a semiconductor integrated circuit device according to claim 16, wherein the metal plug inside the first contact hole contains Ru, Pt or Ir as the main ingredient.

39. A method of manufacturing a semiconductor integrated circuit device according to claim 21, wherein the oxygen absorption layer comprises W silicide, Ti silicide, Ru silicide, Co silicide or Al or TaN.

40. A semiconductor integrated circuit device in which a groove is formed in an insulating film formed on a main surface of a semiconductor substrate, and a capacitance device constituted by laminating a first electrode comprising a first metal, a dielectric film and a second electrode comprising a second metal is formed inside the groove, wherein an bonding layer comprising a material having a higher adhesion to the insulating film than that of the first metal is formed on at least a portion of a boundary between the inner wall of the groove comprising the insulating film and the first electrode.

41. A semiconductor integrated circuit device according to claim 40, wherein the first metal constituting the first electrode contains Ru as the main ingredient.

42. A semiconductor integrated circuit device according to claim 41, wherein the bonding layer contains tantalum oxide or tantalum nitride as the main ingredient.

43. A semiconductor integrated circuit device according to claim 41, wherein the dielectric film contains tantalum oxide as the main ingredient.

44. A method of manufacturing a semiconductor integrated circuit device including the following steps of: (a) forming an insulating film on a main surface of a semiconductor substrate and then etching the insulating film thereby forming a groove, (b) depositing a tantalum oxide film on the insulating film including the inside of the groove by a CVD method, (c) removing the tantalum oxide film outside the groove and at the bottom of the groove thereby leaving tantalum oxide film on the side wall of the groove and (d) after the step (c), forming a first electrode for a capacitance device comprising a first metal inside the groove, forming a dielectric film for the capacitance device over the first electrode and forming a second electrode for the capacitance device comprising a second metal over the dielectric film.

45. A method of manufacturing a semiconductor integrated circuit device according to claim 44, wherein the first metal constituting the first electrode contains Ru as the main ingredient.

Description:

BACKGROUND OF THE INVENTION

[0001] This invention concerns a semiconductor integrated circuit device and a manufacturing technique therefor and, more in particular, it relates a technique effective to application to a semiconductor integrated circuit device having a DRAM (Dynamic Random Access Memory).

[0002] Memory cells of DRAM are generally located at intersection between each of a plurality of word lines and each of a plurality of bit lines arranged in a matrix on a main surface of a semiconductor substrate. One memory cell is constituted with one MISFET (Metal Insulator Semiconductor Field Effect Transistor) for selecting the cell and one information storage capacitance device (capacitor) connected in series with the MISFET.

[0003] The memory cell selecting MISFET is formed in a active region surrounded at the periphery thereof with a device isolation region and mainly comprises a gate insulating film, a gate electrode constituted integrally with a word line and a pair of semiconductor regions constituting the source and drain. Memory cell selecting MISFETs are usually formed by two in one active region and one of the source and drain (semiconductor region) of the two MISFET is made in common at the central portion of the active region.

[0004] The bit lines are disposed over the memory cell selecting MISFET and connected electrically through a contact hole in which a plug is buried with one of the source and drain (semiconductor region) (a semiconductor region in common with two MISFETs) Further, the information storage capacitance device is disposed over the bit line and electrically connected in the same manner through a contact hole in which a plug comprising polycrystal silicon or the like is buried with the other of the source and drain (semiconductor region) of the memory cell selecting MISFET.

[0005] As described above, DRAM in recent years adopts a sterical structure in which the information storage capacitance device is disposed over the bit line as a countermeasure for coping with reduction in the stored charge amount in accordance with the refinement of the memory cell. However, in the case of larger capacity DRAM of 256 Mbits or more in which the memory cell is to be refined further, it is considered difficult to cope with the reduction of the stored charge amount by merely making the information storage capacitance device sterical.

[0006] Then, it has been studied to adopt high dielectric (ferroelectric) materials such as tantalum oxide (Ta2O5), strontium titanate (STO) and barium strontium titanate (BST) as the dielectric film for the information storage capacitance device. This is because the relative dielectric constant is as high as about 40 in tantalum oxide and about 200 to 500 in STO and BST, so that remarkable increase in the stored charge amount can be expected in the case of using the high (ferro) dielectric material as the dielectric film compared with the case of using silicon nitride (relative dielectric constant=7 to 8) as the dielectric film.

[0007] However, since such high (ferro) dielectric materials can not provide high relative dielectric constant by merely being formed as films and show large leak current in the films, it is necessary to improve crystallization and film quality by applying a heat treatment in an oxygen atmosphere at 750° C. or higher after film deposition. Accordingly, in the case of using the high (ferro) dielectric material for the dielectric film of the information storage capacitance device, the heat treatment at high temperature results in a problem of fluctuation in the characteristics of MISFET.

[0008] In view of the above, when the high (ferro) dielectric material is used for the dielectric film, a platinum group metal such as Ru (ruthenium), Pt (platinum) or Ir (iridium) is used for the lower electrode as the underlayer. When the high (ferro) dielectric film is deposited on the surface of the metal described above, since crystallization of film and improvement of the film quality can be obtained by a heat treatment at a low temperature such as 650° C. to 600° C. which is lower by 100° C. or more than the usual heat treatment, the amount of heat treatment in the entire manufacturing steps can be decreased to prevent fluctuation in the characteristics of MISFET.

[0009] On the other hand, when the platinum group metal as described above is used for the lower electrode material, since this is an easily oxygen permeable material, when a heat treatment is conducted in an oxygen atmosphere after deposition of a high (ferro) dielectric film on the surface of the lower electrode, oxygen permeates through the high (ferro) dielectric film and the lower electrode and the silicon plug therebelow to bring about a problem that the platinum metal and the silicon are reacted to form an undesired metal silicide layer at the boundary between both of them. As a countermeasure, it has been proposed to form a barrier layer for preventing reaction between them between the lower electrode comprising the platinum group metal and the silicon plug.

[0010] Japanese Published Unexamined Patent Application Hei 10(1998)-79481 proposes a conductive layer containing a high melting metal such as Ti (titanium), W (tungsten), Ta (tantalum), Co (cobalt) or Mo (molybdenum), silicon and nitrogen (metal silicon nitride layer) as a barrier layer for preventing a disadvantage that the platinum group metal and silicon diffuse to each other to form a metal silicide layer or, further, the metal silicide layer is oxidized to form a silicon oxide layer of low dielectric constant by a heat treatment at 700 to 800° C. upon reflow and flattening of a silicon oxide film. It is described that the barrier layer is preferably formed by lamination of a first layer containing columnar crystal or amorphous and a second layer containing granular crystals. Further, it is also described that a layer containing Ti is preferably formed between the barrier layer and the silicon plug for improving adhesion between them.

[0011] Japanese Published Unexamined Patent Application Hei 10(1998)-209394 points out a problem upon forming a lower electrode over a contact hole in which a silicon plug is buried that when mask misalignment is caused between them, the dielectric film formed over the lower electrode and the silicon plug below the lower electrode are in contact with each other to result in reaction between oxygen in the dielectric film and silicon to form a silicon oxide layer at high resistance, or the dielectric film lacks in oxygen to increase leak current. Then, this publication discloses a technique of providing a barrier film comprising silicon nitride between the dielectric film and the silicon plug as a countermeasure.

[0012] Japanese Published Unexamined Patent Application Hei 11(1999)-307736 concerns a ferroelectric memory and discloses a technique of forming a tantalum silicon nitride (TaSiN) film as a diffusion barrier layer over the silicon plug and forming an Ir film as an oxygen inhibition film over the diffusion barrier layer upon forming a capacitance device comprising a lower electrode comprising an iridium oxide (IrOx), a dielectric film comprising a dielectric material such as PZT (lead zirconate titanate) and an upper electrode comprising a platinum group metal such as Pt.

SUMMARY OF THE INVENTION

[0013] As described above, in the prior art, when a lower electrode comprising a platinum group metal is formed over a contact hole in which a silicon plug is buried and then a high (ferro) dielectric film is formed over the lower electrode and a heat treatment is conducted, undesired reaction between the platinum group metal and the silicon plug is prevented by previously forming a barrier layer over the silicon plug.

[0014] However, as the size of the memory cell is further refined, misalignment occurs inevitably between the lower electrode and the contact hole therebelow and the barrier layer in the contact hole may sometimes be etched upon patterning the lower electrode to expose the surface of the silicon plug. In this case, since a portion of the high (ferro) dielectric film formed over the lower electrode is in direct contact with the silicon plug, it results in a problem that the insulation break down voltage of the dielectric film is lowered to increase the leak current.

[0015] Further, as a result of the study made by the present inventors, it has been found a problem that when a barrier layer is formed over the silicon plug, and a heat treatment is conducted to the high (ferro) dielectric film in a high temperature oxygen atmosphere, oxygen permeating through the lower electrode oxidizes the barrier layer itself to form an oxide layer of high resistance and low dielectric constant.

[0016] Further, the present inventors have studied a process of depositing a thick silicon oxide film over a contact hole in which a silicon plug is buried, then etching the silicon oxide film to form a deep groove reaching the surface of the silicon plug and depositing a platinum group metal film on the inner wall of the groove to form a lower electrode, and have found a problem that peeling may sometimes be caused between the lower electrode and the silicon oxide film in the course of the production steps because of less adhesion between the platinum group metal film and the silicon oxide film.

[0017] This invention intends to provide a technique capable of preventing disadvantage that a barrier layer in the contact hole is etched to expose the surface of a silicon plug upon patterning a lower electrode, in a case where the size of the memory cell is further refined and misalignment occur inevitably between the lower electrode of a capacitance device and a contact hole therebelow.

[0018] This invention further intends to provide a technique capable of preventing disadvantage that an oxide layer of high resistance and low dielectric constant is formed upon heat treatment of a dielectric film formed over the lower electrode of a capacitance device in an oxygen atmosphere by the oxidation of the barrier layer itself with oxygen that permeates the lower electrode.

[0019] This invention further intends to provide a technique capable of improving adhesion between a platinum group metal film constituting the lower electrode for a capacitance device and a silicon oxide film.

[0020] This invention further provides a technique capable of ensuring a desired stored charge amount value even in a case of reducing the size of a memory cell, by increasing the surface area of a capacitance device and making the dielectric constant of the dielectric film higher.

[0021] The foregoing and other objects as well as novel features of this invention will become apparent by reading the descriptions of the present specification and appended drawings.

[0022] Among the inventions disclosed in this application, outlines of typical inventions are to be briefly explained as below.

[0023] In a semiconductor integrated circuit device according to this invention, a capacitance device constituted with a first electrode comprising a first metal, a dielectric film and a second electrode comprising a second metal is formed on a main surface of a semiconductor substrate, in which a first semiconductor region formed in the semiconductor substrate and the first electrode of the capacitance device are electrically connected by way of a silicon plug inside a first contact hole formed in a first insulating film over the first semiconductor region, and in which

[0024] a metal silicide layer is formed on the surface of the silicon plug, and at least one of a metal silicon nitride layer or a metal silicon oxynitride layer is formed on the surface of the metal silicide layer.

[0025] In a semiconductor integrated circuit device according to this invention, a capacitance device constituted with a first electrode comprising a first metal, a dielectric film and a second electrode comprising a second metal is formed on a main surface of a semiconductor substrate, in which a first semiconductor region formed in the semiconductor substrate and the first electrode of the capacitance device are electrically connected by way of a silicon plug inside a second contact hole formed in a second insulating film over the first semiconductor region, and a metal plug inside a first contact hole formed in a first insulating film over the second insulating film and in which

[0026] a metal silicide layer is formed on the surface of the silicon plug, and at least one of a metal silicon nitride layer or a metal silicon oxynitride layer is formed on the surface of the metal silicide layer.

[0027] A method of manufacturing a semiconductor integrated circuit device according to this invention include the following steps of:

[0028] (a) forming a first insulating film on a main surface of a semiconductor substrate formed with a first semiconductor region and then forming a first contact hole to the first insulating film over the first semiconductor region,

[0029] (b) forming a silicon plug inside the first contact hole,

[0030] (c) forming a third insulating film over the first insulating film, and then etching the third insulating film over the first contact hole, thereby forming a groove in which the surface of the silicon plug is exposed at the bottom thereof,

[0031] (d) forming a metal silicide layer on the surface of the silicon plug and then forming a metal silicon nitride layer on the surface of the metal silicide layer,

[0032] (e) forming a first electrode for the capacitance device comprising a first metal inside the groove, and electrically connecting the first electrode and the first semiconductor region through the first contact hole,

[0033] (f) forming a dielectric film for the capacitance device over the first electrode and then applying a heat treatment to the dielectric film in an oxygen-containing atmosphere, and

[0034] (g) forming a second electrode comprising a second metal for the capacitance device over the dielectric film.

[0035] A method of manufacturing a semiconductor integrated circuit device according to this invention include the following steps of:

[0036] (a) forming a second insulating film on a main surface of a semiconductor substrate formed with a first semiconductor region and then forming a second contact hole to the second insulating film over the first semiconductor region,

[0037] (b) forming a silicon plug in the second contact hole,

[0038] (c) forming a first insulating film over the second insulating film, and then etching the first insulating film over the second contact hole thereby forming a first contact hole in which the surface of the silicon plug is exposed at the bottom thereof,

[0039] (d) forming a metal silicide layer on the surface of the silicon plug and then forming a metal silicon nitride layer on the surface of the metal silicide layer,

[0040] (e) forming a metal plug inside the first contact hole,

[0041] (f) forming a third insulating film over the first insulating film and then etching the third insulating film over the first contact hole thereby forming a groove in which the surface of the metal plug is exposed at the bottom thereof,

[0042] (g) forming a first electrode comprising a first metal for a capacitance device inside the groove, and electrically connecting the first electrode and the first semiconductor region through the first contact hole and the second contact hole,

[0043] (h) forming a dielectric film for the capacitance device over the first electrode and then applying a heat treatment to the dielectric film in an oxygen-containing atmosphere, and

[0044] (i) forming a second electrode comprising a second metal for the capacitance device over the dielectric film.

[0045] A method of manufacturing a semiconductor integrated circuit device according to this invention include the following steps of:

[0046] (a) forming a first insulating film on a main surface of a semiconductor substrate formed with a first semiconductor region and then forming a first contact hole to the first insulating film over the first semiconductor region,

[0047] (b) forming a silicon plug in the first contact hole,

[0048] (c) forming a third insulating film over the first insulating film, and then etching the third insulating film over the first contact hole thereby forming a groove in which the surface of the silicon plug is exposed at the bottom thereof,

[0049] (d) forming a metal silicide layer on the surface of the silicon plug and then forming a metal silicon nitride layer on the surface of the metal silicide layer,

[0050] (e) a step forming a first metal film on the third insulating film including the inside of the groove thereby burying the first metal film inside the groove and then removing the first metal film outside of the groove,

[0051] (f) removing the third insulating film by etching to form a columnar first electrode comprising the columnar first metal for the capacitance device over the first contact hole and electrically connecting the first electrode and the first semiconductor region by way of the first contact hole,

[0052] (g) forming a dielectric film for the capacitance device over the first electrode and then applying a heat treatment to the dielectric film in an oxygen-containing atmosphere, and

[0053] (h) forming a second electrode comprising a second metal for the capacitance device over the dielectric film.

[0054] A method of manufacturing a semiconductor integrated circuit device according to this invention include the following steps of:

[0055] (a) forming a second insulating film on a main surface of a semiconductor substrate formed with a first semiconductor region and then forming a second contact hole to the second insulating film over the first semiconductor region,

[0056] (b) forming a silicon plug in the second contact hole,

[0057] (c) forming a first insulating film over the second insulating film, and then etching the first insulating film over the second contact hole thereby forming a first contact hole in which the surface of the silicon plug is exposed at the bottom of thereof,

[0058] (d) forming a metal silicide layer on the surface of the silicon plug and then forming a metal silicon nitride layer on the surface of the metal silicide layer,

[0059] (e) forming a metal plug inside the first contact hole,

[0060] (f) forming a third insulating film over the first insulating film and then etching the third insulating film over the first contact hole thereby forming a groove in which the surface of the metal plug is exposed at the bottom thereof,

[0061] (g) forming a first metal film on the third insulating film including the inside of the groove thereby burying the first metal film inside the groove and then removing the first metal film outside of the groove,

[0062] (h) etching to remove the third insulating film to form a columnar first electrode comprising the first metal film for capacitance device over the first contact hole, and electrically connecting the fist electrode and the first semiconductor region through the first contact hole and the second contact hole,

[0063] (i) forming a dielectric film for the capacitance device over the first electrode and then applying a heat treatment to the dielectric film in an oxygen-containing atmosphere, and

[0064] (j) forming a second electrode comprising a second metal for the capacitance device over the dielectric film.

BRIEF DESCRIPTION OF THE DRAWINGS

[0065] FIG. 1 is an entire plan view of a silicon chip formed with a DRAM as one embodiment according to this invention;

[0066] FIG. 2 is a cross sectional view for a main portion of a semiconductor substrate formed with a DRAM as one embodiment according to this invention;

[0067] FIG. 3 is a cross sectional view for a main portion of a semiconductor substrate formed with a DRAM as one embodiment according to this invention;

[0068] FIG. 4 is a plan view for a main portion of a semiconductor substrate formed with a DRAM as one embodiment according to this invention;

[0069] FIG. 5 is a cross sectional view for a main portion of a semiconductor substrate formed with a DRAM as one embodiment according to this invention;

[0070] FIG. 6 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0071] FIG. 7 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0072] FIG. 8 is a plan view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0073] FIG. 9 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0074] FIG. 10 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0075] FIG. 11 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0076] FIG. 12 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0077] FIG. 13 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0078] FIG. 14 is a plan view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0079] FIG. 15 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0080] FIG. 16 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0081] FIG. 17 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0082] FIG. 18 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0083] FIG. 19 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0084] FIG. 20 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0085] FIG. 21 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0086] FIG. 22 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0087] FIG. 23 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0088] FIG. 24 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0089] FIG. 25 is a plan view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0090] FIG. 26 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0091] FIG. 27 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0092] FIG. 28 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0093] FIG. 29 is a plan view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0094] FIG. 30 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0095] FIG. 31 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0096] FIG. 32 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0097] FIG. 33 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0098] FIG. 34 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0099] FIG. 35 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0100] FIG. 36 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0101] FIG. 37 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0102] FIG. 38 is a plan view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0103] FIG. 39 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0104] FIG. 40 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0105] FIG. 41 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0106] FIG. 42 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0107] FIG. 43 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0108] FIG. 44 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0109] FIG. 45 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0110] FIG. 46 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0111] FIG. 47 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0112] FIG. 48 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0113] FIG. 49 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0114] FIG. 50 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0115] FIG. 51 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0116] FIG. 52 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0117] FIG. 53 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0118] FIG. 54 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0119] FIG. 55 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0120] FIG. 56 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0121] FIG. 57 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0122] FIG. 58 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as one embodiment according to this invention;

[0123] FIG. 59 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0124] FIG. 60 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0125] FIG. 61 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0126] FIG. 62 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0127] FIG. 63 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0128] FIG. 64 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0129] FIG. 65 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0130] FIG. 66 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0131] FIG. 67 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0132] FIG. 68 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0133] FIG. 69 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0134] FIG. 70 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0135] FIG. 71 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0136] FIG. 72 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0137] FIG. 73 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0138] FIG. 74 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0139] FIG. 75 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0140] FIG. 76 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0141] FIG. 77 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0142] FIG. 78 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0143] FIG. 79 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0144] FIG. 80 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0145] FIG. 81 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0146] FIG. 82 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0147] FIG. 83 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0148] FIG. 84 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0149] FIG. 85 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0150] FIG. 86 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0151] FIG. 87 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0152] FIG. 88 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0153] FIG. 89 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0154] FIG. 90 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0155] FIG. 91 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0156] FIG. 92 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0157] FIG. 93 is a enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0158] FIG. 94 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0159] FIG. 95 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0160] FIG. 96 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0161] FIG. 97 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0162] FIG. 98 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0163] FIG. 99 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0164] FIG. 100 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0165] FIG. 101 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0166] FIG. 102 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0167] FIG. 103 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0168] FIG. 104 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0169] FIG. 105 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0170] FIG. 106 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0171] FIG. 107 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0172] FIG. 108 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0173] FIG. 109 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0174] FIG. 110 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0175] FIG. 111 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0176] FIG. 112 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0177] FIG. 113 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0178] FIG. 114 is a graph showing adhesion between an Ru film constituting a lower electrode and various kinds of underlayer materials;

[0179] FIG. 115 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0180] FIG. 116 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0181] FIG. 117 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0182] FIG. 118 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0183] FIG. 119 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0184] FIG. 120 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0185] FIG. 121 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0186] FIG. 122 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0187] FIG. 123 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0188] FIG. 124 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0189] FIG. 125 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0190] FIG. 126 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0191] FIG. 127 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0192] FIG. 128 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0193] FIG. 129 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0194] FIG. 130 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0195] FIG. 131 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0196] FIG. 132 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0197] FIG. 133 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0198] FIG. 134 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0199] FIG. 135 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0200] FIG. 136 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0201] FIG. 137 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0202] FIG. 138 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0203] FIG. 139 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0204] FIG. 140 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0205] FIG. 141 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0206] FIG. 142 is an enlarged cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention;

[0207] FIG. 143 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention; and

[0208] FIG. 144 is a cross sectional view for a main portion of a semiconductor substrate illustrating a process for manufacturing a DRAM as other embodiment according to this invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0209] This invention is to be described by way of preferred embodiments with reference to the drawings. In all of the drawings for explaining preferred embodiments, those members having identical functions carry identical reference numerals, for which duplicate explanations will be omitted.

[0210] FIG. 1 is an entire plan view of a silicon chip 1A formed with a DRAM of this embodiment (Embodiment 1). On a main surface of a rectangular silicon chip 1A, a DRAM having a memory capacity, for example, of 256 Mbit (megabit) to 1 Gbit (gigabit) is formed. The DRAM comprises a memory area divided into a plurality of memory arrays (MARY) and peripheral circuits arranged at the periphery of them. In a central area of the main surface of the silicon chip 1A are disposed word drivers WD, control circuits such as data line selection circuits, input/output circuits and bonding pads. Further, a sense amplifier SA is disposed between each of memory arrays (MARY).

[0211] The memory array (MARY) is constituted with a plurality of word lines and bit lines arranged in a matrix and a plurality of memory cells located at intersections of them. FIG. 2 and FIG. 3 are cross sectional views of a silicon substrate (hereinafter simply referred to as a substrate) 1 showing a portion of a DRAM memory array (MARY).

[0212] One memory cell for storing 1 bit information comprises one memory cell selecting MISFETQs formed in a p-well 2 of a substrate 1 and one information storage capacitance device (capacitor) C connected in series therewith. The memory cell selecting MISFETQs mainly comprises a gate electrode 6 (word line WL), source and drain (n-semiconductor region 8) and a gate insulating film 5 not illustrated in the drawings. One of the source and drain (n-semiconductor region 8) of the memory cell selecting MISFETQs is electrically connected with the information storage capacitance device C and the other of them is electrically connected with a bit line BL.

[0213] As shown in the drawings, the memory cell adopts a stacked capacitor structure of locating the information storage capacitance device C as a information storage capacitance section above the memory cell selecting MISFETQs. The information storage capacitance device C comprises a lower electrode (storage node) 28 comprising a metal containing Ru (ruthenium) as a main ingredient, a dielectric film 29 formed over the lower electrode 28 and containing Ta2O5 (tantalum oxide) as a main ingredient and an upper electrode (plate electrode) 30 comprising a metal containing TiN (titanium nitride) as a main ingredient. The information storage capacitance device C is formed in a groove 27 of a high aspect ratio formed in a silicon oxide film 24 of a large thickness over the memory cell selecting MISFETQs.

[0214] The lower electrode 28 of the information storage capacitance device C and one of the source and drain (n-semiconductor region 8) of the memory cell selecting MISFETQs are connected electrically by way of a contact hole 12 and a through hole 19 thereabove. Plugs 13 and 22 each comprising a polycrystal silicon film are buried, respectively, in the contact hole 12 and the through hole 19.

[0215] An Ru silicide layer 25 and an Ru silicon nitride layer 26 are formed at the boundary between the lower electrode 28 of the information storage capacitance device C and a plug 22 buried in the through hole 19 therebelow as a barrier layer for preventing the Ru constituting the lower electrode 28 and polycrystal silicon constituting the plug 22 from taking place a undesired silicide reaction by a heat treatment conducted in the course of a manufacturing step. The Ru silicon nitride layer 26 as a upper barrier layer is oxidized by the heat treatment applied in the course of the manufacturing step and at least a portion thereof is sometimes formed into silicon oxynitride.

[0216] Then, a process for manufacturing the DRAM in this embodiment is to be explained along the sequence of steps with reference to FIG. 4 to FIG. 58. In the manufacturing steps for the DRAM to be explained below, from the step of forming the memory cell selecting MISFETQs on the main surface of the substrate 1 to the step of successively forming bit lines BL on the memory cell selecting MISFETQs are described specifically, for example, in Japanese Published Unexamined Patent Application Hei 11(1999)-166320 (Matsuoka, et al). Accordingly, in this embodiment, only the outline is described for the steps up to the formation of the bit line BL and description is to be made in details for the manufacturing steps of the information storage capacitance device C as a main constituent portion. Further, the steps up to the formation of the bit line BL is not restricted to the steps to be described below.

[0217] At first, as shown in FIG. 4 (plan view for a main portion of a memory array), FIG. 5 (cross sectional view taken along line A-A in FIG. 4), FIG. 6 (cross sectional view taken along line B-B in FIG. 4) and FIG. 7 (cross sectional view taken along line C-C in FIG. 4), a device isolation groove 2 is formed in a device isolation region of the main surface of a substrate 1 comprising, for example, p-type single crystal silicon. The device isolation groove 2 is formed by etching the surface of the substrate 1 to form a groove of about 300 to 400 nm depth, successively depositing a silicon oxide film 4 (about 600 nm thickness) on the substrate 1 including the inside of the groove by a CVD (Chemical Vapor Deposition) method and then polishing and flattening the silicon oxide film 4 by a chemical mechanical polishing (CMP) method. The silicon oxide film 4 is deposited, for example, by a plasma CVD method using oxygen (or ozone) and tetraethoxy silane (TEOS) as a source gas and then dry-oxidized at about 1000° C. to densify the film.

[0218] As shown in FIG. 4, when the device isolation grooves 2 are formed, a number of elongate island-shape active regions (L) being surrounded at the periphery with the device isolation groove 2 are formed simultaneously. As will be described later, two memory cell selecting MISFETQs having one of source and drain in common are formed in each of the active regions (L).

[0219] Then, a p-well 3 is formed by ion implanting B (boron) to the substrate 1, successively, the surface of the p-well 3 is cleaned by an HF (hydrofluoric acid) type cleaning solution and then the substrate 1 is thermally oxidized to form a silicon oxide type clean gate insulating film 5 (about 6 nm thickness) on the surface of the active region (L) in the p-well 3. The gate insulating film 5 may be a silicon oxide insulating film formed by the thermal oxidation of the substrate 1, as well as a silicon nitride insulating film or a metal oxide insulating film (for example, tantalum oxide film or titanium oxide film) of a higher dielectric constant than the silicon oxide insulating film. The highly dielectric insulating film is formed by deposition on the substrate 1 by the CVD method or sputtering method.

[0220] Then, as shown in FIG. 8 to FIG. 10, a gate electrode 6 is formed over the gate insulating film 5. The gate electrode 6 functions as a word line (WL) in the region other than the active region (L). The gate electrode 6 (word line WL) is formed, for example, by depositing, an n-polycrystal silicon film (about 70 nm thickness) doped with P (phosphorus), a barrier metal film (about 5 nm to 10 nm thickness) comprising WN (tungsten nitride) or TiN (titanium nitride), a W (tungsten) film (about 100 nm thickness) and a silicon nitride film 7 (about 150 nm thickness) successively over the gate insulating film 5 and then dry etching the films using a photoresist film as a mask. The polycrystal silicon film and the silicon nitride film 7 are deposited by a CVD method and the barrier metal film and the W film are deposited by a sputtering method.

[0221] Then, as shown in FIG. 11 to FIG. 13, As (arsenic) or P (phosphorus) is ion implanted into the p-well 3 to form an n-semiconductor region 8 (source and drain) in the p-well 3 on both sides of the gate electrode 6. The memory cell selecting MISFETQs is substantially completed by the steps so far.

[0222] Then as shown in FIG. 14 to FIG. 17, after depositing a silicon nitride film 9 (50 nm thickness) and a silicon oxide film (about 600 nm thickness) by a CVD method on the substrate 1 and, successively, flattening the surface of the silicon oxide film 10 by a chemical mechanical polishing method, the silicon oxide film 10 and the silicon nitride film 9 are dry etched using a photoresist film (not illustrated) as a mask to form contact holes 11, 12 over the source and drain (n-semiconductor region 8) of the memory cell selecting MISFETQs. Etching for the silicon oxide film 10 is conducted under the condition with higher selectivity to silicon nitride while etching for the silicon nitride film 9 is conducted under the condition with higher selectivity to silicon or silicon oxide. Thus, the contact holes 11, 12 can be formed in self-alignment with the gate electrode 6 (word line WL).

[0223] Then, as shown in FIG. 18 and FIG. 19, plugs 13 are formed inside the contact holes 11 and 12. The plug 13 is formed by depositing a P-doped n-polycrystal silicon film over the silicon oxide film 10 by a CVD method to bury the n-polycrystal silicon film inside the contact holes 11 and 12 and then removing the n-polycrystal silicon film outside the contact holes 11 and 12 by the chemical mechanical polishing method (or dry etching).

[0224] Then, after depositing a silicon oxide film 14 (about 150 nm thickness) on the silicon oxide film 10 by a CVD method, as shown in FIG. 20 to FIG. 22, the silicon oxide film 14 over the contact hole 11 is dry etched using a photoresist film (not illustrated) as a mask to form a through hole 15 for connecting a bit line (BL) formed in the succeeding step and the contact hole 11.

[0225] Then, as shown in FIG. 23 and FIG. 24, a plug 16 is formed inside the through hole 15. The plug 16 is formed by depositing a barrier metal film comprising TiN over the silicon oxide film 14, for example, by a sputtering method, successively, depositing a W film over the barrier metal film by a CVD method to bury the films inside the through hole 15 and then removing the films outside the through hole 15 by a chemical mechanical polishing method.

[0226] Then, as shown in FIG. 25 to FIG. 28, a bit line BL is formed over the silicon oxide film 14. The bit line BL is formed, for example, by depositing a TiN film (about 10 nm thickness) over the silicon oxide film 14 by a sputtering method, successively, depositing a W film (about 50 nm thickness) over the TiN film by a CVD method and then dry etching the films using a photoresist film as a mask. The bit line BL is electrically connected with one of the source and drain (n-semiconductor region 8) of the memory cell selecting MISFETQs by way of the plug 16 buried in the through hole 15 therebelow and the plug 13 buried in the contact hole 11 further therebelow.

[0227] Then, as shown in FIG. 29 to FIG. 32, after depositing a silicon oxide film 17 of about 300 nm thickness over the bit line BL by a CVD method and, successively, flattening the surface by a chemical mechanical polishing method, the silicon oxide film 17 is dry etched using a photoresist film (not illustrated) as a mask to form a through hole 19 over the contact hole 11 in which the plug 13 is buried.

[0228] The through hole 19 is formed such that the diameter is smaller than the diameter of the contact hole 11 therebelow. Specifically, after depositing a polycrystal silicon film 20 by a CVD method over the silicon oxide film 17 and, successively, dry etching the polycrystal silicon film 20 in the region forming the through hole 19 to form a hole, a polycrystal silicon film (not illustrated) is further deposited on the polycrystal silicon film 20. Then, the polycrystal silicon film over the polycrystal silicon film 20 is anisotropically etched to form a side wall spacer 21 on the side wall of the hole and, successively, the silicon oxide film 17 at the bottom of the hole is dry etched by using the polycrystal silicon film 20 and the side wall spacer 21 as a mask.

[0229] Further, as shown in FIG. 29 and FIG. 32, the through hole 19 is offset such that the center thereof is deviated from the center for the contact hole 11 in the direction away from the bit line BL. Since the diameter for the through hole 19 is made smaller than the diameter for the contact hole therebelow, and the center of the through hole is offset in the direction away aparting from the bit line BL, short circuit between the through hole 19 (plug 22 buried in the inside thereof) and the bit line BL can be prevented without using the technique of the self-aligned contact (SAC) also in a case of reducing the memory cell size. Further, since the diameter for the through hole 19 is made smaller than the diameter for the contact hole 11, contact area between both of them can be ensured even when the centers thereof are displaced from each other.

[0230] Then, after removing the mask used for forming the through hole 19 (polycrystal silicon film 20 and the side wall spacer 21) by dry etching, as shown in FIG. 33 to FIG. 35, a plug 22 is formed inside the through hole 19. The plug 22 is formed by at first depositing a P-doped n-polycrystal silicon film over the silicon oxide film 17 by a CVD method to bury the n-polycrystal silicon film inside the through hole 19 and, successively, removing the n-polycrystal silicon film outside the through hole 19 by a chemical mechanical polishing method (or dry etching).

[0231] Then, as shown in FIG. 36 and FIG. 37, after depositing a silicon nitride film 18 over the silicon oxide film 17 by a CVD method, a silicon oxide film 24 is deposited over the silicon nitride film 18 by a CVD method. A lower electrode 28 of the information storage capacitance device C is formed inside the groove 27 formed in the silicon oxide film 24 in the succeeding step. Accordingly, since the thickness of the silicon oxide film 24 defines the height for the lower electrode 28, the silicon oxide film 24 is deposited at a large thickness (about 0.8 μm or more) for increasing the stored static charge quantity by increasing the surface area of the lower electrode 28. The silicon oxide film 24 is deposited, for example, by a plasma CVD method using oxygen and tetraethoxy silane (TEOS) as a source gas and then the surface thereof is flattened optionally by a chemical mechanical polishing method.

[0232] Then, as shown in FIG. 38 to FIG. 40, the silicon oxide film 24 is dry etched using a photoresist film (not illustrated) as a mask and then, successively, the silicon nitride film 18 under the silicon oxide film 24 is dry etched to form a groove 27 in which the surface of the plug 22 in the through hole 19 is exposed at the bottom. As shown in FIG. 38, the groove 27 is constituted as a rectangular planer pattern having a longer side in the extending direction of the word line WL and a shorter side in the extending direction of the bit line BL.

[0233] The groove 27 can be formed also by the following method. At first, after depositing the silicon nitride film 18 and the silicon nitride film 24 of a large thickness successively over the silicon oxide film 17 and then depositing a silicon nitride film (not illustrated) over the silicon oxide film 24 by a CVD method, the silicon nitride film is dry etched by using a photoresist film as a mask. Then, after removing the photoresist film, the silicon oxide film 24 is dry etched by using the silicon nitride film as a mask and, further, the silicon nitride film 18 is dry etched to form a groove 27.

[0234] Then, as shown in FIG. 41 and FIG. 42, an Ru film 23 is deposited by a sputtering method over the silicon oxide film 24 in which the deep groove 27 is formed. The Ru film 23 is deposited at such a thin thickness that the thickness is about 50 nm at the bottom of the groove 27. Generally, since the film deposited by a sputtering method has lower step coverage compared with the film deposited by a CVD method, the Ru film 23 is less deposited on the side wall of the deep groove 27. FIG. 41 and FIG. 42 show a state where the Ru film 23 is deposited over the silicon oxide film 24 and at the bottom of the groove 27, but an extremely thin film (not illustrated) is deposited actually also on the side wall of the groove 27. The thin film deposited on the side wall of the groove 27 has an effect of improving the adhesion of a CVD-Ru film (Ru film 28a) deposited inside the groove 27 in the subsequent step.

[0235] Then, as shown in FIG. 43 and FIG. 44 heat treatment is conducted at about 700° C. for one min in a non-oxidative gas atmosphere such as nitrogen, to react the Ru film 23 at the bottom of the groove 27 and the plug 22 therebelow comprising polycrystal silicon to form an Ru silicide layer 25 on the surface of the plug 22. In this case, since the Ru film 23 over the silicon oxide film 24 causes no silicide reaction, it remains as it is.

[0236] The Ru silicide layer 25 is formed for preventing occurrence of undesired siliciding reaction at the boundary between Ru constituting the lower electrode 28 and the polycrystal silicon constituting the plug 22 and reducing the contact resistance upon heat treatment conducted in the subsequent step, for example, a high temperature heat treatment conducted in the dielectric film forming step for the information storage capacitance device C to be described later.

[0237] Then, as shown in FIG. 45 and FIG. 46, an Ru silicon nitride layer 26 is formed by conducting a heat treatment at about 650° C. for 3 min in an ammonia gas atmosphere to nitride the surface of the Ru silicide 25. The thickness of the Ru silicon nitride layer 26 formed under the heat treatment conditions described above is extremely thin and it was within a range from 0.5 nm to 1.0 nm as a result of observation made by the present inventors by a transmission electron microscope.

[0238] The thickness of the Ru silicon nitride layer 26 can be controlled by varying the heat treatment condition described above. That is, when the surface of the polycrystal silicon (plug 22) is nitrided in the ammonia gas atmosphere, the nitriding reaction starts at about 550° C. and the reaction proceeds rapidly as the temperature goes higher. Since the feature of the nitriding reaction resides in that the reaction stops in a self-alignment manner, it has a merit that the thickness of the Ru silicon nitride layer 26 can be controlled at an extremely high accuracy.

[0239] It may be considered that the Ru silicon nitride layer 26 is formed by depositing a silicon nitride film over the Ru silicide layer 25 by a CVD method and reacting both of them by a heat treatment. However, it is difficult by the method to form an extremely thin film of about 1 nm at a good controllability. In the heat treatment in the ammonia gas atmosphere (thermal nitridation method), the thickness of the film formed is utmost about 2 nm even when the heat treatment is conducted at a high temperature of about 1000° C., which scarcely depends on the treating time. When the treating time is one min or more, the film thickness can substantially be controlled only by setting the temperature. The thermal nitridation method proceeds such that a nitriding agent diffuses in the formed film and reaches the silicon surface to form a nitrided film. Since the nitride film is extremely dense, the formed film itself has a function of inhibiting the diffusion of the nitriding agent. Accordingly, this is a method which is extremely advantageous for forming the Ru silicon nitride layer 26 of a thin film thickness as described above although it can not form a thick film.

[0240] The Ru silicon nitride layer 26 may be formed also by a nitriding treatment utilizing active nitrogen formed in a plasma atmosphere (plasma nitriding method) instead of the thermal nitriding method described above. The principle of forming the nitride film in the plasma nitriding method is identical with that in the thermal nitriding method but this method has an advantage capable of forming a film at a lower temperature since active nitrogen in plasmas is used as the nitriding agent and a nitride film, for example, of about 1 nm thickness can be formed at a temperature within a range from 300° C. to 400° C.

[0241] As described above, in this embodiment, the Ru silicide layer 25 and the Ru silicon nitride layer 26 are formed on the surface of the plug 22 as a barrier layer for preventing occurrence of undesired siliciding reaction between Ru constituting the lower electrode 28 for the information storage capacitance device C and the polycrystal silicon constituting the plug 22. The Ru silicon nitride layer 26 has a function of preventing disadvantage that an oxidizer (oxygen) diffusing in the dielectric film 29 and in the lower electrode 28 oxidizes the surface of the Ru silicide layer 25, to form a silicon oxide film (Ru silicon oxide layer) of lower dielectric constant or, in an extremely case, resul