[0001] This application claims benefit of U.S. Provisional Patent Application Serial No. 60/346,086, filed on Oct. 26, 2001, and entitled “Method and Apparatus for ALD Deposition”, which is incorporated by reference herein. This application also claims benefit of U.S. patent application Ser. No. 09/965,370, filed on Sep. 26, 2001, and entitled “Integration of Barrier Layer and Seed Layer”, which is incorporated by reference herein. This application also claims benefit of U.S. patent application Ser. No. 09/965,373, filed on Sep. 26, 2001, and entitled “Integration of Barrier Layer and Seed Layer”, which is incorporated by reference herein. This application also claims benefit of U.S. patent application Ser. No. 09/965,369, filed on Sep. 26, 2001, and entitled “Integration of Barrier Layer and Seed Layer”, which is incorporated by reference herein.
[0002] 1. Field of the Invention
[0003] Embodiments of the present invention relate to a method for manufacturing integrated circuit devices. More particularly, embodiments of the invention relate to forming metal interconnect structures using one or more cyclical deposition processes.
[0004] 2. Description of the Related Art
[0005] As the structure size of integrated circuit (IC) devices is scaled down to sub-quarter micron dimensions, electrical resistance and current densities have become an area for concern and improvement. Multilevel interconnect technology provides the conductive paths throughout an IC device, and are formed in high aspect ratio features, including contacts, plugs, vias, lines, wires, and other features. A typical process for forming an interconnect on a substrate includes depositing one or more layers, etching at least one of the layer(s) to form one or more features, depositing a barrier layer in the feature(s) and depositing one or more layers to fill the feature. Typically, a feature is formed within a dielectric material disposed between a lower conductive layer and an upper conductive layer. The interconnect is formed within the feature to link the upper and lower conductive layers. Reliable formation of these interconnect features is important to the production of the circuits and continued effort to increase circuit density and quality on individual substrates and die.
[0006] Copper has recently become a choice metal for filling sub-micron high aspect ratio, interconnect features because copper and its alloys have lower resistivities than aluminum. However, copper diffuses more readily into surrounding materials and can alter the electronic device characteristics of the adjacent layers and, for example, form a conductive path between layers, thereby reducing the reliability of the overall circuit and may even result in device failure.
[0007] Barrier layers therefore, are deposited prior to copper metallization to prevent or impede the diffusion of copper atoms. Barrier layers typically contain of a refractory metal such as tungsten, titanium, tantalum, and nitrides thereof, which all have a greater resistivity than copper. To deposit a barrier layer within a feature, the barrier layer must be deposited on the bottom of the feature as well as the sidewalls thereof. Therefore, the additional amount of the barrier layer on the bottom of the feature not only increases the overall resistance of the feature, but also forms an obstruction between higher and lower metal interconnects of a multi-layered interconnect structure.
[0008] There is a need, therefore, for an improved method for forming metal interconnect structures which minimizes the electrical resistance of the interconnect.
[0009] A method for forming a metal interconnect on a substrate is provided. In one aspect, the method includes a refractory metal containing a barrier layer having a thickness that exhibits a crystalline like structure and is sufficient to inhibit atomic migration over at least a portion of a metal layer by alternately introducing one or more pulses of a metal-containing compound and one or more pulses of a nitrogen-containing compound; depositing a seed layer on at least a portion of the barrier layer; and depositing a second metal layer on at least a portion of the seed layer.
[0010] In another aspect, the method includes depositing a tantalum nitride barrier layer having a thickness less than about 20 angstroms over at least a portion of a metal layer by alternately introducing one or more pulses of a tantalum-containing compound and one or more pulses of a nitrogen-containing compound; depositing an alloy seed layer on the barrier layer; and depositing a second metal layer. The alloy seed layer may contain a dual alloy such as copper and a metal selected from the group consisting of aluminum, magnesium, titanium, zirconium, tin, and combinations thereof. The second metal layer may be formed using physical vapor deposition (CVD), physical vapor deposition (PVD), electroplating, or electroless techniques.
[0011] In still another aspect, the method includes depositing a titanium silicon nitride layer having a thickness less than about 20 angstroms over at least a portion of a metal layer by alternately introducing one or more pulses of a titanium-containing compound, one or more pulses of a silicon-containing compound, and one or more pulses of a nitrogen-containing compound; depositing a dual alloy seed layer; and depositing a second metal layer on the seed layer.
[0012] In still another aspect, the method includes depositing a tantalum silicon nitride layer having a thickness less than about 20 angstroms over at least a portion of the first metal layer by alternately introducing one or more pulses of a tantalum-containing compound, one or more pulses of a silicon-containing compound, and one or more pulses of a nitrogen-containing compound; depositing a dual alloy seed layer; and depositing a second metal layer on the seed layer.
[0013] In yet another aspect, the method includes depositing a bilayer barrier having a thickness less than about 20 angstroms over at least a portion of the first metal layer. The bilayer barrier includes a first layer of tantalum nitride deposited by alternately introducing one or more pulses of a tantalum-containing compound and one or more pulses of a nitrogen-containing compound; and a second layer of alpha phase tantalum. The method further includes depositing a dual alloy seed layer and a second metal layer on the seed layer.
[0014] In another aspect, the method includes depositing a tantalum nitride barrier layer having a thickness less than about 20 angstroms over at least a portion of the first metal layer by alternately introducing one or more pulses of a tantalum-containing compound and one or more pulses of a nitrogen-containing compound; depositing a dual alloy seed layer comprising copper and a metal selected from the group consisting of aluminum, magnesium, titanium, zirconium, tin, and combinations thereof; and depositing a second metal layer on the seed layer by physical vapor deposition (CVD), physical vapor deposition (PVD), electroplating, or electroless techniques.
[0015] So that the manner in which the above recited features of the present invention are attained and can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to the embodiments thereof which are illustrated in the appended drawings.
[0016] It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
[0017]
[0018] FIGS.
[0019]
[0020]
[0021] A process sequence for forming one or more interconnect structures is provided. Interconnect structures formed according to embodiments described herein have an overall lower resistivity and better electrical properties than interconnects of the prior art, and are particularly useful for making memory and logic structures for use with the fabrication of integrated circuits. The formation of the interconnect structures includes the formation of a thin barrier layer at least partially deposited on an underlying metal layer, a seed layer at least partially deposited on the barrier layer, and a bulk metal layer at least partially deposited on the seed layer. The term “interconnect” as used herein refers to any conductive path formed within an integrated circuit. The term “bulk” as used herein refers to a greater amount of material deposited in relation to other materials deposited to form the interconnect structure.
[0022]
[0023] A “thin layer” as used herein refers to a layer of material deposited on a substrate surface having a thickness of about 20 angstroms (Å) or less, such as about 10 Å. The thickness of the barrier layer is so small/thin that electrons of the adjacent metal interconnects can tunnel through the barrier layer. Accordingly, the barrier layer significantly enhances the metal interconnect electrical performance by lowering the overall electrical resistance and providing good device reliability.
[0024] The thin barrier layer deposited according to the cyclical deposition methods described herein shows evidence of an epitaxial growth phenomenon. In other words, the barrier layer takes on the same or substantially the same crystallographic characteristics as the underlying layer. As a result, a substantially single crystal is grown such that there is no void formation at an interface between the barrier layer and the underlying layer. Likewise, subsequent metal layers deposited over the barrier layer exhibit the same or substantially the same epitaxial growth characteristics that continue the formation of the single crystal. Accordingly, no void formation is produced at this interface. The resulting structure resembling a single crystal eliminates voids formation, thereby substantially increasing device reliability. The single crystal structure also reduces the overall resistance of the interconnect feature while still providing excellent barrier properties. Furthermore, it is believed that the single crystalline growth reduces the susceptibility of electromigration and stress migration due to the conformal and uniform crystalline orientation across the interconnect material interfaces.
[0025] “Cyclical deposition” as used herein refers to the sequential introduction of two or more compounds to deposit a thin layer on a substrate surface. The two or more compounds are sequentially introduced into a reaction zone of a processing chamber. Each compound is separated by a time delay/pause to allow each compound to adhere and/or react on the substrate surface. In one aspect, a first compound or compound A is dosed/pulsed into the reaction zone followed by a first time delay/pause. Next, a second compound or compound B is dosed/pulsed into the reaction zone followed by a second time delay. When a ternary material is desired, such as titanium silicon nitride, for example, a third compound (C), is dosed/pulsed into the reaction zone followed by a third time delay. These sequential tandems of a pulse of reactive compound followed by a time delay may be repeated indefinitely until a desired film or film thickness is formed on the substrate surface.
[0026] A “pulse/dose” as used herein is intended to refer to a quantity of a particular compound that is intermittently or non-continuously introduced into a reaction zone of a processing chamber. The quantity of a particular compound within each pulse may vary over time, depending on the duration of the pulse. A particular compound may include a single compound or a mixture/combination of two or more compounds.
[0027] A “compound” is intended to include one or more precursors, reductants, reactants, and catalysts. Each compound may be a single compound or a mixture/combination of two or more compounds.
[0028] Still referring to
[0029] The bulk metal layer is at least partially deposited on the seed layer, as shown at step
[0030] FIGS.
[0031] Referring to
[0032] Referring to
[0033] It is to be understood that these compounds or any other compound not listed above may be a solid, liquid, or gas at room temperature. For example, PDMAT is a solid at room temperature and TBTDET is a liquid at room temperature. Accordingly, the non-gas phase precursors are subjected to a sublimation or vaporization step, which are both well known in the art, prior to introduction into the processing chamber. A carrier gas, such as argon, helium, nitrogen, hydrogen, or a mixture thereof, may also be used to help deliver the compound into the processing chamber, as is commonly known in the art.
[0034] Each pulse is performed sequentially, and is accompanied by a separate flow of non-reactive gas at a rate between about 200 sccm and about 1,000 sccm. The separate flow of non-reactive gas may be pulsed between each pulse of the reactive compounds or the separate flow of non-reactive gas may be introduced continuously throughout the deposition process. The separate flow of non-reactive gas, whether pulsed or continuous, serves to remove any excess reactants from the reaction zone to prevent unwanted gas phase reactions of the reactive compounds, and also serves to remove any reaction by-products from the processing chamber, similar to a purge gas. In addition to these services, the continuous separate flow of non-reactive gas helps deliver the pulses of reactive compounds to the substrate surface similar to a carrier gas. The term “non-reactive gas” as used herein refers to a single gas or a mixture of gases that does not participate in the metal layer formation. Exemplary non-reactive gases include argon, helium, nitrogen, hydrogen, and combinations thereof.
[0035] A “reaction zone” is intended to include any volume that is in fluid communication with a substrate surface being processed. The reaction zone may include any volume within a processing chamber that is between a gas source and the substrate surface. For example, the reaction zone includes any volume downstream of a dosing valve in which a substrate is disposed.
[0036] The durations for each pulse/dose are variable and may be adjusted to accommodate, for example, the volume capacity of the processing chamber as well as the capabilities of a vacuum system coupled thereto. Additionally, the dose time of a compound may vary according to the flow rate of the compound, the pressure of the compound, the temperature of the compound, the type of dosing valve, the type of control system employed, as well as the ability of the compound to adsorb onto the substrate surface. Dose times may also vary based upon the type of layer being formed and the geometry of the device being formed.
[0037] Typically, the duration for each pulse/dose or “dose time” is typically about 1.0 second or less. However, a dose time can range from microseconds to milliseconds to seconds, and even to minutes. In general, a dose time should be long enough to provide a volume of compound sufficient to adsorb/chemisorb onto the entire surface of the substrate and form a layer of the compound thereon.
[0038]
[0039] The processing chamber
[0040] Referring to
[0041] A gas delivery apparatus
[0042] The gas delivery apparatus
[0043] The gas delivery apparatus
[0044] The valves
[0045] To facilitate the control and automation of the overall system, the integrated processing system may include a controller
[0046] In a particular embodiment, a TaN barrier layer is formed by cyclically introducing PDMAT and ammonia to the substrate surface. To initiate the cyclical deposition of the TaN layer, a carrier/inert gas such as argon is introduced into the processing chamber
[0047] A pause between pulses of PDMAT and ammonia is about 1.0 second or less, preferably about 0.5 seconds or less, more preferably about 0.1 seconds or less. In various aspects, a reduction in time between pulses at least provides higher throughput. As a result, a pause after the pulse of ammonia is also about 1.0 second or less, about 0.5 seconds or less, or about 0.1 seconds or less. Argon gas flowing between about 100 sccm and about 1000 sccm, such as between about 100 sccm and about 400 sccm, is continuously provided from the gas source
[0048] The heater temperature is maintained between about 100° C. and about 300° C. at a chamber pressure between about 1.0 and about 5.0 Torr. Each cycle consisting of a pulse of PDMAT, pause, pulse of ammonia, and pause provides a tantalum nitride layer having a thickness between about 0.3 Å and about 1.0 Å per cycle. The alternating sequence may be repeated until the desired thickness is achieved, which is less than about 20 Å, such as about 10 Å. Accordingly, the deposition method requires between 10 and 70 cycles, more typically between 20 and 30 cycles.
[0049] In another aspect, a ternary barrier layer having a thickness less than about 20 Å, such as 10 Å, is deposited by providing one or more pulses of a refractory metal-containing compound, one or more pulses of a nitrogen-containing compound, and one or more pulses of a silicon-containing compound. Each pulse is adjusted to provide a desirable composition, silicon incorporation level, thickness, density, and step coverage of the refractory metal silicon nitride layer. A “ternary barrier layer” as used herein refers to a material having a composition comprising three major elements, such as titanium, nitrogen and silicon. An exemplary “ternary barrier layer” may also include tantalum, nitrogen and silicon.
[0050] Each pulse is performed sequentially, and is accompanied by a separate flow of carrier/inert gas at the same process conditions described above. The separate flow of carrier/inert gas may be pulsed between each pulse of reactive compound or the separate flow of carrier/inert gas may be introduced continuously throughout the deposition process.
[0051] Preferably, the ternary barrier layer contains titanium silicon nitride. In this embodiment, each cycle consists of a pulse of a titanium-containing compound, a pause, a pulse of a silicon-containing compound, a pause, a pulse of a nitrogen-containing compound, and a pause. Exemplary titanium-containing compound include tetrakis (dimethylamino) titanium (TDMAT), tetrakis (ethylmethylamino) titanium (TEMAT), tetrakis (diethylamino) titanium (TDEAT), titanium tetrachloride (TiCl
[0052] To initiate the cyclical deposition of a Ti
[0053] A pause between pulses of TDMAT and silane is about 1.0 second or less, preferably about 0.5 seconds or less, more preferably about 0.1 seconds or less. A pause between pulses of silane and ammonia is about 1.0 second or less, about 0.5 seconds or less, or about 0.1 seconds or less. A pause after the pulse of ammonia is also about 1.0 second or less, about 0.5 seconds or less, or about 0.1 seconds or less. In one aspect, a pulse of TDMAT may still be in the chamber when a pulse of silane enters, and a pulse of silane may still be in the chamber when a pulse of ammonia enters.
[0054] The heater temperature is maintained between about 100° C. and about 300° C. at a chamber pressure between about 1.0 and about 5.0 Torr. Each cycle consisting of a pulse of TDMAT, pause, pulse of silane, pause, pulse of ammonia, and pause provides a titanium silicon nitride layer having a thickness between about 0.3 Å and about 1.0 Å per cycle. The alternating sequence may be repeated until the desired thickness is achieved, which is less than about 20 Å, such as about 10 Å. Accordingly, the deposition method requires between 10 and 70 cycles.
[0055] In yet another aspect, an alpha phase tantalum (α-Ta) layer having a thickness of about 20 Å or less, such as about 10 Å, may be deposited over at least a portion of the previously deposited binary (TaN) or ternary (TiSiN) layers. The α-Ta layer may be deposited using conventional techniques, such as PVD and CVD for example, to form a bilayer stack. For example, the bilayer stack may include a TaN portion deposited by cyclical layer deposition described above and an α-Ta portion deposited by high density plasma physical vapor deposition (HDP-PVD).
[0056] To further illustrate, the α-Ta portion of the stack may be deposited using an ionized metal plasma (IMP) chamber, such as a Vectra™ chamber, available from Applied Materials, Inc. of Santa Clara, Calif. The IMP chamber includes a target, coil, and biased substrate support member, and may also be integrated into an Endura™ platform, also available from Applied Materials, Inc. A power between about 0.5 kW and about 5 kW is applied to the target, and a power between about 0.5 kW and 3 kW is applied to the coil. A power between about 200 W and about 500 W at a frequency of about 13.56 MHz is also applied to the substrate support member to bias the substrate. Argon is flowed into the chamber at a rate of about 35 sccm to about 85 sccm, and nitrogen may be added to the chamber at a rate of about 5 sccm to about 100 sccm. The pressure of the chamber is typically between about 5 mTorr to about 100 mTorr, while the temperature of the chamber is between about 20° C. and about 300° C.
[0057] Prior to depositing the barrier layer
[0058] In one aspect, the reactive pre-clean process forms radicals from a plasma of one or more reactive gases such as argon, helium, hydrogen, nitrogen, fluorine-containing compounds, and combinations thereof. For example, a reactive gas may include a mixture of tetrafluorocarbon (CF
[0059] Following the argon plasma, the chamber pressure is increased to about 140 mTorr, and a processing gas consisting essentially of hydrogen and helium is introduced into the processing region. Preferably, the processing gas comprises about 5% hydrogen and about 95% helium. The hydrogen plasma is generated by applying between about 50 watts and about 500 watts power. The hydrogen plasma is maintained for about 10 seconds to about 300 seconds.
[0060] Referring again to
[0061] A typical SIP™ chamber includes a target, coil, and biased substrate support member. To form the copper seed layer, a power between about 0.5 kW and about 5 kW is applied to the target, and a power between about 0.5 kW and 3 kW is applied to the coil. A power between about 200 and about 500 W at a frequency of about 13.56 MHz is applied to bias the substrate. Argon is flowed into the chamber at a rate of about 35 sccm to about 85 sccm, and nitrogen may be added to the chamber at a rate of about 5 sccm to about 100 sccm. The pressure of the chamber is typically between about 5 mTorr to about 100 mTorr.
[0062] Alternatively, a seed layer
[0063] Referring to
[0064] A copper electrolyte solution and copper electroplating technique is described in commonly assigned U.S. Pat. No. 6,113,771, entitled “Electro-deposition Chemistry”, which is incorporated by reference herein. Typically, the electroplating bath has a copper concentration greater than about 0.7M, a copper sulfate concentration of about 0.85, and a pH of about 1.75. The electroplating bath may also contain various additives as is well known in the art. The temperature of the bath is between about 15° C. and about 25° C. The bias is between about −15 volts to about 15 volts. In one aspect, the positive bias ranges from about 0.1 volts to about 10 volts and the negatives bias ranges from about −0.1 to about −10 volts.
[0065] Optionally, an anneal treatment may be performed following the metal layer
[0066] Following deposition, the top portion of the resulting structure may be planarized. A chemical mechanical polishing (CMP) apparatus may be used, such as the Mirra™ System available from Applied Materials, Santa Clara, Calif., for example. Optionally, the intermediate surfaces of the structure may be planarized between the deposition of the subsequent layers described above.
[0067]
[0068] The system
[0069] The transfer chambers
[0070] In one arrangement, each processing chamber
[0071] The following example is intended to provide a non-limiting illustration of one embodiment of the present invention.
[0072] A TaN layer was deposited over a lower level copper layer using cyclical deposition to a thickness of about 20 Å. A copper alloy seed layer was deposited over the TaN layer by physical vapor deposition to a thickness of about 100 Å. The copper alloy seed layer contained aluminum in a concentration of about 2.0 atomic percent, and was deposited by PVD using a copper-aluminum target consisting of aluminum in a concentration of about 2.0 atomic percent. A bulk copper layer was then deposited using ECP to fill the feature. The substrate was then annealed at a temperature of about 380° C. for a time period of about 15 minutes in a nitrogen (N2) and hydrogen (H2) ambient.
[0073] The overall feature resistance was significantly reduced and the upper level copper layer surprisingly exhibited a grain growth similar to that of the lower level copper layer. The barrier performance of the TaN layer exhibited longer TTF compared with 50 Å PVD Ta. Further, the TaN layer showed low contact resistance and tight spread distribution. The TaN layer also exhibited excellent topography, having a smooth and pinhole free surface. Finally, the copper alloy seed layer showed excellent adhesion/wetting to the TaN layer.
[0074] While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.