DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] In the following detailed description of the invention, reference is made to the accompanying drawings which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The terms wafer and substrate used in the following description include any structure having an exposed surface with which to form the integrated circuit (IC) structure of the invention. The term substrate is understood to include semiconductor wafers. The term substrate is also used to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon. Both wafer and substrate include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art. The term conductor is understood to include semiconductors, and the term insulator or dielectric is defined to include any material that is less electrically conductive than the materials referred to as conductors.

[0028] The term “horizontal” as used in this application is defined as a plane parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term “vertical” refers to a direction perpendicular to the horizonal as defined above. Prepositions, such as “on”, “side” (as in “sidewall”), “higher”, “lower”, “over” and “under” are defined with respect to the conventional plane or surface being on the top surface of the wafer or substrate, regardless of the orientation of the wafer or substrate. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.

[0029] FIG. 3 a shows an electron beam evaporation technique to deposit a material on a surface such as a body region of a transistor. In FIG. 3 a , a substrate 310 is placed inside a deposition chamber 300 . The substrate in this embodiment is masked by a first masking structure 312 and a second masking structure 314 . In this embodiment, the unmasked region 316 includes a body region of a transistor, however one skilled in the art will recognize that other semiconductor device structures may utilize this process. Also located within the deposition chamber 300 is an electron beam source 330 , and a target material 334 . Although in this embodiment, an electron beam evaporation technique is used, it will be apparent to one skilled in the art that other thermal evaporation techniques can be used without departing from the scope of the invention. During the evaporation process, the electron beam source 330 generates an electron beam 332 . The electron beam hits the target material 334 and heats a portion of the target material enough to cause the surface of the target material to evaporate. The evaporated material 336 is then distributed throughout the chamber 300 , and the material 336 deposits on surfaces that it contacts, such as the exposed body region 316 . The depositing material builds up to form a layer 320 of material that is chemically the same as the target material 334 .

[0030] In one embodiment of the invention, the deposited material layer 320 includes a pure metal layer chosen from the alkaline earth metals in group IVB of the periodic table. In one embodiment of the invention, the deposited material layer 320 includes zirconium (Zr). In one embodiment of the invention, the target material is a 99.9999% pure slug of zirconium. The choice of material is based on the properties of the oxide formed. Considerations included the thermodynamic stability of the oxide with silicon, the diffusion coefficient of the oxide at high processing temperatures such as 1000° K., the lattice match of the oxide with silicon, the dielectric constant of the oxide, and the conduction band offset of the oxide. In one embodiment, the conduction band offset of the metal oxide formed is in a range of approximately 5.16 eV to 7.8 eV. In one embodiment, the deposited material layer 320 is substantially amorphous. A lower presence of grain boundaries in the substantially amorphous material layer 320 reduces the leakage current through the final gate oxide. Although the amorphous form is preferred, the material chosen for oxidation, such as zirconium is also acceptable in its crystalline form.

[0031] A thermal evaporation process such as the electron beam evaporation technique described above does not cause the surface damage that is inherent in other deposition techniques such as the sputtering technique shown in FIG. 2 b . This allows a very thin layer of material to be deposited on a body region of a transistor, while maintaining a smooth interface. A thermal evaporation process such as the electron beam evaporation technique described above also allows low processing temperatures that inhibit the formation of unwanted byproducts such as suicides and oxides. In one embodiment, the thermal evaporation is performed with a substrate temperature between approximately 150 and 200° C.

[0032] FIG. 3 b shows a magnified view of the body region 316 and the deposited layer 320 from FIG. 3 a . The interface 340 is shown with a roughness variation 346 . The deposited layer surface 348 is also shown with a similar surface roughness. One possible surface variation 346 would be an atomic layer variation. In atomic smoothness, the greatest difference in surface features is between a first atomic layer as indicated by layer 342 and a second atomic layer 344 . The thermal evaporation deposition technique described above preserves atomic smoothness such as is shown in FIG. 3 b , however other acceptable levels of surface roughness greater than atomic smoothness will also be reserved by the thermal evaporation technique.

[0033] FIGS. 4 a - 4 c show a low temperature oxidation process that is used in one embodiment to convert the deposited layer 320 into a gate oxide. A deposited material layer 410 is shown in FIG. 4 a on a substrate surface 400 . The layer 410 forms an interface 420 with the substrate surface 400 , and the layer 410 has an outer surface 430 . The layer 410 in this embodiment is deposited over a body region of a transistor, however the layer may be deposited on any surface within the scope of the invention.

[0034] In FIG. 4 b , the layer 410 is in the process of being oxidized. In one embodiment, the oxidation process includes a krypton/oxygen mixed plasma oxidation process. The mixed plasma process generates atomic oxygen or oxygen radicals in contrast to molecular oxygen or O ₂ used in conventional thermal oxidation. The atomic oxygen is introduced to the layer from all exposed directions as indicated by arrows 440 , creating an oxide portion 450 . The atomic oxygen continues to react with the layer and creates an oxidation interface 422 . As the reaction progresses, atomic oxygen diffuses through the oxide portion 450 and reacts at the oxidation interface 422 until the layer is completely converted to an oxide of the deposited material layer. FIG. 4 c shows the resulting oxide layer 450 which spans a physical thickness 452 from the outer surface 430 to the interface 420 .

[0035] In one embodiment, the processing variables for the mixed plasma oxidation include a low ion bombardment energy of less than 7 eV, a high plasma density above 10 ¹² /cm ³ and a low electron temperature below 1.3 eV. In one embodiment, the substrate temperature is approximately 400° C. In one embodiment, a mixed gas of 3% oxygen with the balance being krypton at a pressure of 1 Torr is used. In one embodiment, a microwave power density of 5 W/cm ² is used. In one embodiment, the oxidation process provides a growth rate of 1.5 nm/min.

[0036] The low temperature mixed plasma oxidation process described above allows the deposited layer to be oxidized at a low temperature, which inhibits the formation of unwanted byproducts such as silicides and oxides. The mixed plasma process in one embodiment is performed at approximately 400° C. in contrast to prior thermal oxidation processes that are performed at approximately 1000° C. The mixed plasma oxidation process has also been shown to provide improved thickness variation on silicon (111) surfaces in addition to (100) surfaces. Although the low temperature mixed plasma process above describes the formation of alternate material oxides, one skilled in the art will recognize that the process can also be used to form SiO ₂ oxide structures.

[0037] Metals chosen from group IVB of the periodic table form oxides that are thermodynamically stable such that the gate oxides formed will have minimal reactions with a silicon substrate or other structures during any later high temperature processing stages. Zirconium is one example of a metal selected from group IVB that forms a thermodynamically stable gate oxide. In particular, zirconium forms an oxide comprised of ZrO ₂ . Zirconium oxide ZrO ₂ exhibits a dielectric constant of approximately 25, which allows for a thinner EOT than conventional SiO ₂ . In addition to the stable thermodynamic properties inherent in the oxides chosen, the novel process used to form the oxide layer is performed at lower temperatures than the prior art, which further inhibits reactions with the silicon substrate or other structures.

[0038] A transistor made using the novel gate oxide process described above will possess several novel features. By creating an oxide material with a higher dielectric constant (k) and controlling surface roughness during formation, a gate oxide can be formed with an EOT thinner than 2 nm. A thicker gate oxide that is more uniform, and easier to process can also be formed with the alternate material oxide of the present invention, the alternate material gate oxide possessing an EOT equivalent to the current limits of SiO ₂ gate oxides. The smooth surface of the body region is preserved during processing, and a resulting transistor will have a smooth interface between the body region and the gate oxide with a surface roughness on the order of 0.6 nm.

[0039] Transistors created by the methods described above may be implemented into memory devices and information handling devices as shown in FIGS. 5 - 7 and described below. While specific types of memory devices and computing devices are shown below, it will be recognized by one skilled in the art that several types of memory devices and information handling devices could utilize the invention.

[0040] A personal computer, as shown in FIGS. 5 and 6 , include a monitor 500 , keyboard input 502 and a central processing unit 504 . The processor unit typically includes microprocessor 606 , memory bus circuit 608 having a plurality of memory slots 612 ( a - n ), and other peripheral circuitry 610 . Peripheral circuitry 610 permits various peripheral devices 624 to interface processor-memory bus 620 over input/output (I/O) bus 622 . The personal computer shown in FIGS. 5 and 6 also includes at least one transistor having a gate oxide according to the teachings of the present invention.

[0041] Microprocessor 606 produces control and address signals to control the exchange of data between memory bus circuit 608 and microprocessor 606 and between memory bus circuit 608 and peripheral circuitry 610 . This exchange of data is accomplished over high speed memory bus 620 and over high speed I/O bus 622 .

[0042] Coupled to memory bus 620 are a plurality of memory slots 612 ( a - n ) which receive memory devices well known to those skilled in the art. For example, single inline memory modules (SIMMs) and dual in-line memory modules (DIMMs) may be used in the implementation of the present invention.

[0043] These memory devices can be produced in a variety of designs which provide different methods of reading from and writing to the dynamic memory cells of memory slots 612 . One such method is the page mode operation. Page mode operations in a DRAM are defined by the method of accessing a row of a memory cell arrays and randomly accessing different columns of the array. Data stored at the row and column intersection can be read and output while that column is accessed. Page mode DRAMs require access steps which limit the communication speed of memory circuit 608 . A typical communication speed for a DRAM device using page mode is approximately 33 MHZ.

[0044] An alternate type of device is the extended data output (EDO) memory which allows data stored at a memory array address to be available as output after the addressed column has been closed. This memory can increase some communication speeds by allowing shorter access signals without reducing the time in which memory output data is available on memory bus 620 . Other alternative types of devices include SDRAM, DDR SDRAM, SLDRAM and Direct RDRAM as well as others such as SRAM or Flash memories.

[0045] FIG. 7 is a block diagram of an illustrative DRAM device 700 compatible with memory slots 612 ( a - n ). The description of DRAM 700 has been simplified for purposes of illustrating a DRAM memory device and is not intended to be a complete description of all the features of a DRAM. Those skilled in the art will recognize that a wide variety of memory devices may be used in the implementation of the present invention. The example of a DRAM memory device shown in FIG. 7 includes at least one transistor having a gate oxide according to the teachings of the present invention.

[0046] Control, address and data information provided over memory bus 620 is further represented by individual inputs to DRAM 700 , as shown in FIG. 7 . These individual representations are illustrated by data lines 702 , address lines 704 and various discrete lines directed to control logic 706 .

[0047] As is well known in the art, DRAM 700 includes memory array 710 which in turn comprises rows and columns of addressable memory cells. Each memory cell in a row is coupled to a common wordline. Additionally, each memory cell in a column is coupled to a common bitline. Each cell in memory array 710 includes a storage capacitor and an access transistor as is conventional in the art.

[0048] DRAM 700 interfaces with, for example, microprocessor 606 through address lines 704 and data lines 702 . Alternatively, DRAM 700 may interface with a DRAM controller, a micro-controller, a chip set or other electronic system. Microprocessor 606 also provides a number of control signals to DRAM 700 , including but not limited to, row and column address strobe signals RAS and CAS, write enable signal WE, an output enable signal OE and other conventional control signals.

[0049] Row address buffer 712 and row decoder 714 receive and decode row addresses from row address signals provided on address lines 704 by microprocessor 606 . Each unique row address corresponds to a row of cells in memory array 710 . Row decoder 714 includes a wordline driver, an address decoder tree, and circuitry which translates a given row address received from row address buffers 712 and selectively activates the appropriate wordline of memory array 710 via the wordline drivers.

[0050] Column address buffer 716 and column decoder 718 receive and decode column address signals provided on address lines 704 . Column decoder 718 also determines when a column is defective and the address of a replacement column. Column decoder 718 is coupled to sense amplifiers 720 . Sense amplifiers 720 are coupled to complementary pairs of bitlines of memory array 710 .

[0051] Sense amplifiers 720 are coupled to data-in buffer 722 and data-out buffer 724 . Data-in buffers 722 and data-out buffers 724 are coupled to data lines 702 . During a write operation, data lines 702 provide data to data-in buffer 722 . Sense amplifier 720 receives data from data-in buffer 722 and stores the data in memory array 710 as a charge on a capacitor of a cell at an address specified on address lines 704 .

[0052] During a read operation, DRAM 700 transfers data to microprocessor 606 from memory array 710 . Complementary bitlines for the accessed cell are equilibrated during a precharge operation to a reference voltage provided by an equilibration circuit and a reference voltage supply. The charge stored in the accessed cell is then shared with the associated bitlines. A sense amplifier of sense amplifiers 720 detects and amplifies a difference in voltage between the complementary bitlines. The sense amplifier passes the amplified voltage to data-out buffer 724 .

[0053] Control logic 706 is used to control the many available functions of DRAM 700 . In addition, various control circuits and signals not detailed herein initiate and synchronize DRAM 700 operation as known to those skilled in the art. As stated above, the description of DRAM 700 has been simplified for purposes of illustrating the present invention and is not intended to be a complete description of all the features of a DRAM. Those skilled in the art will recognize that a wide variety of memory devices, including but not limited to, SDRAMs, SLDRAMs, RDRAMs and other DRAMs and SRAMs, VRAMs and EEPROMs, may be used in the implementation of the present invention. The DRAM implementation described herein is illustrative only and not intended to be exclusive or limiting.

Conclusion

[0054] Thus has been shown a gate oxide and method of fabricating a gate oxide that produce a more reliable and thinner equivalent oxide thickness. Gate oxides formed from elements in group IVB of the periodic table are thermodynamically stable such that the gate oxides formed will have minimal reactions with a silicon substrate or other structures during any later high temperature processing stages. Zirconium oxide in particular has been shown to provide excellent electrical and thermodynamic properties. In addition to the stable thermodynamic properties inherent in the gate oxide of the invention, the process shown is performed at lower temperatures than the prior art, which further inhibits reactions with the silicon substrate or other structures.

[0055] Transistors and higher level ICs or devices have been shown utilizing the novel gate oxide and process of formation. The higher dielectric constant (k) oxide materials shown in one embodiment are formed with an EOT thinner than 2 nm, e.g. thinner than possible with conventional SiO ₂ gate oxides. A thicker gate oxide that is more uniform, and easier to process has also been shown with at EOT equivalent to the current limits of SiO ₂ gate oxides. In one embodiment of the present invention, the novel gate oxide provides a conduction band offset in a range of approximately 5.16 eV to 7.8 eV.

[0056] A novel process of forming a gate oxide has been shown where the surface smoothness of the body region is preserved during processing, and the resulting transistor has a smooth interface between the body region and the gate oxide with a surface roughness on the order of 0.6 nm. This solves the prior art problem of poor electrical properties such as high leakage current, created by unacceptable surface roughness.

[0057] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiment shown. This application is intended to cover any adaptations or variations of the present invention. It is to be understood that the above description is intended to be illustrative, and not restrictive. Combinations of the above embodiments, and other embodiments will be apparent to those of skill in the art upon reviewing the above description. The scope of the invention includes any other applications in which the above structures and fabrication methods are used. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.