DETAILED DESCRIPTION OF THE EMBODIMENTS

[0073] Computer System— FIG. 1

[0074] Referring now to FIG. 1 , one embodiment of a computer system 80 that includes a three-dimensional (3-D) graphics system is shown. The 3-D graphics system may be comprised in any of various systems, including a computer system, network PC, Internet appliance, a television, including HDTV systems and interactive television systems, personal digital assistants (PDAs), and other devices which display 2D and or 3D graphics, among others.

[0075] As shown, the computer system 80 comprises a system unit 82 and a display device 84 coupled to the system unit 82 . The display device 84 may be any of various types of display monitors or devices (e.g., a CRT, LCD, or gas-plasma display). Various input devices may be connected to the computer system, including a keyboard 86 and/or a mouse 88 , or other input device (e.g., a trackball, digitizer, tablet, six-degree of freedom input device, head tracker, eye tracker, data glove, body sensors, etc.). Application software may be executed by the computer system 80 to display 3-D graphical objects on display device 84 .

[0076] As described further below, the 3-D graphics system in computer system 80 includes a super-sampled sample buffer with a programmable sample-to-pixel calculation unit to improve the quality and realism of images displayed on display device 84 . The sample-to-pixel calculation unit may include a filter or convolve pipeline or other hardware for generating pixels in response to samples in the sample buffer. The sample-to-pixel calculation unit may operate to obtain samples from the sample buffer and generate pixels that are provided directly to the display. The sample-to-pixel calculation unit may operate in a “real-time” or “on-the-fly” fashion.

[0077] As used herein the terms “filter” and “convolve” are used interchangeably and refer to mathematically manipulating one or more samples to generate a pixel (e.g., by averaging, by applying a convolution function, by summing, by weighting the samples and then manipulating them, by applying a randomized function, etc.).

[0078] As used herein, the term “on-the-fly” refers to a function that is performed at or near the display device's refresh rate. “Real-time” means at, near, or above the human visual system's perception capabilities for motion fusion (how often a picture must be changed to give the illusion of continuous motion) and flicker fusion (how often light intensity must be changed to give the illusion of continuous). These concepts are further described in the book “Spatial Vision” by Russel L. De Valois and Karen K. De Valois, Oxford University Press, 1988.

[0079] In one embodiment, the graphics system is operable to provide various sample modes for pixels within a frame, preferably on a per window or per object basis. Thus, the graphics system may provide single sample per pixel support in a multi-sample environment. The graphics system may maintain information (e.g., a window ID) on a per window basis regarding the number of samples per pixel and/or filter type used. The graphics system may identify whether a window requires single sample per pixel support, for example, by examining the window ID associated with each sample, pixel, or bin. In one embodiment, the graphics system is provided with graphics data, which include a window ID, stating coordinates and color information for a pixel (for example, pixel write commands). In another embodiment, the graphics processor may receive graphics commands from the central processing unit or from another external control unit stating, for example, “draw an object at this location of this color”. In this instance, the computer system or graphics processor may assign a window ID to the samples, pixels, or bins corresponding to the object.

[0080] Computer Network— FIG. 1A

[0081] Referring now to FIG. 1A, a computer network 500 is shown comprising at least one server computer 502 and one or more client computers 506 A-N. (In the embodiment shown in FIG. 1 C, client computers 506 A-B are depicted). One or more of the client systems may be configured similarly to computer system 80 , with each having one or more graphics systems 112 as described above. Server 502 and client(s) 506 may be joined through a variety of connections 504 , such as a local-area network (LAN), a wide-area network (WAN), or an Internet connection. In one embodiment, server 502 may store and transmit 3-D geometry data (which may be compressed) to one or more of clients 506 . The clients 506 receive the compressed 3-D geometry data, decompress it (if necessary), and then render the geometry data. The rendered image is then displayed on the client's display device. The clients render the geometry data and display the image using super-sampled sample buffer and on-the-fly filter techniques described herein. In another embodiment, the compressed 3-D geometry data may be transferred between client computers 506 .

[0082] Computer System Block Diagram— FIG. 2

[0083] Referring now to FIG. 2, a simplified block diagram illustrating one embodiment of the computer system 80 of FIG. 1 (or FIG. 1A ) is shown. FIG. 2 may also illustrate the computers 506 A, 506 B, or 502 . Elements of the computer system that are not necessary for an understanding of the present invention are not shown for convenience. As shown, the computer system 80 includes a central processing unit (CPU) 102 coupled to a high-speed memory bus or system bus 104 also referred to as the host bus 104 . A system memory 106 may also be coupled to high-speed bus 104 .

[0084] Host processor 102 may comprise one or more processors of varying types, e.g., microprocessors, multi-processors, and CPUs. The system memory 106 may comprise any combination of different types of memory subsystems, including random access memories, (e.g., static random access memories or “SRAMs”, synchronous dynamic random access memories or “SDRAMs”, and Rambus dynamic access memories or “RDRAM”, among others) and mass storage devices. The system bus or host bus 104 may comprise one or more communication or host computer buses (for communication between host processors, CPUs, and memory subsystems) as well as specialized subsystem buses.

[0085] A 3-D graphics system or graphics system 112 according to the present invention is coupled to the high-speed memory bus 104 . The 3-D graphics system 112 may be coupled to the bus 104 by, for example, a crossbar switch or other bus connectivity logic. It is assumed that various other peripheral devices, or other buses, may be connected to the high-speed memory bus 104 . It is noted that the 3-D graphics system may be coupled to one or more of the buses in computer system 80 and/or may be coupled to various types of buses. In addition, the 3D graphics system may be coupled to a communication port and thereby directly receive graphics data from an external source, e.g., the Internet or a network. As shown in the figure, display device 84 is connected to the 3-D graphics system 112 comprised in the computer system 80 .

[0086] Host CPU 102 may transfer information to and from the graphics system 112 according to a programmed input/output (I/O) protocol over host bus 104 . Alternately, graphics system 112 may access the memory subsystem 106 according to a direct memory access (DMA) protocol or through intelligent bus mastering.

[0087] A graphics application program conforming to an application programming interface (API) such as OpenGL or Java 3D may execute on host CPU 102 and generate commands and data that define a geometric primitive (graphics data) such as a polygon for output on display device 84 . As defined by the particular graphics interface used, these primitives may have separate color properties for the front and back surfaces. Host processor 102 may transfer these graphics data to memory subsystem 106 . Thereafter, the host processor 102 may operate to transfer the graphics data to the graphics system 112 over the host bus 104 . In another embodiment, the graphics system 112 may read in geometry data arrays over the host bus 104 using DMA access cycles. In yet another embodiment, the graphics system 112 may be coupled to the system memory 106 through a direct port, such as the Advanced Graphics Port (AGP) promulgated by Intel Corporation.

[0088] The graphics system may receive graphics data from any of various sources, including the host CPU 102 and/or the system memory 106 , other memory, or from an external source such as a network, e.g., the Internet, or from a broadcast medium, e.g., television, or from other sources.

[0089] As will be described below, graphics system 112 may be configured to allow more efficient microcode control, which results in increased performance for handling of incoming color values corresponding to the polygons generated by host processor 102 . Note that while graphics system 112 is depicted as part of computer system 80 , graphics system 112 may also be configured as a stand-alone device (e.g., with its own built-in display) or as part of another device, such as a PDA, television, or any other device with display capabilities. Graphics system 112 may also be configured as a single chip device or as part of a system-on-a-chip or a multi-chip module.

[0090] Graphics System— FIG. 3

[0091] FIG. 3 is a block diagram illustrating details of one embodiment of graphics system 112 . As shown in the figure, graphics system 112 may comprise one or more graphics processors 90 , one or more super-sampled sample buffers 162 , and one or more sample-to-pixel calculation units 170 A-D. Graphics system 112 may also comprise one or more digital-to-analog converters (DACs) 178 A-B. Graphics processor 90 may be any suitable type of high performance processor (e.g., specialized graphics processors or calculation units, multimedia processors, DSPs, or general purpose processors). In one embodiment, graphics processor 90 may comprise one or more rendering units 150 A-D. In the embodiment shown, however, graphics processor 90 also comprises one or more control units 140 and one or more schedule units 154 . Sample buffer 162 may comprises one or more sample memories 160 A- 160 N as shown in the figure.

[0092] A. Control Unit

[0093] Control unit 140 operates as the interface between graphics system 112 and computer system 80 by controlling the transfer of data between graphics system 112 and computer system 80 . In embodiments of graphics system 112 that comprise two or more rendering units 150 A-D, control unit 140 may also divide the stream of data received from computer system 80 into a corresponding number of parallel streams that are routed to the individual rendering units 150 A-D. The graphics data may be received from computer system 80 in a compressed form. This may advantageously reduce the bandwidth requirements between computer system 80 and graphics system 112 . In one embodiment, control unit 140 may be configured to split and route the data stream to rendering units 150 A-D in compressed form.

[0094] The graphics data may comprise one or more graphics primitives. As used herein, the term graphics primitive includes polygons, parametric surfaces, splines, NURBS (non-uniform rational B-splines), sub-divisions surfaces, fractals, volume primitives, and particle systems. These graphics primitives are described in detail in the textbook entitled “Computer Graphics: Principles and Practice” by James D. Foley, et al., published by Addison-Wesley Publishing Co., Inc., 1996. Note polygons are referred to throughout this detailed description for simplicity, but the embodiments and examples described may also be used with graphics data comprising other types of graphics primitives.

[0095] B. Rendering Units

[0096] Rendering units 150 A-D (also referred to herein as draw units) are configured to receive graphics instructions and data from control unit 140 and then perform a number of functions, depending upon the exact implementation. For example, rendering units 150 A-D may be configured to perform decompression (if the data is compressed), transformation, clipping, lighting, texturing, depth cueing, transparency processing, set-up, and screen space rendering of various graphics primitives occurring within the graphics data. Each of these features is described separately below. In one embodiment, rendering units 150 may comprise first rendering unit 151 and second rendering unit 152 . First rendering unit 151 may be configured to perform decompression (for compressed graphics data), format conversion, transformation, lighting, etc. Second rendering unit may be configured to perform screen space setup, screen space rasterization, sample rendering, etc. In one embodiment, first rendering unit 151 may be coupled to first data memory 155 , and second rendering unit 152 may be coupled to second data memory 156 . First data memory 155 may comprise SDRAM, and second data memory 156 may comprise RDRAM. In one embodiment, first rendering unit 151 may be a processor, and second rendering unit 152 may be a dedicated ASIC chip.

[0097] Depending upon the type of compressed graphics data received, rendering units 150 A-D may be configured to perform arithmetic decoding, run-length decoding, Huffman decoding, and dictionary decoding (e.g., LZ77, LZSS, LZ78, and LZW). In another embodiment, rendering units 150 A-D may be configured to decode graphics data that has been compressed using geometric compression. Geometric compression of 3D graphics data may achieve significant reductions in data size while retaining most of the image quality. Two methods for compressing and decompressing 3D geometry are described in U.S. Pat. No. 5,793,371, U.S. application Ser. No. 08/511,294, (filed on Aug. 4, 1995, entitled “Method And Apparatus For Geometric Compression Of Three-Dimensional Graphics Data,” Attorney Docket No. 5181-05900) and U.S. patent application Ser. No. 09/095,777, filed on Jun. 11, 1998, entitled “Compression of Three-Dimensional Geometry Data Representing a Regularly Tiled Surface Portion of a Graphical Object,” Attorney Docket No. 5181-06602). In embodiments of graphics system 112 that support decompression, the graphics data received by each rendering unit 150 is decompressed into one or more graphics “primitives” which may then be rendered. The term primitive refers to components of objects that define its shape (e.g., points, lines, triangles, polygons in two or three dimensions, polyhedra, or free-form surfaces in three dimensions). Rendering units 150 may be any suitable type of high performance processor (e.g., specialized graphics processors or calculation units, multimedia processors, DSPs, or general purpose processors).

[0098] Transformation refers to manipulating an object and includes translating the object (i.e., moving the object to a different location), scaling the object (i.e., stretching or shrinking), and rotating the object (e.g., in three-dimensional space, or “3-space”).

[0099] Clipping refers to defining the limits of the displayed image (i.e., establishing a clipping region, usually a rectangle) and then not rendering or displaying pixels that fall outside those limits.

[0100] Lighting refers to calculating the illumination of the objects within the displayed image to determine what color and or brightness each individual object will have. Depending upon the shading algorithm being used (e.g., constant, Gourand, or Phong), lighting may be evaluated at a number of different locations. For example, if constant shading is used (i.e., each pixel of a polygon has the same lighting), then the lighting need only be calculated once per polygon. If Gourand shading is used, then the lighting is calculated once per vertex. Phong shading calculates the lighting on a per-pixel basis.

[0101] Set-up refers to mapping primitives to a three-dimensional viewport. This involves translating and transforming the objects from their original “world-coordinate” system to the established viewport's coordinates. This creates the correct perspective for three-dimensional objects displayed on the screen.

[0102] Screen-space rendering refers to the calculations performed to actually calculate the data used to generate each pixel that will be displayed. In prior art systems, each pixel is calculated and then stored in a frame buffer. The contents of the frame buffer are then output to the display device to create the final image. In the embodiment of graphics system 112 shown in the figure, however, rendering units 150 A-D calculate “samples” instead of actual pixel data. This allows rendering units 150 A-D to “super-sample” or calculate more than one sample per pixel. Super-sampling is described in greater detail below. The rendering units 150 A-D may also generate a greater area of samples than the viewable area of the display 84 for various effects such as panning and zooming. Note that rendering units 150 A-B may comprises a number of smaller functional units, e.g., a separate set-up/decompress unit and a lighting unit.

[0103] More details on super-sampling are discussed in the following books: “Principles of Digital Image Synthesis” by Andrew Glassner, 1995, Morgan Kaufman Publishing (Volume 1); “The Renderman Companion” by Steve Upstill, 1990, Addison Wesley Publishing; “Advanced Renderman: Beyond the Companion” by Anthony A. Apodaca et al.; and “Advanced Renderman: Creating Cgi for Motion Pictures (Computer Graphics and Geometric Modeling)” by Anthony A. Apodaca and Larry Gritz, Morgan Kaufmann Publishers; ISBN: 1558606181. In one embodiment of the invention, the rendering units may receive a window ID value that indicates a sample mode for rendering of samples within the window. Based on the received window ID, the rendering units may be operable to selectively render a different number of samples per pixel or per bin on a per window basis. For example, for pixels in a window that has been identified as requiring a single sample per pixel, the rendering units may generate only a single sample per pixel. In other regions of the display, the rendering units may generate the default number of samples per pixel, which is typically greater than one.

[0104] Alternatively, the rendering units may render the same number of samples per pixel regardless of the sample mode. In this embodiment, for pixels in a window which has a single sample per pixel mode, the rendering units may render the same sample value for the samples that correspond to particular pixels in the pre-defined window. Here it may be desirable for the rendering unit to know a priori the filter size of the filter applied to the respective pixels. It may also be desirable that the filters not overlap in this region.

[0105] C. Data Memories

[0106] Each rendering unit 150 A-D may comprise two sets of instruction and data memories 155 and 156 . In one embodiment, data memories 155 and 156 may be configured to store both data and instructions for rendering units 150 A-D. While implementations may vary, in one embodiment, data memories 156 may comprise two 8 MByte SDRAMs providing a total of 16 MBytes of storage for each rendering unit 150 A-D. Data memories 155 may comprise RDRAMs (Rambus DRAMs). RDRAMs may be used to support the decompression and set-up operations of the rendering units, while SDRAMs may be used to support the draw functions of rendering units 150 A-D

[0107] D. Schedule Unit

[0108] Schedule unit 154 may be coupled between the rendering units 150 A-D and the sample memories 160 A-N. Schedule unit 154 is configured to sequence the completed samples and store them in sample memories 160 A-N. Note in larger configurations, multiple schedule units 154 may be used in parallel. In one embodiment, schedule unit 154 may be implemented as a crossbar switch.

[0109] E. Sample Memories

[0110] Super-sampled sample buffer 162 comprises sample memories 160 A- 160 N, which are configured to store the plurality of samples generated by the rendering units. As used herein, the term “sample buffer” refers to one or more memories that store samples. As previously noted, samples are rendered into the sample buffer 162 at positions in the sample buffer which correspond to positions or locations in screen space on the display. The positions may be calculated using various methods, such as grid-based or stochastic position generation. The positions may be calculated or programmatically determined on a per frame basis, a per bin basis, or even a per sample basis. In one embodiment, sample position information is stored with the samples in the sample buffer.

[0111] One or more samples are then filtered to form each output pixel (i.e., pixels to be displayed on a display device). The number of samples stored may be greater than, equal to, or less than the total number of pixels output to the display device to refresh a single frame. Each sample may correspond to one or more output pixels. As used herein, a sample “corresponds” to an output pixel when the sample's information contributes to the final output value of the pixel. Note, however, that some samples may contribute zero to their corresponding output pixel after filtering takes place. Also, some samples may be rendered and stored in the sample buffer which are outside the viewable area of the display device 84 for one or more frames, wherein these samples may be used in subsequent frames for various display effects such as panning and zooming.

[0112] Stated another way, the sample buffer stores a plurality of samples that have positions that correspond to locations in screen space on the display, i.e., the samples contribute to one or more output pixels on the display. The number of stored samples may be greater than the number of pixel locations, and more than one sample may be combined in the convolution (filtering) process to generate a particular output pixel displayed on the display device. Any given sample may contribute to one or more output pixels.

[0113] Sample memories 160 A- 160 N may comprise any of a number of different types of memories (e.g., SDRAMs, SRAMs, RDRAMs, 3DRAMs, or next-generation 3DRAMs) in varying sizes. In one embodiment, each schedule unit 154 is coupled to four banks of sample memories, wherein each bank comprises four 3DRAM-64 memories. Together, the 3DRAM-64 memories may form a 116-bit deep super-sampled sample buffer that stores multiple samples per pixel. For example, in one embodiment, each sample memory 160 A- 160 N may store up to sixteen samples per pixel. 3DRAM-64 memories are specialized memories configured to support full internal double buffering with single buffered Z in one chip. The double-buffered portion comprises two RGBX buffers, wherein X is a fourth channel that can be used to store other information (e.g., alpha). 3DRAM-64 memories also may include a lookup table that receives window ID information and controls an internal 2 - 1 or 3 - 1 multiplexer that selects which buffer's contents will be output. 3DRAM-64 memories are next-generation 3DRAM memories that may soon be available from Mitsubishi Electric Corporation's Semiconductor Group. In one embodiment, four chips used in combination are sufficient to create a double-buffered 1280×1024 super-sampled sample buffer. Since the memories are internally double-buffered, the input pins for each of the two frame buffers in the double-buffered system are time multiplexed (using multiplexers within the memories). The output pins may similarly be time multiplexed. This allows reduced pin count while still providing the benefits of double buffering. 3DRAM-64 memories further reduce pin count by not having z output pins. Since z comparison and memory buffer selection is dealt with internally, this may simplify sample buffer 162 (e.g., using less or no selection logic on the output side). Use of 3DRAM-64 also reduces memory bandwidth since information may be written into the memory without the traditional process of reading data out, performing a z comparison, and then writing data back in. Instead, the data may be simply written into the 3DRAM-64, with the memory performing the steps described above internally.

[0114] However, in other embodiments of graphics system 112 , other memories (e.g., SDRAMs, SRAMs, RDRAMs, or current generation 3DRAMs) may be used to form sample buffer 162 .

[0115] Graphics processor 90 may be configured to generate a plurality of sample positions according to a particular sample positioning scheme (e.g., a regular grid, a perturbed regular grid, stochastic, etc.).

[0116] In one embodiment of the invention, the graphics processor receives the window ID value for a window and generates or renders sample positions based on the window. For example, the graphics processor may receive pixel write commands with a window ID from a legacy API such as X-Windows.

[0117] The sample position information for each of the samples may be stored for later use by the sample-to-pixel calculation unit(s). For example, the graphics processor 90 may store the sample position information in the sample buffer with the samples, or may store the sample position information in a separate sample position memory. Alternatively, the sample position information (e.g., offsets that are added to regular grid positions to form the sample positions) may be pre-determined or pre-computed using one of the above schemes and simply read from the sample position memory (e.g., a RAM/ROM table). The sample position information may be pre-computed by the graphics processor, by the host CPU, or by other logic.

[0118] The sample position information may comprise coordinate values relative to a sample buffer coordinate system, e.g., coordinate values relative to the display space. The sample position information may also comprise offset values, wherein the offset values are relative to pre-defined locations in the sample buffer, such as a pre-defined regular grid, pre-defined bins, or pixel center coordinates.

[0119] Upon receiving a polygon that is to be rendered, graphics processor 90 determines which samples reside within the polygon based upon the sample position information. Graphics processor 90 renders the samples that fall within the polygon and stores rendered samples in sample memories 160 A-N. Note as used herein the terms render and draw are used interchangeably and refer to calculating color values for samples. Depth values, alpha values, and other per-sample values may also be calculated in the rendering or drawing process.

[0120] Furthermore, as mentioned above, the graphics processor may generate a different number of samples per pixel for different windows on the screen. The central processing unit may designate some windows with different sample modes, e.g., to not utilize multi-sampling, by tagging a window ID for the respective window.

[0121] F. Sample-To-Pixel Calculation Units

[0122] Sample-to-pixel calculation units 170 A-D (sometimes collectively referred to as sample-to-pixel calculation unit 170 ) may be coupled between sample memories 160 A-N and DACs 178 A-B. Sample-to-pixel calculation units 170 A-D are configured to read selected samples from sample memories 160 A-N, wherein the samples are selected based on the position information of the samples, and then perform a convolution (e.g., a filtering and weighting function or a low pass filter) on the samples to generate the output pixel values which are output to DACs 178 A-B. The sample-to-pixel calculation units 170 A-D may be programmable to allow them to perform different filter functions at different times, depending upon the type of output desired. In one embodiment, the sample-to-pixel calculation units 170 A-D may implement a 5×5 super-sample reconstruction band-pass filter to convert the super-sampled sample buffer data (stored in sample memories 160 A-N) to single pixel values. In other embodiments, calculation units 170 A-D may filter a selected number of samples to calculate an output pixel. The filtered samples may be multiplied by a variable weighting factor that gives more or less weight to samples having positions close to the center of the pixel being calculated. Other filtering functions may also be used either alone or in combination, e.g., tent filters, circular and elliptical filters, Mitchell filters, band pass filters, sync function filters, etc.

[0123] Sample-to-pixel calculation units 170 A-D may also be configured with one or more of the following features: color look-up using pseudo color tables, direct color, inverse gamma correction, filtering of samples to pixels, and conversion of pixels to non-linear light space. Other features of sample-to-pixel calculation units 170 A-D may include programmable video timing generators, programmable pixel clock synthesizers, cursor generators, and crossbar functions. Once the sample-to-pixel calculation units have manipulated the timing and color of each pixel, the pixels are output to DACs 178 A-B.

[0124] Sample-to-pixel calculation units may utilize a window ID associated with each sample, bin, or pixel for generating output pixels. For example, for a sample, bin, or pixel that has been designated through a window ID to use regular multi-sampling, the sample-to-pixel calculation units may perform regular filtering operations, such as selecting one or more samples within a neighborhood of a pixel center. For a sample, bin, or pixel that has been designated through a window ID to use a single sample per pixel mode, the sample-to-pixel calculation units 170 may turn off filtering. In cases where a window is overlaid on top of another window, the pixels or samples corresponding to the first window may be designated to use multi-sampling mode, and the pixels or samples corresponding to the second window may be designated to use a single sample per pixel mode. For example, the first window may be displaying a car rendered in 3D for which anti-aliasing is preferably turned on for a higher quality image. The second (overlaid) window may contain annotations corresponding to the anti-aliased image of the car. Such a window is preferably displayed without using anti-aliasing to avoid blurring of any lines or writing contained in the annotations. In addition, since filtering may be turned on or off on a per sample, pixel, or bin basis, pixels that fall inside the first window but not inside the second window may be designated to use multisampling, and pixels that fall inside the window may be designated to use a single sample per pixel mode. In another embodiment, for a window that has been designated not to use multi-sampling, the sample-to-pixel calculation units may select a single sample per pixel, for example, the sample that is closest to the pixel center. In yet another embodiment, for a window that has been designated not to use multi-sampling and where all sample values for a pixel have the same value, the sample-to-pixel calculation units may perform regular, multi-sample filtering, preferably with the filter area limited so that there is no overlap of the filters for different pixels. The window ID associated with each sample, pixel, or bin may be used to determine the samples per pixel a particular window may use. The information may be used by the rendering unit (graphics processor) to generate the correct number of samples per pixel for each window.

[0125] G. DACs

[0126] DACs 178 A-B operate as the final output stage of graphics system 112 . The DACs 178 A-B serve to translate the digital pixel data received from cross units 174 A-B into analog video signals that are then sent to the display device. Note in one embodiment DACs 178 A-B may be bypassed or omitted completely in order to output digital pixel data in lieu of analog video signals. This may be useful when display device 84 is based on a digital technology (e.g., an LCD-type display or a digital micro-mirror display).

[0127] Super-Sampling FIGS. 4 - 5

[0128] FIG. 4 illustrates an example of traditional, non-super-sampled pixel value calculation. Each pixel has exactly one data point calculated for it, and the single data point is located at the center of the pixel. For example, only one data point (i.e., sample 74 ) contributes to value of pixel 70 .

[0129] Turning now to FIG. 5 A, an example of one embodiment of super-sampling is illustrated. In this embodiment, a number of samples are calculated. The number of samples may be related to the number of pixels or completely independent of the number of pixels. In this example, 18 samples are distributed in a regular grid across nine pixels. Even with all the samples present in the figure, a simple one to one correlation could be made (e.g., by throwing out all but the sample nearest to the center of each pixel). However, the more interesting case is performing a filtering function on multiple samples to determine the final pixel values. Also, as noted above, a single sample can be used to generate a plurality of output pixels, i.e., sub-sampling.

[0130] A circular filter 72 is illustrated in the figure. In this example, samples 74 A-B both contribute to the final value of pixel 70 . This filtering process may advantageously improve the realism of the image displayed by smoothing abrupt edges in the displayed image (i.e., performing anti-aliasing). Filter 72 may simply average samples 74 A-B to form the final value of output pixel 70 , or it may increase the contribution of sample 74 B (at the center of pixel 70 ) and diminish the contribution of sample 74 A (i.e., the sample farther away from the center of pixel 70 ). Circular filter 72 is repositioned for each output pixel being calculated so the center of filter 72 coincides with the center position of the pixel being calculated. Other filters and filter positioning schemes are also possible and contemplated.

[0131] Turning now to FIG. 5 B, another embodiment of super-sampling is illustrated. In this embodiment, however, the samples are positioned randomly. More specifically, different sample positions are selected and provided to graphics processor 90 (and render units 150 A-D), which calculate color information to form samples at these different locations. Thus the number of samples falling within filter 72 may vary from pixel to pixel.

[0132] Super-Sampled Sample Buffer With On-The-Fly Convolution—FIGS. 6 - 13

[0133] FIGS. 6A, 6B , 7 A and 7 B illustrate possible configurations for the flow of data through one embodiment of graphics system 112 . As the figures show, geometry data 350 is received by graphics system 112 and used to perform draw or render process 352 . The draw process 352 is implemented by one or more of control unit 140 , rendering units 150 , and schedule unit 154 . Geometry data 350 comprises data for one or more polygons. Each polygon comprises a plurality of vertices (e.g., three vertices in the case of a triangle), some of which may be shared. Data such as x, y, and z coordinates, color data, lighting data and texture map information may be included for each vertex.

[0134] The draw process 352 may also generate sample coordinates or sample position information for rendering of samples, or may receive pre-computed sample position information from a sample position memory 354 . As used herein, the term “sample position information” or simply “position information” refers to information which indicates or specifies positions or locations of samples rendered into the sample buffer 162 , wherein the positions or locations in the sample buffer 162 are generally relative to or correspond to positions or locations in a screen space of the display. In general, the terms “position” and “position information” are used interchangeably.

[0135] As discussed above, sample positions may be generated according to a particular sample positioning scheme. Example sample positioning schemes include a regular grid (e.g., regular square grid or a regular hexagonal grid), a perturbed regular grid, or stochastic position generation, among others. Graphics system 112 may receive an indication from the operating system, device driver, or the geometry data 350 that indicates which type of sample positioning scheme is to be used. Thus the graphics system 112 (e.g., graphics processor 90 ) is configurable or programmable to generate position information according to one or more different schemes. More detailed information on several sample position schemes are described further below (see description of FIG. 8 ).

[0136] Graphics processor 90 executing draw process 352 utilizes sample position information during rendering. The graphics processor 90 may be configured to generate the plurality of sample positions (position information) during rendering, or the sample positions may be generated by a graphics driver executing on the host CPU, or by other logic. The sample positions may also be pre-computed and stored in the sample position memory 354 for later use during rendering, wherein the position information is pre-computed by one of the graphics processor 90 , host CPU, or other logic. Thus the draw process 352 , or other hardware or software, may generate the plurality of sample positions on-the-fly during the rendering process and then store the position information in the sample position memory 354 , or the sample positions may be pre-computed and stored in the sample position memory 354 for later use during rendering.

[0137] As shown in FIGS. 6A and 6B , the sample position information may be stored in a separate sample position memory 354 . For example, the sample position information (e.g., offsets that are added to regular grid positions to form the sample positions) may be pre-determined or pre-computed using one of the above schemes and read from the sample position memory 354 (e.g., a RAM/ROM table) during rendering. The sample positions may be pre-computed by the graphics processor 90 , by the host CPU, or by other logic as noted above. Alternatively, the graphics processor 90 may generate the sample position information during rendering and store the sample position information in the sample position memory 354 .

[0138] In one embodiment, position memory 354 is embodied within rendering units 150 A-D. In another embodiment, position memory 354 may be realized as part of the texture and render data memories, or as a separate memory. Sample position memory 354 is configured to store position information for samples that are calculated in draw process 352 and then stored into super-sampled sample buffer 162 .

[0139] The sample position memory 354 may comprise a single memory ( FIG. 6A ) or may comprise two memories ( FIG. 6B ), e.g., a double buffered configuration. The double buffered sample position memories 354 A and 354 B allow for programmability of the sample position information, such as on a per frame or per bin basis, or a per sample basis. The double buffered embodiment of FIG. 6B is discussed further below.

[0140] The sample position information may also be stored in the sample buffer 162 with the samples, as shown in FIG. 7A . For example, the graphics processor 90 may generate the sample position information during rendering and store the sample position information with the samples in the sample buffer 162 . Since the sample buffer 162 is already double buffered, storage of the sample position information in the sample buffer 162 effectively double buffers the sample position information. FIG. 7B illustrates an embodiment where look-up table (LUT) tags or indices are stored with the samples in the sample buffer 162 , wherein these tags reference offsets stored in a separate sample position memory 354 .

[0141] In one embodiment, the sample position information may comprise entire sample position “addresses” or coordinates. However, this may involve increasing the size of position memory 354 ( FIGS. 6A, 6B and 7 B) or may involve increasing the size of the sample buffer ( FIG. 7A ). Alternatively, the sample position information may comprise only one or more offsets for each sample. Storing only the offsets may use less storage space than storing each sample's entire position. The one or more offset values may comprise x- and y-offsets or angular and distance offsets (polar coordinates), among others.

[0142] The one or more offset values may comprise offset values relative to a pre-defined regular grid, e.g., may be relative to pre-determined bin coordinates or pre-determined pixel center coordinates. For example, the one or more offset values may be relative to the bin in which the sample is located, such as the lower left corner of the bin. The offsets may be based on any of the various sample position schemes discussed above.

[0143] The sample position of a sample may be determined by combining the one or more offset values of the sample with the reference coordinates, e.g., coordinates from a regular grid, pre-determined bin coordinates, or pre-determined pixel center coordinates, among others. The offset values stored in sample position memory 354 or in the sample buffer 162 may be read by each of the graphics processor 90 and/or the sample-to-pixel calculation unit 170 and processed to calculate sample positions for the samples. Alternatively, the offset values stored in sample position memory 354 may be read by a dedicated sample position calculation unit (not shown) and processed to calculate example sample positions for graphics processor 90 and/or for sample-to-pixel calculation unit 170 . More detailed information on sample position offsets is included below (see description of FIGS. 9 and 10 ).

[0144] As mentioned above, the graphics system may include sample position memory 354 coupled to the sample-to-pixel calculation unit 170 which stores the offset values for each of the samples. As shown in FIGS. 6A, 6B and 7 B, the sample-to-pixel calculation unit 170 is operable to access the memory 354 to determine the offset values of the samples. The memory 354 may be a look-up table memory, wherein the sample-to-pixel calculation unit 170 is operable to index into the look-up table memory 354 to determine the offset values of the samples.

[0145] The samples may be stored in the sample buffer 162 according to bins, wherein each respective bin defines a region in the sample buffer 162 in which samples in the respective bin are located. As used herein, the term “bin” refers to a region or area in screen-space and contains however many samples are in that area (e.g., the bin may be 1×1 pixels in area, 2×2 pixels in area, etc.). The term “screen space” refers generally to the coordinate system of the display device. The use of bins may simplify the storage and access of samples in sample buffer 162 . A number of different bin sizes may be used (e.g., one sample per bin, four samples per bin, etc.). In the preferred embodiment, each bin has an xy-position that corresponds to a particular location on the display. The bins are preferably regularly spaced. In this embodiment the bins' xy-positions may be determined from the bin's storage location within sample buffer 162 . The bins' positions correspond to particular positions on the display. In some embodiments, the bin positions may correspond to pixel centers, while in other embodiments the bin positions correspond to points that are located between pixel centers.

[0146] The one or more offset values may comprise offset values relative to a bin. Thus a position of each sample within a respective bin may be determined by using the one or more offset values associated with the sample and the sample's bin position. As one example, position memory 354 may store pairs of 8 -bit numbers, each pair comprising an x-offset and a y-offset (other possible offsets are also possible, e.g., a time offset, a z-offset, polar coordinate offsets, etc.). When added to a bin position, each pair defines a particular position in screen space. To improve read times, memory 354 may be constructed in a wide/parallel manner so as to allow the memory to output more than one sample location per clock cycle.

[0147] In one embodiment, the samples are stored in the sample buffer 162 according to a bin ordering, wherein, for a respective bin, the bin ordering indicates a position of the samples in the respective bin. Thus, for a respective sample, the sample-to-pixel calculation unit 170 is operable to generate the position of the respective sample based at least partly on the bin ordering of the respective sample within its bin. For example, the offset values may be stored in the memory 354 according to the bin ordering of the samples, and the sample-to-pixel calculation unit 170 is operable to use the bin ordering of the samples in the bins to index into the memory 354 to determine the offset values of the samples. The sample position memory 354 may store a number of offset values less than the total number of samples in the sample buffer. For example, the sample position memory 354 may store a number of offset values corresponding to only one bin of the sample buffer 162 . In this instance, the sample-to-pixel calculation unit 170 is operable to reuse these offset values for each bin of the sample buffer 162 . The sample-to-pixel calculation unit 170 may operate to manipulate bits in the sample position memory addresses to obtain different offset values for samples in the bins as described above.

[0148] Once the sample positions have been read from sample position memory 354 , draw process 352 selects the sample positions that fall within the polygon currently being rendered. Draw process 352 then calculates the z and color information (which may include alpha, other depth of field information values, or other values) for each of these samples and stores the data into sample buffer 162 . In one embodiment, the sample buffer may only single-buffer z values (and perhaps alpha values) while double buffering other sample components such as color. Unlike prior art systems, graphics system 112 may double buffer all samples (although not all sample components may be double-buffered, i.e., the samples may have components that are not double-buffered, or not all samples may be double-buffered). In one embodiment, the samples are stored into sample buffer 162 in bins. In some embodiments, the size of bins, i.e., the quantity of samples within a bin, may vary from frame to frame and may also vary across different regions of display device 84 within a single frame. For example, bins along the edges of display device may comprise only one sample, while bins corresponding to pixels near the center of display device 84 may comprise sixteen samples. Note the area of bins may vary from region to region. The use of bins will be described in greater detail below in connection with FIG. 11 .

[0149] In parallel and preferably independently of draw process 352 , filter process 360 is configured to read samples from sample buffer 162 , filter (i.e., filter) them, and then output the resulting output pixel to display device 84 . Sample-to-pixel calculation units 170 implement filter process 380 . Thus, for at least a subset of the output pixels, the filter process is operable to filter a plurality of samples to produce a respective output pixel. In one embodiment, filter process 360 is configured to: (i) determine the distance from each sample to the center of the output pixel being filtered; (ii) multiply the sample's components (e.g., color and alpha) with a filter value that is a specific (programmable) function of the distance; (iii) sum all the weighted samples that contribute to the output pixel, and (iv) normalize the resulting output pixel. The filter process 360 is described in greater detail below (see description accompanying FIGS. 11, 12 , and 14 ). Note the extent of the filter need not be circular (i.e., it may be a function of x and y instead of the distance), but even if the extent is, the filter need not be circularly symmetrical. The filter's “extent” is the area within which samples can influence the particular pixel being calculated with the filter.

[0150] In one embodiment of the invention, the filtering process receives focus information and uses the focus information to selectively adjust the filtering to provide depth cueing or convergence cueing. This operation is discussed below with respect to FIG. 16 .

[0151] Double-Buffered Sample Position Memories— FIG. 6B

[0152] FIG. 6B illustrates an alternate embodiment of graphics system 112 , wherein two or more sample position memories 354 A and 354 B are utilized. As shown in FIG. 6 B, the graphics includes a first sample position memory 354 A and a second sample position memory 354 B. The first sample position memory 354 A is coupled to the graphics processor 90 and stores the position information for each of the samples. The graphics processor 90 uses the first memory 354 A in rendering the samples into the sample buffer 162 . As discussed above, the graphics processor 90 may also operate to generate and store the sample position information in the memory 354 A. The second sample position memory 354 B is coupled to the sample-to-pixel calculation unit 170 and also stores the position information for each of the samples. The sample-to-pixel calculation unit 170 is operable to access the second memory 354 B to determine the position information of the samples. The sample-to-pixel calculation unit 170 uses the position information obtained from the second memory 354 B to aid in selecting samples for filtering.

[0153] As shown, the first sample position memory 354 A is configured to provide sample position information to the second sample position memory 354 B, thus effectively providing a double buffered configuration. For example, the first memory 354 A is operable to transfer current position informatio