DETAILED DESCRIPTION OF THE INVENTION

[0033] Korean Patent Application No. 2001-37959, filed on Jun. 29, 2001, and entitled: “Method of Forming a Gate Electrode in Semiconductor Device and Method of Manufacturing a Non-Volatile Memory Device Using the Same,” is incorporated by reference herein in its entirety.

[0034] Hereinafter, the embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0035] FIGS. 2A to 2 J illustrate sectional views of stages in a method of forming a gate electrode in a semiconductor device according to a first embodiment of the present invention.

[0036] Referring to FIG. 2A, a semiconductor substrate 40 , including a material such as silicon, is divided into an active area and a field area by a conventional isolation process (not shown). A silicon oxide film is grown on the semiconductor substrate 40 having the active area and the field area to form a gate oxide film 42 of a cell transistor.

[0037] Polysilicon, which is doped with impurities to make it highly conductive, is deposited on the gate oxide film 42 to form a polysilicon layer 44 . An insulation material, such as a nitride, is deposited on the polysilicon layer 44 to form a hard mask layer 46 , which is used as an etching mask in a subsequent etching process. Preferably, the hard mask layer 46 includes a nitride based insulating materials, such as a silicon nitride film or a silicon oxynitride film.

[0038] Referring to FIG. 2B, a predetermined portion of the hard mask layer 46 is etched by a photolithography process so that a hard mask pattern 46 a is formed. The hard mask nitride film remains only where the gate electrode is to be formed. The hard mask pattern 46 a is used as an etching mask for forming a gate structure in a subsequent process.

[0039] Referring to FIG. 2 C, the lower films are continuously and anisotropically etched using the hard mask pattern 46 a as an etching mask in order to form a gate structure 48 in which the hard mask pattern 46 a, a polysilicon layer pattern 44 a and the gate oxide film pattern 42 a are stacked.

[0040] Using the gate structure 48 as an ion implanting mask, impurities are implanted into the semiconductor substrate 40 so that source/drain regions 50 are formed under a surface of the semiconductor substrate 40 .

[0041] When the anisotropic etching is performed in order to form the gate structure 48 , however, a surface of the hard mask pattern 46 a used as the etching mask is partially etched due to an impact of an ion beam used for the anisotropic etching. The respective hard mask pattern 46 a is differently and non-uniformly etched due to a difference in the density of a peripheral pattern or a position of the hard mask pattern on the semiconductor substrate. Therefore, the hard mask pattern 46 a remaining on the top of the respective gate structure 48 has a non-uniform thickness after the etching process is performed.

[0042] Referring to FIG. 2 D, an oxide film is formed on the resulting gate structure 48 and the semiconductor substrate 40 , shown in FIG. 2C . Then, the oxide film is anisotropically etched to form a gate spacer 52 on a sidewall of the gate structure 48 .

[0043] Referring to FIG. 2 E, the hard mask pattern 46 a remaining on the top of the gate structure 48 is removed to expose a surface of the polysilicon pattern 44 a.

[0044] The hard mask pattern 46 a is removed by dipping in an etchant, such as a chemical stripping solution including a phosphoric acid (H ₃ PO ₄ ). Alternatively, the hard mask pattern 46 a may be removed in a dry etching process. In the case of the dry etching process, however, a process defect including a substrate defect can occur since an impact of an ion beam used for dry etching is applied to a surface of the semiconductor substrate 40 where the polysilicon layer pattern 44 a is not formed. Therefore, the hard mask pattern 46 a is preferably removed in the phosphoric acid wet etch stripping process.

[0045] The resulting exposed polysilicon layer pattern 44 a will have a uniform thickness after the removal of the hard mask pattern 46 a having a non-uniform thickness, at this stage of processing the gate electrode, using the phosphoric acid wet etching. After the removal of the hard mask pattern 46 a, a top portion 52 a of the gate spacer that was around the hard mask pattern 46 a projects above the polysilicon layer pattern 44 a.

[0046] Referring to FIG. 2F, a top portion of the gate spacer 52 a that was formed around the hard mask pattern 46 a and projected above the polysilicon layer pattern 44 a is removed to planarize the top portions of the polysilicon layer pattern 44 a and the gate spacer 52 , resulting a new gate spacer structure 52 b.

[0047] For planarizing the top portions of the polysilicon layer pattern 44 a and the gate spacer 52 and to obtain the structure shown in FIG. 2 F, the semiconductor substrate including the projected gate spacer 52 a, shown in FIG. 2E is dipped in a hydrofluoric acid (HF) solution for thirty seconds. When the semiconductor substrate is immersed in the hydrofluoric acid solution, the projected portion of the gate spacer 52 a can be removed by an etching characteristic of the hydrofluoric acid while the exposed surface of the semiconductor substrate and the polysilicon layer pattern 44 a are cleaned.

[0048] Referring to FIG. 2G, a stopping layer 54 is continuously formed on the top portion of the polysilicon layer pattern 44 a, a sidewall of the gate spacer 52 b and the surface of the semiconductor substrate 40 . The stopping layer 54 indicates a finishing point of polishing in a planarization process of a subsequently formed insulating interlayer. Furthermore, the stopping layer 54 is used to self-align contacts that are formed in a subsequent process between the gate electrodes. The stopping layer 54 includes an insulating material, such as a nitride. Since the polysilicon layer pattern 44 a has a uniform thickness, the stopping layer 54 is uniformly formed on an upper surface of the respective polysilicon layer pattern 44 a.

[0049] Referring to FIGS. 2H and 2I , an insulating interlayer 56 is formed on the resultant, shown in FIG. 2 G, including the stopping layer 54 . Then, a planarization process is performed to expose the upper surface of the polysilicon layer pattern 44 a.

[0050] Referring firstly to FIG. 2 H, the insulating interlayer 56 is formed on the resultant, shown in FIG. 2 G, so that the resultant structure including the stopping layer 54 is covered with the insulating interlayer 56 . Then, the insulating interlayer 56 is chemically and mechanically polished to expose the stopping layer 54 , as shown in FIG. 2H . In order to precisely polish the insulating interlayer 56 in the chemical and mechanical polishing process, the polishing rate of the stopping layer 54 must be slower than the polishing rate of the insulating interlayer 56 . For this purpose, the polishing process is performed using a slurry that has a selectivity ratio of the insulating interlayer 56 to the stopping layer 54 , of about 4:1 to 10:1. After the chemical and mechanical polishing process, the stopping layer 54 remaining on the top portion of the respective polysilicon layer pattern 44 a has a uniform thickness.

[0051] Referring to FIG. 21 , the stopping layer 54 exposed in the chemical and mechanical polishing process is removed in order to expose the top portion of the polysilicon layer pattern 44 a. The stopping layer 54 remaining on the top portion of the polysilicon layer pattern and the insulating interlayer 56 surrounding it are then removed using a non-selective etching process to obtain a planar surface. The removal of the exposed stopping layer 54 remaining on top of the polysilicon layer pattern 44 a and the insulating interlayer 56 surrounding it can be carried out using a dry etching process or a wet etching process.

[0052] In the dry etching process, the removal of the exposed stopping layer 54 may be performed using a mixed gas of CHF ₃ and CF ₄ or a mixed gas of CHF ₃ and argon. In the wet etching process, on the other hand, the semiconductor substrate is dipped in a chemical including the phosphoric acid in order to remove the exposed stopping layer 54 .

[0053] When the exposed stopping layer 54 is removed in the wet etching process using the chemicals including the phosphoric acid, the stopping layer 54 a formed on the sidewall of the gate spacer 52 b is also partially removed. Therefore, the removal of the exposed stopping layer 54 is preferably performed in the dry etching process.

[0054] As described above, since the stopping layer 54 on the upper portion of the respective polysilicon layer pattern 44 a has a uniform thickness, the stopping layer 54 on the upper portion of the polysilicon layer pattern 44 a can be uniformly etched in the etching process. Furthermore, as the stopping layer 54 is uniformly etched, the polysilicon layer pattern 44 a also has a uniform thickness and a uniform exposed surface area.

[0055] Referring to FIG. 2J, a metal silicide layer 58 is selectively formed, using a standard photolithography technique, on the upper surface of the polysilicon layer pattern 44 a to obtain a gate electrode. The exposed portion of the polysilicon layer pattern 44 a is subjected to silicidation in order to form the metal silicide layer 58 after forming a metal layer on the polysilicon layer. The metal silicide layer includes any one of the materials selected from the group consisting of cobalt silicide (CoSi _x ), tungsten silicide (WSi _x ), titanium silicide (TiSi _x ) and tantalum silicide (TaSi _x ). The metal silicide layer 58 has a characteristic of decreasing the resistance of the gate electrode.

[0056] As the polysilicon layer pattern 44 a has a uniform exposed surface area, the metal silicide layer 58 also can be uniformly deposited across the wafer surface. Since the polysilicon layer pattern 44 a and the metal silicide layer 58 , which are provided as the gate electrode, are uniformly formed, the difference in the resistance between the gate electrodes across the wafer can be minimized. As a result, the reliability of the semiconductor device including the gate electrodes can be improved.

[0057] FIGS. 3A to 3 K illustrate sectional views of stages in a method of manufacturing a non-volatile memory device according to the second embodiment of the present invention.

[0058] Referring to FIG. 3A, a semiconductor substrate 100 comprised of silicon has an active area and a field area divided by a conventional isolation process. A silicon oxide film is grown on the semiconductor substrate 100 having the active area and the field area in order to form a gate oxide film (not shown) of a cell transistor, for an example, a tunnel oxide film. In the case of exposing the semiconductor substrate to atmosphere, a natural oxide film is formed on the semiconductor substrate because the semiconductor substrate is reacted with oxygen in the atmosphere. As described above, the natural oxide film is formed on the semiconductor substrate 100 . In the present embodiment, the gate oxide film (not shown) is further grown on the semiconductor substrate to a thickness of about 50-100 Å.

[0059] A conductive layer 102 that is to be used as a floating gate is deposited on the gate oxide film (not shown) to a thickness of about 2000 Åvia a low-pressure chemical vapor deposition (LPCVD) process. Preferably, the conductive layer 102 is comprised of polysilicon. Then, an N-type impurity is doped into the conductive layer 102 at a high density by one of the general doping processes such as POCl ₃ diffusion, ion implanting or insite doping.

[0060] A dielectric layer 104 , for example, an ONO (oxide film/nitride film/oxide film) layer is deposited on the conductive layer 102 . Particularly, after the conductive layer 102 is oxidized in order to grow a first oxide film having a thickness of about 100 Å, a nitride film is deposited on the first oxide film at a thickness of about 130 Å. Finally, a second oxide film is deposited on the nitride film to a thickness of about 40 Å to form the dielectric film 104 having a thickness of about 100-150 Å.

[0061] Continuously, a polysilicon layer 106 doped with an N-type impurity is formed on the dielectric layer 104 , which is to be used as a control gate. Insulation material, such as a nitride, is deposited on the polysilicon layer 106 in order to form a hard mask layer 108 , which is used as an etching mask in a subsequent process. The hard mask layer 108 is comprised of silicon nitride or silicon oxynitride. The required thickness of the hard mask layer 108 depends upon the layer formed under the hard mask layer 108 and a thickness of the underlying layer that is etched in a subsequent process. In the present embodiment, preferably, the hard mask layer 108 has a thickness of about 800-1500 Å.

[0062] Referring to FIG. 3 B, the hard mask layer 108 is selectively etched to expose the polysilicon layer 106 under the hard mask layer 108 , so that a hard mask pattern 108 a is formed. The gate electrode is subsequently formed below the hard mask pattern 108 a. That is, a photoresist pattern (not shown) is formed on an upper portion of the hard mask layer 108 . Then, the hard mask layer 108 is etched via a general photolithography process in which the photoresist pattern is used as an etching mask. As a result, the hard mask layer 108 becomes the hard mask pattern 108 a.

[0063] Referring to FIG. 3 C, the underlying films are subsequently etched via an anisotropic etching process in which the hard mask pattern 108 a is used as an etching mask in order to form a gate structure 110 in which the gate oxide pattern (not shown), the conductive layer pattern 102 a, the dielectric film pattern 104 a, the polysilicon layer pattern 106 a and the hard mask pattern 108 a are stacked. Then, using the gate structure 110 as an ion implant mask, an N-type impurity is implanted into an NMOS transistor area while a P-type impurity is doped into a PMOS transistor area, to form source/drain regions 112 having a low resistivity.

[0064] When the anisotropic etching process is performed to form the gate structure 110 , however, the upper surface of the hard mask pattern 108 a used as the etching mask is partially etched by an impact of the ion beam. In addition, the hard mask pattern 108 a may be non-uniformly etched according to the density of a peripheral pattern and a position of the semiconductor substrate on which the hard mask pattern is formed. Accordingly, after the etching process is performed, the hard mask pattern 108 a remaining on the top portion of the respective gate construction has a varying thickness at different locations on the wafer surface.

[0065] When the etching process is performed under a condition of the present embodiment, the thickness of the hard mask pattern 108 a is reduced by about 100-500 Å during the etching process as compared to the thickness thereof before the etching process. Furthermore, the hard mask pattern 108 a has a thickness variation of about 400-500 Å depending on the density of the peripheral pattern and the position of the hard mask pattern on the semiconductor substrate.

[0066] Referring to FIG. 3 D, an oxide film is formed on the gate structure 110 and the semiconductor substrate 100 and then the oxide film is anisotropically etched in order to form a gate spacer 114 on a sidewall of the gate structure 110 . Preferably, the gate spacer includes an oxide based insulating material. The gate spacer 114 including the oxide film prevents damage to the sidewall of the gate structure 110 during the subsequent processing.

[0067] Referring to FIG. 3 E, the hard mask pattern formed on the top portion of the gate structure 110 is removed to expose the upper surface of the polysilicon layer pattern 106 a.

[0068] The hard mask pattern 108 a can be removed using the phosphoric acid stripping process in which the hard mask pattern 108 a is dipped into the chemical solution including the phosphoric acid. When the hard mask pattern 108 a is removed, the polysilicon layer pattern 106 a under the hard mask pattern 108 a is exposed. The hard mask pattern 108 a may be removed by a dry etching process as well as the above phosphoric acid stripping process.

[0069] Since the surface of the semiconductor substrate 100 on which the gate structure 110 is not formed is exposed, the ion beam used for etching the hard mask pattern 108 a causes an impact damage on the surface of the semiconductor substrate 100 , resulting in process related defects including defects on the substrate surface. When the phosphoric acid stripping process is used for removing the hard mask pattern 108 a, the hard mask pattern 108 a can be effectively removed without having an effect on the underlying films or on the surface of the semiconductor substrate 100 .

[0070] When the hard mask pattern 108 a is removed, the top portion of the gate spacer 114 a that was around the hard mask pattern 108 a is projected above the polysilicon layer pattern 106 a.

[0071] Referring to FIG. 3 F, the top portion of the gate spacer 114 a that was around the hard mask pattern 108 a is removed in order to planarize an upper portion of the gate spacer 114 and the polysilicon layer pattern 106 a. In order to remove the projected portion of the gate spacer 114 a, the semiconductor substrate including the gate spacer 114 is immersed in the hydrofluoric acid (HF) solution for thirty seconds. When the semiconductor substrate is dipped in the hydrofluoric acid solution, the projected portion of the gate spacer 114 a can be removed while the surfaces of the semiconductor substrate 100 and the polysilicon layer pattern 106 a are cleaned due to the etching characteristic of the hydrofluoric acid (HF) solution. After the dip in the HF solution, the top of the remaining gate spacer 114 b is planar with the polysilicon layer pattern 106 a.

[0072] Referring to FIG. 3G, a stopping layer 116 is continuously formed on the top portion of the exposed polysilicon layer pattern 106 a, a sidewall of the gate spacer 114 b and the surface of the semiconductor substrate 100 . The stopping layer 116 indicates a finishing of polishing in a planarization process of a subsequently formed insulating interlayer. Furthermore, the stopping layer 116 is used to self-align contacts formed in a subsequent process between the gate electrodes. The stopping layer 116 is comprised of an insulating material, such as a nitride, to have a thickness of about 500-800 Å.

[0073] The stopping layer 116 is uniformly formed on an upper surface of the respective polysilicon layer pattern 106 a since the polysilicon layer pattern 106 a has a uniform thickness.

[0074] Referring to FIG. 3 H, an insulating interlayer 118 is formed on the stopping layer 116 to cover the resultant structure shown in FIG. 3G . For example, the insulating interlayer 118 may be formed by depositing a first insulating layer and a second insulating layer. The first insulating layer is formed by depositing a high density plasma (HDP) oxide to a thickness of about 5000-6000 Å and the second insulating layer is formed by depositing plasma enhanced-tetra-ethyl-ortho-silicate (PE-TEOS) oxide film on the first insulating layer to a thickness of about 4000-8000 Å. As the high-density plasma oxide film is used as the insulating layer, the oxide film is filled in gaps between the gate structures which are formed to be adjacent to each other.

[0075] Referring to FIGS. 3I and 3J , the structure in FIG. 3H is planarized so that the polysilicon layer pattern 106 a is exposed.

[0076] Referring firstly to FIG. 3 I, the insulating interlayer 118 is polished by a chemical and mechanical polishing (CMP) process until the stopping layer 116 under the insulating interlayer 118 is exposed. At this stage, the top surface of the remaining insulating interlayer 118 a is planarized with the top surface of the stopping layer 116 . Since the stopping layer 116 formed on the upper surface of the respective polysilicon layer pattern 106 a has a uniform thickness, the thickness of the stopping layer 116 has not changed significantly during the polishing process.

[0077] In order to precisely polish the insulating interlayer 118 in the chemical and mechanical polishing process, the polishing rate of the stopping layer 116 needs to be slower than the polishing rate of the insulating interlayer 118 . Therefore, the polishing process is performed using a slurry having a selectivity ratio of the insulating interlayer 118 to the stopping layer 116 , of about 4:1 to 10:1. When the slurry with such a high selectivity ratio is used for polishing the insulating interlayer 118 , the damage of the stopping layer 116 can be minimized. The thickness variation of the stopping layer 116 remaining on the polysilicon layer pattern 106 a can also be reduced which is caused by a varying pattern density at different locations, with the density of the patterns being small at the peripheral portion and the density of the patterns being large at the cell portion, and also due to variation in the polysilicon layer pattern thickness on the semiconductor substrate.

[0078] If the stopping layer 116 has a thickness of about 600 Å before the chemical and mechanical polishing process, the stopping layer 116 has a thickness of about 350-500 Å, depending on the density of the peripheral pattern and the position of the semiconductor substrate, after the insulating interlayer 118 is polished using the slurry having the selectivity ratio 4:1 of the insulating interlayer 118 with respect to the stopping layer 116 . That is, the maximum variation in the thickness of the stopping layer 116 is about 100-250 Å.

[0079] Referring now to FIG. 3 J, the stopping layer 116 formed on the upper surface of the polysilicon layer pattern 106 a is removed. When the stopping layer 116 is removed from the upper surface of the polysilicon layer pattern 106 a, the stopping layer 116 a only remains on the sidewall of the gate spacer 14 b. The removal of the stopping layer 116 can be performed using the dry etching process or the wet etching process.

[0080] In the dry etching process, the removal of the stopping layer 116 may be performed using a mixed gas of CHF ₃ and CF ₄ or a mixed gas of CHF ₃ and argon. In the wet etching process, on the other hand, the semiconductor substrate is dipped in a chemical solution including the phosphoric acid in order to remove the stopping layer 116 .

[0081] When the stopping layer 116 is removed via the wet etching process using the chemical solution including the phosphoric acid, the stopping layer 116 formed on the sidewall of the gate spacer 114 b is partially removed as the etchant penetrates into the sidewall of the gate spacer 114 b.

[0082] When a contact is formed between the gate electrodes after the gate electrodes are formed in a subsequent process, the stopping layer 116 a formed on the sidewall of the gate spacer 114 b can be used as a film for self-aligning the contacts. When the stopping layer 116 a is partially removed from the sidewall of the gate spacer 114 b, however, the process defects may be caused during the formation of the contact. Therefore, the stopping layer 116 is preferably removed in the dry etching process.

[0083] When the stopping layer 116 , formed on the upper surface of the polysilicon layer pattern 106 a, is removed via the dry etching process, the insulating interlayer 118 a around the stopping layer 116 is also etched together with the stopping layer 116 . The etchant used in this step does not have selectivity with respect to the stopping layer 116 and the insulating interlayer 118 a, resulting in a planar surface at the end of this etching step. In addition, when the etching of the stopping layer 116 formed on the upper surface of the polysilicon layer pattern 106 a is completed, plasma ions are forced to the upper surface of the polysilicon layer pattern 106 a thereby causing damage on the surface of the polysilicon layer pattern 106 a. Furthermore, as being impacted by the ions, the polysilicon layer pattern 106 a is etched to have a reduced thickness.

[0084] As described above, since the hard mask pattern 108 a is removed before the stopping layer 116 is formed, the stopping layer 116 formed on the respective polysilicon layer pattern 106 a has a uniform thickness. Therefore, the stopping layer 116 formed on the respective polysilicon layer pattern 106 a can be uniformly etched in the etching process. Accordingly, during the etching process a situation where the polysilicon layer pattern 106 a has a non-uniform thickness and a different exposed area due to its non-uniform thickness rarely arises.

[0085] Referring to FIG. 3K, a metal silicide layer 120 is selectively deposited on the exposed portion of the polysilicon layer pattern 106 a to form the gate electrode using a standard photolithographic technique. The metal silicide layer 120 may be formed using cobalt silicide CoSi _x , tungsten silicide WSi _x , titanium silicide TiSi _x , tantalum silicide TaSi _x , etc. The exposed portion of the polysilicon layer pattern 106 a is subjected to silicidation in order to form the metal silicide layer 120 (after forming a metal layer on the polysilicon layer). The metal silicide layer 120 can decrease the resistance of the gate electrode.

[0086] Since the metal silicide layer 120 is comprised of a metal material having a high conductivity, the metal silicide layer 120 has a great influence on the resistance of the gate electrode. Therefore, the metal suicide layer 120 must be uniformly formed on the respective polysilicon layer pattern 106 a so that the difference in the resistance of the gate electrodes is not generated between the gate electrodes.

[0087] As the polysilicon layer pattern 106 a has the uniformly exposed area, the silicidation of the exposed area of the polysilicon layer pattern 106 a is accomplished uniformly. As a result, the metal silicide layer 120 is formed uniformly. Therefore, the difference in the resistance of the gate electrodes can be minimized. Furthermore, the reliability of the non-volatile memory device can be improved. 1

[0088] Table 1 shows the thickness of the nitride films remaining on the polysilicon layer pattern after the chemical and mechanical polishing process was performed to expose the stopping layer in the respective non-volatile memory devices that were manufactured according to the conventional method and a method of the embodiment of the present invention. The nitride film in the conventional method includes the stopping layer and the hard mask pattern, where as in the preferred embodiments of the present invention, the nitride film is entirely constituted by the stopping layer.

[0089] As described above, the gate electrodes of the semiconductor device have a different resistance due to the non-uniform thickness of the nitride film remaining on the polysilicon layer pattern after the polishing process. Table 1 shows data of the thickness of the nitride film remaining at the cell area and peripheral area (referred to as “peri”) in the respective portions (upper portion, central portion, lower portion, left side portion and right side portion) of the semiconductor substrate. In Table 1, the unit of measure for the thickness is angstroms.

[0090] Referring to Table 1, data # 1 are values of the thickness of the nitride film that were measured at the respective portions on the semiconductor substrate according to the conventional method after the polishing process. The nitride film had the stopping layer and the hard mask pattern for the conventional method. The semiconductor substrate was polished using the slurry without the selectivity to the insulation interlayer with respect to the nitride film. Therefore, the nitride film has a non-uniform thickness and the thickness variation of the nitride film is very large across the semiconductor substrate surface. The maximum of the thickness variation across the wafer surface is 850 Å.

[0091] Data # 2 are values of the thickness of the nitride film that were measured at the respective portions on the semiconductor substrate according to the conventional art after performing the polishing process using a selective slurry. The nitride film included the stopping layer and the hard mask pattern. The semiconductor substrate was polished using the slurry having a selectivity ratio greater than 4:1 of the insulating interlayer to the nitride film. Therefore, the insulating interlayer was polished in the polishing process while the nitride film is polished only slightly. The nitride film according to data # 2 has a thickness greater than the nitride film according to data # 1 , while having a small variation of the thickness across the semiconductor substrate. The maximum thickness difference of the nitride film across the wafer according to data # 2 is 480 Å. However, the nitride film remaining on the wafer after polishing according to data # 2 is thicker as compared to data # 1 . Accordingly, there is a disadvantage because it takes a long time to remove the nitride film.

[0092] Data # 3 are values of the thickness of the nitride film that were measured at the respective portions on the semiconductor substrate according to an embodiment of the present invention after the polishing process. In the present invention, since the hard mask pattern was already removed before the stopping layer was formed, the nitride film only includes the stopping layer. The semiconductor substrate was polished using the slurry having a selectivity ratio greater than 4:1 of the insulating interlayer to the nitride film.

[0093] The nitride film according to data # 3 had a thickness thinner than the nitride film according to data # 1 and # 2 , while having a small variation of the thickness in the respective portions on the semiconductor substrate. The maximum difference in the thickness of the nitride film according to data # 3 is 190 Å. Therefore, it can be noted that the variation of the thickness of the nitride film is remarkably small in the present invention as compared to the conventional art.

[0094] In the present invention, since the hard mask pattern is removed before the stopping layer is formed as described above, it is possible to form the polysilicon layer pattern with a uniform thickness and, consequently, a uniform exposed area. Accordingly, the difference in the resistances between the gate electrodes across the wafer can be minimized and the reliability of the semiconductor device can be improved.

[0095] Although preferred embodiments of the present invention have been described, it is understood that the present invention should not be limited to these preferred embodiments but various changes and modifications can be made by one skilled in the art within the spirit and scope of the present invention as hereinafter claimed.