DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0053] FIGS. 1 A- 1 H show process steps for producing a semiconductor storage device according to a first embodiment of the present invention. FIGS. 4 A- 4 E show process steps for producing a semiconductor storage device according to a second embodiment. FIGS. 6 A- 6 I show process steps for producing a semiconductor storage device according to a third embodiment.

[0054] In these figures, reference numeral 1 denotes a silicon substrate, reference numeral 2 denotes a first interlayer dielectric, reference numeral 3 denotes a gate insulator, reference numeral 4 denotes a gate electrode of a MOS transistor, and reference numeral 5 denotes a source/drain region of the MOS transistor. Also, reference numeral 6 denotes a polysilicon plug, reference numeral 7 denotes a Ti (titanium) film as an adhesion layer, reference numeral denotes a tantalum silicon nitride film as a material of a barrier metal 8 a , reference numeral 9 denotes a silicon nitride film formed by a plasma enhanced CVD (chemical vapor deposition) method. Reference numeral 10 denotes an Ir (iridium) film as a material of a lower electrode 10 a of a capacitor, reference numeral 11 denotes a SBT film as a material of a ferroelectric film 11 a of the capacitor, reference numeral 12 denotes a Pt (platinum) film as a material of an upper electrode 12 a of the capacitor, reference numeral 13 denotes a titanium oxide film as a diffusion barrier film, and reference numeral 14 denotes a second interlayer dielectric. Also, reference numeral 15 denotes wiring, reference numeral 16 denotes a silicon nitride film formed by a low-pressure CVD method, and reference numeral 17 denotes an ozone TEOS (tetraethylorthosilicate)-NSG film.

[0055] [First Embodiment]

[0056] The following describes process steps of fabricating the semiconductor storage device according to the first embodiment with reference to FIGS. 1 A- 1 H.

[0057] First, using a CVD method, a silicon oxide film is formed as a first interlayer dielectric 2 on the silicon substrate 1 formed with the MOS transistor. Then, a contact hole of 0.6 μm in diameter is formed in the first interlayer dielectric 2 in a position on a source/drain region 5 of the MOS transistor. By the CVD method, polysilicon is deposited such that the contact hole is filled with polysilicon, which is then doped with phosphorus (P) for resistance reduction. Thereafter, the phosphorus-diffused polysilicon and the first interlayer dielectric 2 are planarized by CMP (Chemical Mechanical Polishing). As a result, a polysilicon plug 6 is formed ( FIG. 1A ).

[0058] Next, a Ti film 7 is formed to a thickness of 20 nm by a DC magnetron sputtering method. Then, tantalum silicon nitride (TaSiN) film 8 is formed to a thickness of 100 nm by a reactive DC magnetron sputtering method using an alloy of tantalum and silicon as a target ( FIG. 1B ). The sputtering conditions are: a DC power of 2.0 kW, a substrate temperature of 500° C., and sputtering gases of Ar and N ₂ at a flow rate of 24 sccm and 16 sccm, respectively. After the sputtering process, a heat treatment is performed at a temperature of 600° C. and in an N ₂ ambient to densify the TaSiN film 8 . Then, using a known photolithography and dry etching technique, the TaSiN film 8 and the Ti film 7 are patterned into a barrier metal 8 a and an adhesion layer 7 a , each 1.2 μm square, which entirely cover the upper surface of the polysilicon plug 6 . For the dry etching process, an ECR (Electron Cyclotron Resonance) etcher is used. Next, a silicon nitride (P—SiN) film 9 is deposited to a thickness of 200 nm on the barrier metal 8 a and the first interlayer dielectric 2 by the plasma enhanced CVD method ( FIG. 1C ). The P—SiN film 9 is formed at a substrate temperature of 400° C.

[0059] Next, the P—SiN film 9 is abraded by the CMP method such that a top surface of the TaSiN barrier metal 8 a is exposed and that a planarized surface is obtained ( FIG. 1D ). Instead of the P—SiN film 9 , a silicon oxide nitride (P—SiON) film may be deposited to a film thickness of 200 nm at a substrate temperature of 400° C. by the plasma enhanced CVD method.

[0060] Next, an iridium (Ir) film 10 , which will be formed into a lower electrode, is deposited to a thickness of 150 nm by the DC magnetron sputtering method. Then, a ferroelectric film 11 is formed. In this embodiment, an SrBi ₂ Ta ₂ O ₉ (SBT) film 11 is formed as the ferroelectric film in the following manner. First, an organic metal solution containing metal elements of Sr, Bi and Ta is applied onto the Ir film 10 by spin coating, and then dried. Then, the resulting film is annealed for crystallization for 30 minutes at a temperature of 700° C. in an O ₂ ambient and under a normal pressure. These steps are repeated until a desired film thickness is obtained. The composition ratio of the elements in the organic metal solution is Sr:Bi:Ta=0.8:2.4:2.0, and the final film thickness of the SBT film 11 is 150 nm. After the SBT film 11 has been completed, a platinum (Pt) film 12 is deposited to a film thickness of 100 nm by the DC magnetron sputtering ( FIG. 1E ). Then, the Pt film 12 is patterned into an upper electrode 12 a by a known photolithography and dry etching technique ( FIG. 1F ), and subsequently the films 11 and 10 are patterned into a ferroelectric 11 a and an Ir lower electrode 10 a of a capacitor by a known photolithography and dry etching technique ( FIG. 1G ). Note that after etching the Pt film 12 , a heat treatment is performed for 30 minutes as an electrode annealing process at a temperature of 700° C. in an O ₂ ambient. The size of the Ir film or lower electrode 10 a is large enough to cover the entire top surface of the TaSiN barrier metal 8 a , namely it is larger than the size of the barrier metal 8 a . In this embodiment, the Ir lower electrode 10 a has a size of 4 μm by 4 μm. In processing the Ir film 10 into the Ir lower electrode 10 a , the P—SiN film 9 , or a liner, will also be etched so that the first interlayer dielectric 2 is exposed. The first interlayer dielectric 2 , however, does not necessarily need to be exposed.

[0061] According to the conventional method as mentioned above, it is necessary to stop the etching at an interface between the Ir film 10 , which will be a lower electrode, and the TaSiN film 8 , which will be a barrier metal. In contrast, according to the embodiment, if the Ir film 10 is overetched, not the TaSiN film 8 but the P—SiN film 9 is etched. Accordingly, etch residue occurring in the etching process of the Ir film 10 is easily removable by a chemical liquid. The P—SiN film 9 thus patterned will serve as an anti-oxygen-permeation film for preventing the TaSiN barrier metal 8 a from being oxidized during a ferroelectric-recovery heat treatment process that is performed later. To this end, the P—SiN film 9 around the barrier metal has preferably a wall thickness, or a thickness in the horizontal direction, of from 0.1 to 2.0 μm inclusive. If the wall thickness is below 0.1 μm, the P—SiN film 9 becomes permeable to oxygen. If the wall thickness is over 0.2 μm, the device size will conspicuously increase.

[0062] After the above etching process, a titanium oxide (TiO ₂ ) film 13 as a diffusion barrier film is deposited to a thickness of 25 nm by sputtering and then the film is processed into a pattern to cover or envelope almost the entire ferroelectric capacitor. After that, a second interlayer dielectric 14 is deposited to a thickness of 300 nm. This second interlayer dielectric 14 is an ozone TEOS-NSG film like the first interlayer dielectric. Then, a contact hole leading to the upper electrode 12 a of the ferroelectric capacitor is formed in the second interlayer dielectric 14 and TiO ₂ film 13 by photolithography and dry etching.

[0063] Next, a heat treatment is performed to recover the ferroelectric. The heat treatment conditions are: a temperature of 700° C., a time of 30 minutes, and an O ₂ ambient under a normal pressure. In the fabrication process for the conventional semiconductor storage device, after the ferroelectric capacitor has been formed, it is difficult to perform a high temperature heat treatment in the O ₂ ambient for the following reason. That is, the barrier metal tends to be oxidized from its sides by oxygen permeating into the barrier metal through the second interlayer dielectric 14 . The oxidation of the barrier metal invites the problems of poor conduction, hillocks, and film detachment. In contrast, with the arrangement of the present invention, the P—SiN film 9 suppresses the permeation of oxygen, so that it is much less possible for the barrier metal to be oxidized. Accordingly, in this first embodiment, occurrence of the poor conduction and/or the film detachment is well suppressed.

[0064] After the contact hole is made, wiring 15 of an Al-based material is formed ( FIG. 1H ).

[0065] FIG. 2 shows the hysteresis characteristic of a ferroelectric capacitor, formed through the above steps, in which the P—SiN film is used as the anti-oxygen-permeation film. Also, FIG. 3 shows the hysteresis characteristic of a ferroelectric capacitor, formed through the above steps, in which a P—SiON film is used as the anti-oxygen-permeation film. In both cases, the hysteresis curves show good symmetry, which proves that considerably good results were obtained.

[0066] (Second Embodiment)

[0067] The fabrication process steps for a semiconductor storage device according to a second embodiment of the invention will be described below with reference to FIGS. 4 A- 4 E.

[0068] First, through process steps similar to the process steps adopted in the first embodiment (see FIGS. 1 A- 1 C), a TaSiN barrier metal 8 a and a Ti adhesion layer 7 a , each 1.2 μm square, are formed in such a manner that these films 7 a and 8 a cover an entire top surface of the polysilicon plug 6 . Thereafter, a SiN film 16 is deposited to a thickness of 0.03 μm on the barrier metal 8 a and the first interlayer dielectric 2 by a low pressure CVD method at a substrate temperature of 700° C. Then, an ozone TEOS-NSG film 17 is formed to a thickness of 200 nm ( FIG. 4A ). The film thickness of the SiN film 16 formed by the low pressure CVD method is preferably 0.03 μm or more. If the SiN film 16 has a film thickness of below 0.03 μm, the film 16 is permeable to oxygen. An insulating film to be formed on the SiN anti-oxygen-permeation film 16 is not limited to the ozone TEOS-NSG film 17 , but may be of any type so far as the insulating film has a smaller film stress than the SiN anti-oxygen-permeation film 16 does, or has a film stress acting in a direction opposite to a direction in which a film stress of the SiN film 16 acts.

[0069] Next, the ozone TEOS-NSG film 17 and the SiN film 16 are abraded by CMP until the barrier metal is exposed and the wafer surface is planarized.

[0070] Next, an Ir film 10 , which will be a lower electrode, is formed to a thickness of 150 nm by the DC magnetron sputtering method. In the following process, a ferroelectric film 11 is formed. In this embodiment, an SrBi ₂ Ta ₂ O ₉ (SBT) film 11 is formed in a manner same as the first embodiment. The final thickness of the SBT film 11 is 150 nm. After the SBT film 11 is formed, a platinum (Pt) film 12 is deposited to a film thickness of 100 nm by the DC magnetron sputtering ( FIG. 4B ). Then, the Pt film 12 is patterned into an upper electrode 12 a of a ferroelectric capacitor by a known photolithography and dry etching technique ( FIG. 4C ), and subsequently the films 11 and 10 are patterned into a SBT ferroelectric 11 a and an Ir lower electrode 10 a of the ferroelectric capacitor by a known photolithography and dry etching technique ( FIG. 4D ). Note that after etching the Pt film 12 , a heat treatment is performed for 30 minutes as an electrode annealing process at a temperature of 700° C. in an O ₂ ambient. The size of the Ir lower electrode 10 a is larger than the size of the barrier metal 8 a . In this embodiment, the Ir lower electrode 10 a is 4 μm square. In processing the Ir film 10 into the Ir lower electrode 10 a , the ozone TEOS-NSG film 17 and SiN film 16 , namely liners, are also etched away so that the first interlayer dielectric 2 is exposed. The resulting SiN film 16 is generally L-shaped in section. In the second embodiment, overetching of the Ir film 10 results in the etching of the TEOS-NSG film 17 and SiN film 16 , and not the etching of the barrier metal 8 a , similarly to the first embodiment. Accordingly, etch residue occurring when etching the Ir film 10 can be easily removed by a chemical liquid.

[0071] After the above etching process, a titanium oxide (TiO ₂ ) film 13 as a diffusion barrier film is deposited to a thickness of 25 nm by sputtering and then the film is processed into a pattern to cover almost the entire ferroelectric capacitor. After that, a second interlayer dielectric 14 is deposited to a thickness of 300 nm. This second interlayer dielectric 14 is an ozone TEOS-NSG film like the first interlayer dielectric. Then, a contact hole leading to the upper electrode 12 a of the ferroelectric capacitor is formed in the second interlayer dielectric 14 and TiO ₂ film 13 by photolithography and dry etching. After that, wiring 15 of an Al-based material is formed ( FIG. 4E ).

[0072] In the second embodiment, similar to the first embodiment, permeation of oxygen is suppressed by the SiN film 16 , so that poor conduction and/or film detachment caused from the oxidation of the barrier metal is suppressed.

[0073] FIG. 5 shows the hysteresis characteristic of the ferroelectric capacitor formed through the above steps. The hysteresis curve in FIG. 5 shows good symmetry, which proves that considerably good results were obtained.

[0074] [Third Embodiment]

[0075] The following describes process steps of fabricating the semiconductor storage device according to a third embodiment with reference to FIGS. 6 A- 6 I.

[0076] First, using a CVD method, a silicon oxide film is formed as a first interlayer dielectric 2 on a silicon substrate 1 formed with a MOS transistor. Then, a contact hole of 0.6 μm in diameter leading to a source/drain region 5 of the MOS transistor is formed in the first interlayer dielectric 2 by lithography and dry etching. Then, by the CVD method, the contact hole is filled with polysilicon, which is then doped with phosphorus (P) for resistance reduction. Thereafter, the phosphorus-diffused polysilicon and the first interlayer dielectric 2 are planarized by CMP. As a result, the polysilicon plug 6 as a conductive contact plug is completed ( FIG. 6A ).

[0077] Next, a Ti film 7 serving as an adhesion layer is deposited to a thickness of 20 nm. Then, a TaSiN film 8 is formed to a thickness of 50 nm by reactive sputtering using an alloy of tantalum and silicon as a target ( FIG. 6B ).

[0078] Then, using a known photolithography and dry etching technique, the TaSiN film 8 and the Ti film 7 are continuously patterned into a barrier metal 8 a and an adhesion layer 7 a , each 1.2 μm square, which are positioned directly on the polysilicon plug 6 . Next, an iridium (Ir) film 10 , which is a lower electrode material, is formed on the barrier metal 8 a and the first interlayer dielectric 2 to a thickness of 300 nm by sputtering ( FIG. 6C ).

[0079] Next, the Ir film 10 is planarized using the CMP technique such that the Ir film of a thickness of 200 nm remains over the barrier metal 8 a ( FIG. 6D ).

[0080] Next, an SBT film 11 , namely a ferroelectric material, is deposited to a thickness of 150 nm by spin coating. Subsequently, a platinum (Pt) film 12 , namely an upper electrode material, is deposited to a film thickness of 100 nm by sputtering ( FIG. 6E ).

[0081] Then, the Pt film 12 is patterned into an upper electrode 12 a , 1.2 μm square, of a ferroelectric capacitor by lithography and dry etching ( FIG. 6F ), and then a heat treatment is performed for 30 minutes as an electrode annealing process at a temperature of 700° C. in an O ₂ ambient ( FIG. 6F ).

[0082] Then, by lithography and dry etching, the SBT film 11 and the Ir film 10 are continuously formed into a ferroelectric 11 a and a lower electrode 10 a of an inverted-U shape in section such that the lower electrode 10 a covers the entire top surface and the entire side surfaces of the barrier metal 8 a of TaSiN. A lower portion 10 b of the lower electrode 10 a which covers the side surfaces of the barrier metal 8 a and the adhesion layer 7 a serves as an anti-oxygen-permeation film. In this manner, a ferroelectric capacitor including the Pt upper electrode 12 a , the capacitor ferroelectric 11 a , and the Ir lower electrode 10 a is formed on the silicon plug 6 , with the TaSiN film 8 a disposed between the plug 6 and the lower electrode 10 a ( FIG. 6G ). Note that the size of the lower electrode 10 a is required to be large enough to cover at least the top surface of the TaSiN barrier metal 8 a , namely, the upper Ir film portion 10 a is required to be larger than the size of the barrier metal 8 a . In this embodiment, the Ir lower electrode 10 a has a size of 4 μm by 4 μm.

[0083] According to the conventional method as mentioned above, it is necessary to stop the etching at an interface between the Ir film, which will be a lower electrode, and the TaSiN film, which will be a barrier metal. According to the embodiment, however, if the Ir film 10 is overetched during the process of etching the Ir film, not the TaSiN film 8 but the first interlayer dielectric (silicon oxide film) 2 is etched. Accordingly, etching residue occurring in the etching process of the Ir film 10 can be easily removed by a chemical liquid.

[0084] In this embodiment, the lower electrode 10 a covering entirety of the upper and side surfaces of the TaSiN film (barrier metal) 8 a serves both as a lower electrode and as an anti-oxygen-permeation film for preventing the TaSiN film 8 a from being oxidized during a ferroelectric-recovery heat treatment process that is performed later.

[0085] After the above etching process, a titanium oxide (TiO ₂ ) film 13 as a diffusion barrier film is deposited to a thickness of 25 nm by reactive sputtering and then the film is processed into a pattern to cover almost the entire ferroelectric capacitor. After that, a second interlayer dielectric 14 of silicon oxide is deposited to a thickness of 300 nm by the CVD technique. Then, a contact hole 0.7 μm diameter leading to the Pt upper electrode 12 a of the ferroelectric capacitor is formed in the second interlayer dielectric 14 and TiO ₂ film 13 by lithography and dry etching ( FIG. 6H ).

[0086] Next, a heat treatment is performed to recover the SBT film 11 a serving as a capacitor ferroelectric. The heat treatment conditions are: a temperature of 700° C., a time of 30 minutes, and an O ₂ ambient under a normal pressure. In the case of fabricating a semiconductor storage device with the conventional structure as mentioned above, it is difficult to perform a high temperature heat treatment in the O ₂ ambient after the ferroelectric capacitor has been formed, for the following reason. That is, the barrier metal is oxidized at its side surfaces by oxygen permeating into the barrier metal through the second interlayer dielectric, resulting in occurrence of the poor conduction and the film detachment. In contrast, with the arrangement of the present invention, the Ir film lower portion, or anti-oxygen-permeation film 10 b which is unified with the lower electrode 10 a , suppresses the permeation of oxygen into the TaSiN film (namely, barrier metal) 8 a , so that the barrier metal 8 a is hardly oxidized.

[0087] Finally, wiring 15 of an Al-based material is formed ( FIG. 6I ).

[0088] In the first through third embodiments, an SBT film is used as the ferroelectric material. The ferroelectric film is not limited to this material, but may also be formed of a material constituting a ferroelectric stratiform perovskite structure containing Bi or a material constituting a ferroelectric perovskite structure containing Pb, such as, for example, (Pb _x La _1−x ) (Zr _y Ti _1−y ) O ₃ (0≦X, Y≦1), Bi ₄ Ti ₃ O ₁₂ , BaMgF ₄ . Also, in the first to third embodiments the barrier metal is formed of TaSiN, although this material is not limitative and it is also possible to use other materials, such as TiN, TiAlN, TiSiN, WSiN, that can prevent a reaction between the conductive contact plug material and the lower electrode material from occurring. Furthermore, although the first interlayer dielectric is formed of a silicon oxide in the first to third embodiments, alternatively it may be formed of a silicon nitride film or a multi-layered film of a silicon oxide film and a silicon nitride film.

[0089] The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.