DETAILED DESCRIPTION OF THE INVENTION INCLUDING THE PREFERRED EMBODIMENT

[0032] EEPROM cells of the stacked gate type shown in FIG. 1 are used in a variety of different types of flash array architectures where they are subject to disturbance of the floating gate potential during CISEI page mode programming operations, and may also suffer disturbance of the floating gate potential during read operations.

[0033] A common ground NOR array 100 is shown in FIG. 3 . Simplified for clarity, the array 100 illustratively is arranged in M rows and N columns of memory cells, and each individual memory cell 111 - 114 , 121 - 124 , 131 - 134 and 141 - 144 is a stacked gate type of cell such as that shown in FIG. 1 but preferably having a halo implant in a manner well known in the art. While a variety of other type of nonvolatile memory cells using floating gates and other classes of nonvolatile memory cells using charge trapping like the MNOS (Metal-Nitride-Oxide-Semiconductor) device to set the threshold voltage V _T of the cell may also be used, the use of the stacked gate type cell permits the memory array 100 to have a high integration density. Indeed, the integration density of flash EEPROM memory using the stacked gate structure is quite large, even in a NOR memory architecture. For example, memory fabricated using 0.18 μm processes can have storage capacity as large as 128 megabits, with a single row having as many as 5000 memory cells.

[0034] In the illustrative memory array 100 , the memory cells reside at respective row-column cross points and large groups of the memory cells share common source lines. The row lines R ₁ , R ₂ , . . . , R _(M−1) and R _M are the word lines of the memory array 100 , and the column lines C ₁ , C ₂ , . . . , C _(N−1) and C _N are the bit lines of the memory array 100 . Word line R ₁ is connected to the control gates of transistors 111 , 112 , 113 and 114 . Similarly, word line R ₂ is connected to the control gates of transistors 121 , 122 , 123 and 124 ; word line R _(M-1) is connected to the control gates of transistors 131 , 132 , 133 and 134 ; and word line R _M is connected to the control gates of transistors 141 , 142 , 143 and 144 . Column line C ₁ is connected to the drains of transistors 111 , 121 , 131 and 141 . Similarly, column line C ₂ is connected to the drains of transistors 112 , 122 , 132 and 142 ; column line C _(N-1) is connected to the drains of transistors 113 , 123 , 133 and 143 ; and column line C _(N) is connected to the drains of transistors 114 , 124 , 134 and 144 . Additional operating voltage is brought to groups of the memory cells on the source lines S ₁ , and S _(M/2) , which are connected to the sources of, respectively, transistors 111 - 114 and 121 - 124 , and transistors 131 - 134 and 141 - 144 . The source lines S ₁ and S _(M/2) may be commonly connected, connected in groups, or individually controllable, as desired. For purposes of clarity, a page of the memory array 100 is considered a row of memory cells, although a page may be differently defined for other memory array architectures. For purposes of clarity, the sector aspect of the architecture is not shown, although a sector illustratively has 32, 64 or more word lines. Illustratively, the memory array 100 has a storage capacity in the range of 16 to 128 Mb, with a single row having as many as 2K, 4K or even 8K memory cells. It will be appreciated that more complex arrangements such as sub-bit lines and substrate block isolation may be used as desired to enhance certain aspects of the memory, in a manner well known in the art.

[0035] A great many array architectures and nonvolatile semiconductor memory devices have been developed based on virtual ground contactless array architecture that can achieve even higher memory density levels than the NOR array, as exemplified by the following patents: U.S. Pat. No. 6,175,519, issued Jan. 16, 2001 to Lu et al.; U.S. Pat. No. 5,959,892, issued Sep. 28, 1999 to Lin et al.; U.S. Pat. No. 5,646,886, issued Jul. 8, 1997 to Brahmbhatt; U.S. Pat. No. 5,418,741, issued May 23, 1995 to Gill; and U.S. Pat. No. 5,060,195, issued Oct. 22, 1991 to Gill et al.

[0036] FIG. 4 shows a portion of the core of a simple virtual ground contactless array architecture 200 that uses a cross-point array configuration defined by, illustratively, buried n+ diffusions 210 , 211 , 212 , 213 and 214 that form the bit lines and source lines BL ₊₂ , BL ₊₁ , BL ₀ , BL ₋₁ , and BL ₋₂ , and WSi ₂ /Poly control gate wordlines 220 , 230 and 240 , or WL ₊₁ , WL ₀ and WL ₋₁ . Due to elimination of the common ground line and the drain contact in each memory cell, extremely small cell size is realized. Programming, erasing and reading of the memory cells is obtained by the use of asymmetrical CISEI-programmed floating gate transistors 221 - 224 , 231 - 234 , and 241 - 244 , and suitable source and drain decoding. Various well know measures may be taken to improve performance, such as the use of metal lines to periodically connect to the bit lines to reduce bit line resistance, the use of block select transistors to control the various voltages on segmented bit lines, and so forth.

[0037] In practice, memory arrays such as the arrays 100 and 200 are organized into bytes and pages and redundant rows (not shown), which may be done in any desired manner. Complete memories include well known elements such as sense amplifiers, pull-up circuits, word line amplifiers, sense amplifiers, decoders, and voltage circuits, which are omitted from FIGS. 3 and 4 for clarity.

[0038] A variety of processes for fabricating arrays of memory cells, including halo-implanted stacked gate cells, are well known in the art. For example, one suitable process for fabricating a NOR array of stacked gate cells such as shown in FIG. 1 is the ETOX™ memory technology, which is widely described in the literature, including various publications of Intel Corporation of Santa Clara, Calif., and which is available as a fabrication service from various semiconductor device manufacturers. Virtual ground processes are widely described in the literature and are available as fabrication services from various semiconductor device manufacturers, including National Semiconductor Corporation of Santa Clara, Calif., and Macronix International Co., Ltd. of Hsinchu, Taiwan.

[0039] Preferably, the memory cells in the illustrative arrays 100 and 200 are designed to be erased using Fowler-Nordheim (“FN”) tunneling, and programmed using channel-initiated secondary electron injection (“CISEI”). Advantageously, the use of CISEI programming allows a shorter channel length, which enables a smaller cell size. Advantageously, CISEI programming is significantly faster on a single cell basis than FN tunneling. Advantageously, the use of FN tunneling through the channel area for erase allows single or multiple pages to be erased with low relatively low power. An illustrative stacked gate halo-implanted transistor for the memory arrays 100 and 200 has the following exemplary basic characteristics: a grown tunnel oxide having a thickness of about 9 nm to 10 nm, an oxide-nitride-oxide (“ONO”) insulator between the control gate and the floating gate having an effective thickness of about 14 nm to 16 nm, a phosphorus doped polysilicon floating gate having a thickness of about 160 nm, a p-well peak doping and depth of about 8×10 ¹⁷ cm ⁻³ and 1.8 μm respectively, an n-well peak doping and depth of about 1×10 ¹⁷ cm ³ and 4 μm respectively, source and drain peak doping and depth of about 1×10 ²¹ cm ³ and 0.15 μm respectively, a p-type halo implant of Boron under the condition of 25 KeV, 5×10 ¹³ cm ⁻³ , a 15° tilt, and quad rotation, a channel width in the range of 0.15 μm to 0.25 μm, and a channel length in the range of 0.25 μm to 0.35 μm. It will be appreciated that these characteristics are illustrative, and may vary depending on the application and the fabrication process. In particular, transistors designed for CISEI programming are optimized in various ways know in the art, such as by using thin oxides, heavily doped junctions, and shallow junctions; see, e.g., J. D. Bude et al., EEPROM/Flash Sub 5.0V Drain-Source Bias Hot Carrier Writing, IEDM Technical Digest, 1995, p. 989-991.

[0040] Memory array programming operations for CISEI-programmed serial flash memory may be performed on successive sets of multiple bits, and preferably on a multiple byte basis with all the bits of multiple bytes being programmed simultaneously, and an entire pate of memory being programmed in successive groups of bytes. Memory array erase operations preferably are performed on multiple pages, one or more selected sectors, or the entire memory array. The selected memory cells for these memory operations are accessed by placing appropriate voltages on the word, bit and source lines of the selected memory cells, as well as on the diffusion wells in which the selected memory cells reside. The non-selected cells have different combinations of voltages, including in some cases word, bit and source lines that are brought to ground potential or left floating, which prevent the operation from occurring on them.

[0041] Consider, for example, the NOR array 100 . All of the transistors 111 - 114 are erased simultaneously by placing an erase select voltage on the word line R ₁ , an erase support voltage on all of the column lines C ₁ , C ₂ , C _(N-1) and C _N , and an erase support voltage on the p-well in which the channel is formed. Any suitable technique may be used for erase convergence. If for purposes of illustration one does not wish to erase the transistors 121 - 124 , 131 - 134 and 141 - 144 , the word lines are brought to ground potential. As another example, the transistors 111 - 114 are selected for programming by placing a program select voltage on the word line R ₁ , and grounding the source line S ₁ . The column lines C ₁ , C ₂ , C _(N-1) and C _N , carry a program support voltage or ground potential, depending on the data to be programmed into the memory array 100 . If for purposes of illustration one does not wish to program the transistors 121 - 124 , 131 - 134 and 141 - 144 , the word lines R ₂ , . . . , R _(M-1) and R _M would normally be brought to ground potential. It will be appreciated that the voltage levels depend on not only the type of memory cell, but also on the specific characteristics of the stacked gate memory cell. For example, a reduction in the oxide thickness between the floating gate and the channel permits reductions in the source-drain voltage.

[0042] As another example, consider the virtual ground array 200 . Access to individual memory cells on a selected word line for reading and programming is obtained by applying appropriate voltages to the bit lines to avoid disturbing the threshold voltage of the cell adjacent to and on the same word line with the cell being read or programmed, in a manner well known in the art. For example, memory cell 232 is accessed for reading or programming by bringing the word line 230 high, the bit line 211 (BL ₊₁ ) high, and the bit line 212 (BL ₀ ) low. Disturbance of the threshold voltage of the adjacent cells 231 and 233 is avoided by bringing the bit line 210 (BL ₊₂ ) high and the bit line 213 (BL ₀ ) low.

[0043] Generally, the voltages used for CISEI cells are lower than the voltages used in conventional CHE cells. The channel current is sustained in each cell to be programmed by bring its source to ground potential and its drain to a program support voltage of less than about a positive 4 volts. Sufficient hot electron injection is realized by applying a negative bias to the substrate of less than about 3 volts (absolute value) and preferably between about minus 2.5 and minus 1.5 volts. The voltage levels are suitable for the stacked gate structure of FIG. 1 having a halo implant in a manner well known in the art, although it will be appreciated that the voltage levels depend on not only the type of memory cell, but also specific characteristics of the stacked gate memory cell. For example, a reduction in the oxide thickness between the floating gate and the channel permits reduction in the negative substrate bias as well as reductions in the source-drain voltage. In an event, relatively fast programming (about 10 μsec or less to reach a high V _T of 5.5V) can be achieved with low programming current (about 110 μA or less per cell), thereby making feasible simultaneous multiple byte program operation for page mode flash memory as well as non-page mode flash memory.

[0044] We have found that flash memory that uses CISEI for programming multiple bytes and entire pages suffers disturbance of the floating gate potential during programming operations in the memory cells controlled by the unselected word lines and sharing the same bit line or bit lines as the cell or cells being programmed. Memory cells in the memory arrays 100 and 200 are impressed with four different sets of voltages during programming, two sets being impressed on the selected cells depending on the whether data is being programmed therein, and the other two sets being impressed on unselected cells depending on their location in the memory array. These various sets of voltages are illustrated in FIG. 5 , FIG. 6 , FIG. 7 and FIG. 8 for the NOR memory array 100 , but are applicable in principle to other types of arrays such as the virtual ground array 200 .

[0045] FIG. 5 shows illustrative voltages on a selected memory transistor that is being programmed: the gate voltage V _G =8V, the source voltage V _S =0V, the drain voltage V _D =4V and the p-well substrate voltage V _P =−2V. Majority carriers flow in the channel, as indicated by the arrow with the black arrowhead. Additionally, channel hot electrons and secondary hot electrons are generated and injected into the floating gate, as indicated by the arrows with the white arrowheads. The resulting threshold voltage is illustratively V _T =5.5V. This is a satisfactory condition.

[0046] FIG. 6 shows illustrative voltages on a selected memory transistor that is not being programmed: the gate voltage V _G =8V, the source voltage V _S =0V, the drain voltage V _D =0V and the p-well substrate voltage V _P =−2V. A similar condition exists in the virtual ground array 300 , except that the source and drain of the memory cell adjacent the memory cell being programmed are pulled up. No channel current flows, and no channel hot electrons or secondary hot electrons are generated. This is a satisfactory condition.

[0047] FIG. 7 shows illustrative voltages on a non-selected memory transistor that shares a bit line with a selected memory transistor that is being programmed: the gate voltage V _G =0V, the source voltage V _S =0V, the drain voltage V _D =4V, and the p-well substrate voltage V _P =−2V. Some majority carrier flow exists in the channel, as indicated by the arrow with the black arrowhead. Channel hot electrons and secondary hot electrons are generated, as indicated by the arrows with the white arrowheads. Since the control gate is at zero potential, it does not attract the hot electrons. However, some of the hot electrons will nonetheless become injected into the floating gate after a prolonged time, thereby disturbing the erased state of this transistor. Although the effect is small for each programming operation, the cumulative effect for a very large and very dense memory array can be sufficiently large to raise the transistor's threshold voltage V _T so that it reads like a programmed cell. This is an unsatisfactory condition, and is found in the memory arrays 100 and 200 .

[0048] FIG. 8 shows illustrative voltages on a non-selected memory transistor that shares a bit line with a selected memory transistor that is not being programmed: the gate voltage V _G =0V, the source voltage V _S =0V, the drain voltage V _D =0V and the p-well substrate voltage V _P =−2V. No channel current flows, and no channel hot electrons or secondary hot electrons are generated. This is a satisfactory condition.

[0049] The unsatisfactory condition illustrated in FIG. 7 is improved by placing a negative bias on the gates of at least the unselected transistors having differential voltages on their sources and drains. An illustrative value is about minus 2 volts, although the precise voltage depends on the type of memory transistor and its specific characteristics. The various sets of illustrative voltages that result are shown in FIG. 9 and FIG. 10 .

[0050] FIG. 9 shows illustrative improved voltages on a non-selected memory transistor that shares a bit line with a selected memory transistor that is being programmed: the gate bias voltage V _G =−2V, the source voltage V _S =0V, the drain voltage V _D =4V, and the p-well substrate voltage V _P =−2V. Some majority carrier flow exists in the channel, as indicated by the arrow with the black arrowhead. Channel hot electrons and secondary hot electrons are generated, as indicated by the arrows with the white arrowheads. However, since the control gate is at a negative bias, it repels the hot electrons and relatively few become injected into the floating gate. The erased state of this transistor is not significantly disturbed, even if the transistor remains unselected for a great number of programming operations common for a very large and very dense memory array. This is a satisfactory condition.

[0051] FIG. 10 shows illustrative improved voltages on a non-selected memory transistor that shares a bit line with a selected memory transistor that is not being programmed: the gate bias voltage V _G =−2V, the source voltage V _S =0V, the drain voltage V _D =0V, and the p-well substrate voltage V _P =−2V. No channel current flows, and no channel hot electrons or secondary hot electrons are generated. The negative bias on the gate has no adverse effect. This is a satisfactory condition.

[0052] Exemplary program characteristics are shown in FIGS. 15 and 16 . FIG. 15 is a graph of threshold voltage vs. time that shows program speed with different values of V _G (points corresponding to V _G =6V are marked by the symbol ⋄, points corresponding to V _G =7V are marked by the symbol ¤, and points corresponding to V _G =8V are marked by the symbol Δ), and indicates that cells can be programmed to V _T ≧5.5V within about 10 μsec with V _G =7V, V _D =4V, and V _P =−3V. FIG. 16 is a graph of threshold voltage vs. time that shows program speed with different values of V _P (points corresponding to V _P =−2V are marked by the symbol ⋄, points corresponding to V _P =−3V are marked by the symbol ¤, and points corresponding to V _P =4V are marked by the symbol Δ), and indicates that cells can be programmed to V _T ≧5.5V within about 10 μsec with V _G =8V, V _D =4V, and V _P =−2V. FIGS. 17 - 19 are graphs of drain current vs. drain voltage, and shows program current with different values of V _P (points corresponding to V _P =−1V are marked by the symbol ⋄, points corresponding to V _P =−2V are marked by the symbol ¤, and points corresponding to V _P =−3V are marked by the symbol Δ) for fixed V _G of 6V ( FIG. 17 ), 7V ( FIG. 18 ), and 8V ( FIG. 19 ). With V _G =7V and V _P =−2V, a program current of about 110 μA is achievable. Hence, for flash memory with 8 bits per byte, the simultaneous programming of all of the bits of up to 4 bytes is feasible, requiring less than about 4 mA of programming current. However, depending on the fabrication process, even less programming current per cell is achievable, permitting either a lower total programming current or the simultaneous programming of even bytes. The one page programming time for a low density part of about 16 MB having a page size of 1024 bits is about 320 msec, while the one page programming time for a high density part of about 32 MB having a page size of 2048 bits is about 640 msec.

[0053] FIG. 20 is a graph of threshold voltage vs. time that shows bit line disturb for an erased cell with different values of V _G (points corresponding to V _G =−1.5V are marked by the symbol ⋄, points corresponding to V=0V are marked by the symbol ¤) for fixed V _D =4V, V _P =−3V, and V _S floating, and shows significant improvement in the disturb characteristics by using V _G =−1.5V instead of V _G =0V. The curve for V _G =−2V (not shown) is expected to be even flatter than the curve for V _G =−1.5V.

[0054] It will be appreciated that the time required for programming a page of a serial flash memory using CISEI programming is improved over the time required for programming a page of a serial flash memory using FN programming, which typically is on the order of about 5 ms and could be 7 ms and greater. The amount of some supporting circuitry is also reduced. A serial flash memory using FN programming requires a page of bit latches to store an entire page of data while the page of memory is being programmed. In contrast, flash memory using CHE programming requires only 32 bit latches to store the data while each successive group of 4 bytes in the page is being programmed.

[0055] We have also found that the relatively thin tunnel oxide commonly found in the stacked gate type of flash memory transistor, including the type that is programmed using channel hot electron injection as well as the type that is programmed using channel-initiated secondary electron injection as disclosed in, for example, U.S. Pat. No. 5,659,504, which issued Aug. 19, 1997 (Bude et al., “Method and Apparatus for Hot Carrier Injection”) and is incorporated herein by reference in its entirety, suffers a shortened lifetime because of the high fields that occur across the tunnel oxide during the FN erase operations. Memory cells in memory arrays such as the arrays 100 and 200 are impressed with three different sets of voltages during erase operations, one set being impressed on all of the selected cells and the other two sets being impressed on unselected cells depending on their location in the memory array. These various sets of voltages are illustrated in FIG. 11 , FIG. 12 and FIG. 13 for a cell of the NOR memory array 100 , but are applicable in principle to other types of arrays such as the virtual ground array 200 . It also will be appreciated that the voltage levels depend on not only the type of memory cell, but also specific characteristics of the stacked gate memory cell and the application.

[0056] FIG. 11 shows illustrative voltages on a selected memory transistor that is being erased: the gate voltage V _G =−11V, the drain voltage V _D =6V, the p-well substrate voltage V _P =6V, and the n-well substrate voltage is 6V. The source voltage V _S is left floating. Alternatively, the source voltage V _S may be set to 6V and the drain voltage V _D left floating, or both the source voltage V _S and the drain voltage V _D may be set to 6V. Electrons move by FN tunneling from the floating gate through the oxide to the channel and drain regions, thereby decreasing the VT of the transistor. The electron tunneling, which is generally parallel to the direction of the electrical field, is indicated by the arrows in FIG. 11 . This is a satisfactory condition.

[0057] FIG. 12 shows illustrative voltages on a non-selected memory transistor: the gate voltage V _G =0V, the drain voltage V _D =6V, the p-well substrate voltage V _P =6V, and the n-well substrate voltage is 6V. The voltage difference between the channel/drain and the gate is insufficient to support FN tunneling. When the transistor is in an unprogrammed state, which is to say that the floating gate typically contains relatively few electrons, the electric field across the tunnel oxide is modest and does relatively little harm to the tunnel oxide, even if the memory undergoes many erase operations but the transistor itself is not erased. However, when the transistor is in a programmed state, which is to say that the floating gate contains many electrons and is highly charged, the electric field across the tunnel oxide is quite high. For example, for the stacked gate transistor of FIG. 1 holding a full charge, the voltage on the floating gate may be as greatly negative as minus 3 volts. The cumulative effect for a very large and very dense memory array can be sufficient, leading to degradation of the tunnel oxide. This is an unsatisfactory condition, which we refer to as erase disturb.

[0058] The unsatisfactory condition when the transistor is in a programmed or high V _T state is improved by placing a positive bias on the gates of the unselected transistors in the memory array during erase operations. An illustrative value is about 2.5 volts to about 3 volts, that is V _CC , although the precise voltage depends on the type of memory transistor and its specific characteristics. The various set of voltages that results is illustrated in FIG. 13 .

[0059] FIG. 13 shows illustrative voltages on a non-selected memory transistor having a positive gate bias: the gate bias voltage V _G =2.5V, the drain voltage V _D =6V, the p-well substrate voltage V _P =6V, and the n-well substrate voltage is 6V. The voltage difference between the channel/drain and the gate remains insufficient to support FN tunneling. When the transistor is in an unprogrammed state, the electric field across the tunnel oxide is even smaller than in the FIG. 12 arrangement. When the transistor is in a programmed state, the electric field across the tunnel oxide is reduced by 2.5 volts, thereby bring it down to a lower field strength so that the cumulative effect for a very large and very dense memory array is acceptable. This is a satisfactory condition.

[0060] Exemplary erase characteristics are shown in FIG. 21 , which is a graph of threshold voltage vs. time, for a stacked gate cell having a halo implant. Specifically, FIG. 21 shows erase speed for different values of V _G (points corresponding to V _G =−9V are marked by the symbol ⋄, points corresponding to V _G =−10V are marked by the symbol ¤, and points corresponding to V _G =−11V are marked by the symbol Δ), with V _D =6V and V _P =6V and with the n-well substrate voltage at 6V. With V _G =−11V, cells are erased to V _T ≦2V within about 300 μsec to about 500 μsec. FIG. 22 is a graph of threshold voltage vs. time, and shows the amount of erase disturb for four combinations: V _G =2.5V and V _D =V _S =V _P =6V (corresponding points marked by the symbol ⋄); V _G =2.5V and V _D =V _S =V _P =7V (corresponding points marked by the symbol ¤); V _G =0V and V _D =V _S =V _P =6V (corresponding points marked by the symbol Δ); and V _G =0V and V _{D=V S} =V _P =7V (corresponding points marked by the symbol X). The threshold voltage is seen to be essentially unchanged when using V _G =2.5V instead of V _G =0V during erase operations. FIGS. 21 and 22 are illustrative both of cells designed for CISEI programming as well as cells designed for CHE programming.

[0061] The counter biasing techniques described herein is not limited to the specific memory array architecture of FIGS. 3 and 4 , but may be used in any array architecture, including virtual ground flash memory, NAND, NOR, and so forth, in which the individual unselected memory cells are subject to either voltage disturb during programming or to high electric fields across the tunnel oxide during erase.

[0062] The stacked gate transistor is read using any suitable technique and any suitable set of voltages, including page mode and single and multiple byte reading. Illustratively, the stacked gate transistor of FIG. 1 is designed to have a low V _T of about 2.0V or even about 1.5V, and a high V _T of about 5.5V, although the precise voltage depends on the type of memory transistor and its specific characteristics.

[0063] To avoid any tendency for any memory cells in memory arrays such as the arrays 100 and 200 to experience read disturb due to hot electrons including channel-induced secondary electron injection, which is similar to program disturb but on a smaller scale, a negative bias is placed on the gates of the transistors in the memory array that are not selected for reading. An illustrative value is about minus 2 volts, although the precise voltage depends on the type of memory transistor and its specific characteristics.

[0064] The illustrative set of voltages described above are summarized in the table shown in FIG. 14 , which also includes illustrative voltages suitable for the memory array 200 . The substrate n-well voltage V _NW is also shown. It will be appreciated that the particular voltages and voltage ranges set forth are illustrative and that satisfactory voltages different than the voltages and voltage ranges set forth in the table may be used. These voltages and variations thereof are generated and applied to the memory array using voltage multipliers and voltage dividers in a manner well know in the art.

[0065] The description of the invention and its applications as set forth herein is illustrative and is not intended to limit the scope of the invention. Variations and modifications of the embodiments disclosed herein are possible, and practical alternatives to and equivalents of the various elements of the embodiments are known to those of ordinary skill in the art. These and other variations and modifications of the embodiments disclosed herein may be made without departing from the scope and spirit of the invention.