BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a semiconductor device including an integrated circuit using thin film transistors on a substrate and a method of fabricating the same. Particularly the invention relates to a structure of, for example, an electro-optical device typified by a liquid crystal display device a nd an electronic equipment incorporating the electro-optical device.
[0003] 2. Description of the Related Art
[0004] Development has been made on a semiconductor device typified by an active matrix type liquid crystal display device in which a number of TFTs (thin film transistors) are arranged on a substrate. The TFT has a laminate structure including at least an active layer made of an island-like semiconductor film, a first insulating layer provided at a substrate side of the active layer, and a second insulating layer provided at a side opposite to the substrate side of the active layer. Alternatively, the TFT has a laminate structure including an active layer and a second insulating layer provided to be in close contact with a surface of the active layer at a side opposite to a substrate side thereof, in which the first insulating layer is omitted.
[0005] The structure in which a gate electrode is provided so as to apply a predetermined voltage to the active layer through the first insulating layer is called an inverted stagger type or a bottom gate type. On the other hand, the structure in which a gate electrode is provided so as to apply a predetermined voltage to the active layer through the second insulating layer is called a forward stagger type or top gate type.
[0006] It has been considered that a crystalline semiconductor capable of obtaining high mobility in addition to an amorphous semiconductor is suitable for a semiconductor film used for a TFT. Here, the crystalline semiconductor includes a single crystal semiconductor, a polycrystal semiconductor, and a microcrystal semiconductor. The insulating layer is typically formed of a material such as silicon oxide, silicon nitride, or silicon nitride oxide.
[0007] It is known, as the semiconductor film above, a semiconductor disclosed in Japanese Patent Application Laid Open No. Hei. 7-130652, No. Hei. 8-78329, No. Hei. 10-135468, or No. Hei. 10-135469.
[0008] It has been known that a thin film of the above material fabricated by a well-known film forming technique, such as a CVD (Chemical Vapor Deposition), a sputtering method, and a vacuum evaporation method, includes internal stress. The internal stress has been classified into intrinsic stress which the thin film intrinsically has, and thermal stress due to a difference in thermal expansion coefficient between the thin film and the substrate. It has been possible to neglect the thermal stress by controlling the thermal expansion coefficient of the substrate and process temperature of fabricating steps of the TFT. However, the generation mechanism of the intrinsic stress has not been necessarily clarified, and it has been considered that the intrinsic stress is generated by a complicated combination of a phase change and composition change of the thin film during a growth process thereof, by heat treatment thereafter, and the like.
[0009] In general, as shown in FIG. 3 A, when a thin film is contracted with respect to a substrate, the substrate is deformed by the influence while the thin film is located inside. Thus, the internal stress is called tensile stress. On the other hand, as shown in FIG. 3 B, when the thin film is expanded, the substrate is compressed and is deformed while the thin film is located outside. Thus, the internal stress is called compressive stress. Like this, the definition of the internal stress has been considered while the substrate is made the center. Also in this specification, the internal stress is set forth in accordance with this definition.
[0010] It has been known that volume contraction occurs during a process of crystallization in a crystalline semiconductor film fabricated from an amorphous semiconductor film by a thermal annealing method or a laser annealing method. Although depending on the state of the amorphous semiconductor film, it has been considered that the rate is about 0.1 to 10%. As a result, there has been a case where the tensile stress is generated in the crystalline semiconductor film and its intensity becomes about 1×10 9 Pa. Besides, it has been known that the internal stress of an insulating film, such as a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film, is variously changed from the compressive stress to the tensile stress by fabricating conditions and subsequent heat treatment conditions.
[0011] In the technical field of a VLSI, a problem of stress has been pointed out as one of causes of a poor device. With the improvement in integration, it has inevitably become impossible to neglect an influence of local stress. For example, it has been considered that a heavy metal impurity is captured in a region where the stress is concentrated so that various poor modes are caused, or dislocation generated to relieve the stress is also a factor to deteriorate the characteristics of a device.
[0012] However, with respect to a TFT formed by laminating a plurality of thin films, such as a semiconductor film and an insulating film, an influence caused by the interaction between the respective internal stresses of the thin films has not been sufficiently clarified.
[0013] Although there are some characteristic parameters expressing TFT characteristics, an electric field mobility is regarded as one standard indicating the level of performance. In order to realize a high field effect mobility, the structure of a TFT and its fabricating process have been carefully studied in view of theoretical analysis and empirical side. As especially important factors, it has been considered that it is necessary to decrease a bulk defect density in a semiconductor layer and an interface level density at an interface between a semiconductor layer and an insulating layer to the utmost degree.
[0014] In order to decrease the bulk defect density and interface defect density formed in a crystalline semiconductor layer, the present inventor has considered it to be a problem that the defect density is decreased while internal stresses of respective thin films are taken into consideration and a stress balance is taken, in addition to optimization of fabricating conditions of a TFT.
SUMMARY OF THE INVENTION
[0015] An object of the present invention is to solve the foregoing problem and to realize a TFT in which bulk defect density and interface defect density are decreased while distortion is not generated in a crystalline semiconductor layer.
[0016] As described in the Background of the Invention section, tensile stress is inherent in a crystalline semiconductor film fabricated from an amorphous semiconductor film. In a TFT including an active layer of such a crystalline semiconductor film, it has been necessary to consider a stress balance in order to laminate a gate insulating film, other insulating films and conductive films without generating distortion to the crystalline semiconductor film.
[0017] The stress balance to be considered here is not such that composed stress is made zero by compensating the internal stresses of the laminated thin films, but such that the thin films having inherent internal stresses are laminated, with the crystalline semiconductor film including tensile stress as the center, in such a direction that distortion does not occur in the crystalline semiconductor film.
[0018] FIGS. 4A and 4B are views for explaining the concept of the present invention. With respect to a crystalline semiconductor film having tensile stress, the present inventor has considered to be desirable that a thin film provided at a substrate side of the crystalline semiconductor film has tensile stress ( FIG. 4B ). On the other hand, the present inventor has considered to be desirable that a thin film provided on a surface of the crystalline semiconductor film at a side opposite to the substrate side has compressive stress ( FIG. 4A ). In all events, when the crystalline semiconductor film is contracted, if a stress acts in a direction to expand this, it is expected that distortion occurs in crystal grain boundaries and micro cracks are formed. In such a case, dislocations and crystal defects are produced in the region, and a number of unpaired bonds are formed. Thus, when the thin film provided at the substrate side of the crystalline semiconductor film is made to have the tensile stress, the stress can be given in the same direction as the direction in which the crystalline semiconductor layer is contracted. On the contrary, when the thin film provided at the side opposite to the substrate side with respect to the crystalline semiconductor film is made to have the compressive stress, the stress can be given in the same direction as the direction in which the crystalline semiconductor layer is contracted. That is, when such a structure is adopted that stress is given from other thin films in the direction to contract the crystalline semiconductor film, the defect density can be effectively decreased.
[0019] For the purpose of controlling the internal stress of the thin film, it was sufficient if fabricating conditions and subsequent heat treatment conditions were considered. For example, in a silicon nitride oxide film fabricated by a plasma CVD method, it was possible to change the stress from the compressive stress to the tensile stress by changing the composition ratio of nitrogen and oxygen or the hydrogen content. In a silicon nitride film fabricated by a plasma CVD method, it was possible to change the intensity of the internal stress by changing a film deposition rate.
[0020] Further, the important point in consideration of the stress balance was temperature control in all fabricating steps of a TFT. In a thin film fabricated by a plasma CVD method or a sputtering method, even if the film had a predetermined internal stress in the initial state, there was a case where the stress was changed to quite the opposite direction internal stress by a substrate heating temperature in a subsequent step. On the contrary, it was also possible to change the internal stress by using this property. For example, when a heat treatment at a temperature of 300° C. or more was applied to a silicon nitride film having compressive stress, it was also possible to change the stress to tensile stress.
[0021] When a gate electrode was provided to apply a predetermined voltage through a first insulating layer provided at a substrate side of an active layer made of an island-like semiconductor film formed on a substrate, it was possible to form an inverted stagger type or bottom gate type TFT. When a gate electrode is provided to apply a predetermined voltage to an active layer through a second insulating layer provided at a side opposite to a substrate side of the active layer, it was possible to form a forward stagger type or top gate type TFT.
[0022] Although a material of an insulating film used for the first insulating layer or the second insulating layer was not particularly limited, it was necessary to be able to control the internal stress in some way. For that purpose, a silicon nitride film, a silicon nitride oxide film, a silicon oxide film, a tantalum oxide film, and the like were suitable. Although a method of fabricating the silicon nitride film is not limited, for example, in the case where the film is formed by a plasma CVD method, the film can be formed from a mixture gas of SiH 4 , NH 3 , N 2 , and H 2 . By changing a mixture ratio of the gas and discharge power density, it was possible to fabricate the silicon nitride film under conditions of different film formation rates. As a measuring device of the internal stress, Model-30114 made by Ionic System Inc. was used. A sample fabricated on a silicon wafer was used for measurement.
[0023] With respect to values of the internal stress, it is assume that the tensile stress is indicated by a positive value and the compressive stress is indicated by a negative value so that distinction can be made. According to data of FIG. 17 , although any of silicon nitride films fabricated at a substrate temperature of 400° C. and at different film deposition rates had compressive stress, when a heat treatment at 500° C. for 1 hour was applied, it was possible to change the compressive stress to the tensile stress. Such change was realized when a heat treatment at a temperature higher than a substrate temperature at film formation was carried out, and it was considered that densification of the silicon nitride film was the cause. Thus, it was possible to fabricate both of a film having the compressive stress and a film having the tensile stress for the silicon nitride film.
[0024] A silicon nitride oxide film was fabricated from a mixture gas of SiH 4 and N 2 O using a plasma CVD method. Also in this case, it was possible to fabricate the silicon nitride oxide film by changing the mixture ratio of gas or discharge power density to make film deposition rate different. FIG. 18 shows values of the internal stress of the silicon nitride oxide films fabricated at a substrate temperature of 400° C. Any of respective samples with different film deposition rates had compressive stress. Even if a heat treatment at 450° C. for 4 hours was further applied, the state was unchanged though the absolute value of the compressive stress became small.
[0025] Although FIG. 19 similarly shows data of internal stress of silicon nitride oxide films, this drawing shows data of silicon nitride oxide films fabricated by further mixing NH 3 to SiH 4 and N 2 O. When the NH 3 gas was added at film formation, the characteristic was changed from the compressive stress to the side of the tensile stress. Further, when a heat treatment at 550° C. for 4 hours was applied to the samples, it was possible to increase the tensile stress. The change like this corresponded to the change of composition ratio of a nitrogen content and an oxygen content in the silicon nitride oxide film. Table 1 shows the result of measurement of the content of each element in the silicon nitride oxide film measured by Rutherford backscattering method (RBS).
1 | TABLE 1 |
| |
| |
| CONTENTS (atomic %) |
| CONDITIONS | H | N | O | Si |
| |
| SAMPLE 1 | NH 3 = 0 SCCM | 1.5 | 7.0 | 59.5 | 32.0 |
| SAMPLE 2 | NH 3 = 30 SCCM | 16.5 | 24.0 | 26.5 | 33.0 |
| SAMPLE 3 | NH 3 = 100 SCCM | 15.5 | 44.1 | 6.0 | 34.4 |
|
[0026] When the nitrogen content and the oxygen content in a silicon nitride oxide film were 7 atomic % and 59.5 atomic %, respectively, it was possible to make the nitrogen content and the oxygen content 24.0 atomic % and 26.5 atomic %, respectively, by adding the NH 3 gas of 30 SCCM at film formation. Besides, it was possible to make the nitrogen content and the oxygen content 44.1 atomic % and 6.0 atomic %, respectively, by adding the NH 3 gas of 100 SCCM. That is, by adding the NH 3 gas, it was possible to increase the nitrogen content in the silicon nitride oxide film and to decrease the oxygen content. At this time, it was possible to change the compressive stress to the tensile stress. When the composition of various silicon nitride oxide films obtained by adding the NH 3 gas were investigated, in any film, the composition was such that the silicon content was about 34 atomic %, the hydrogen content was about 16 atomic %, and the sum of nitrogen and oxygen content was about 50 atomic %. The films having the nitrogen content of not less than 25 atomic % and less than 50 atomic % obviously exhibited the tensile stress, and the films having the nitrogen content of not less than 5 atomic % and less than 25 atomic % exhibited the compressive stress. It was possible to consider the change of the internal stress by heat treatment while relating it to the change of the hydrogen content in the film as shown in FIG. 20 . The data of FIG. 20 show the result of measurement by FT-IR to the hydrogen content in the silicon nitride oxide films fabricated by adding the NH 3 gas. By a heat treatment at 500° C. for 1 hour, hydrogen bonded with silicon is first released. This tendency becomes remarkable as the substrate temperature (see Tsub expressed at the upper right of each graph of FIG. 20 ) at film formation becomes low. It is expected that when hydrogen bonded with silicon is released, unpaired bonds are produced, and the tensile stress is strengthened by the interaction (attractive force) of the unpaired bonds. Like this, it was also possible to change the internal stress by decreasing the hydrogen content in the film.
[0027] Like this, by controlling the film formation rate, by applying the heat treatment at a temperature higher than a substrate temperature of film formation, or by controlling film formation conditions, it was possible to control the internal stress. As is well known, a TFT is completed by repeating thin film formation and an etching process, and the important point here was the control of process temperature over all the fabricating steps. It was sufficient if the highest temperature of the process was determined in view of the internal stresses of thin films to be laminated.
[0028] A semiconductor device of the present invention comprises an active layer of an island-like semiconductor film formed over a substrate; a first insulating layer provided at a substrate side of the active layer and including a first silicon nitride oxide film having a nitrogen content higher than an oxygen content and a second silicon nitride oxide film having a nitrogen content lower than an oxygen content; and a second insulating layer provided to be in contact with a surface of the active layer at a side opposite to the substrate side and including a plurality of third silicon nitride oxide films each having a nitrogen content lower than an oxygen content.
[0029] In the semiconductor device of the present invention, the active layer has tensile stress, the first silicon nitride oxide film of the first insulating layer in which the nitrogen content is higher than the oxygen content has tensile stress, and each of the plurality of third silicon nitride oxide films of the second insulating layer in which the nitrogen content is lower than the oxygen content has compressive stress. It is desirable that a difference in absolute values of the tensile stresses between the first insulating layer and the semiconductor layer, or a difference in absolute values between the compressive stress of the second insulating layer and the tensile stress of the semiconductor layer is within 5×10 8 Pa.
[0030] Besides, in the semiconductor device of the present invention, the nitrogen content of the first silicon nitride oxide film in which the nitrogen content is higher than the oxygen content is not less than 25 atomic % and less than 50 atomic %, and the nitrogen content of each of the plurality of third silicon nitride oxide films in which the nitrogen content is lower than the oxygen content is not less than 5 atomic % and less than 25 atomic %.
DETAILED DESCRIPTION OF THE INVENTION
Embodiment Mode 1
[0064] A first embodiment mode for carrying out the invention will be described with reference to FIGS. 1A to 1 C. In FIGS. 1A to 1 C, a first insulating layer 102 is formed on a substrate 101 having an insulating surface. The first insulating layer 102 is formed of a nitrogen-rich silicon nitride oxide film 102 a having a nitrogen content of not less than 25 atomic % and less than 50 atomic % and a silicon nitride oxide film 102 b having a nitrogen content of not less than 5 atomic % and less than 25 atomic % in this order from the substrate. The nitrogen-rich silicon nitride oxide film 102 a has a tensile stress of 5×10 8 Pa to 2×10 9 Pa. The silicon nitride oxide film 102 b is a film having a compressive stress of not higher than −5×10 8 Pa, and is provided between the nitrogen-rich silicon nitride oxide film 102 a and an active layer 103 so as to slightly relieve the action of stress.
[0065] The active layer 103 is a crystalline semiconductor film fabricated from an amorphous semiconductor film by a method such as a laser annealing method or a thermal annealing method, and has inevitably tensile stress without limitations to a particular fabricating method. As the need arises, a channel formation region 103 a , LDD regions 103 b, a source region 103 c, and a drain region 103 d are provided. Contact holes are provided in part of a second insulating layer 104 so that a source electrode 106 and a drain electrode 107 are provided.
[0066] Although a second insulating layer 104 is laminated on the active layer 103 , in the case of top gate type TFT as shown in FIGS. 1A to 1 C, a gate insulating film 104 a is first provided, which is formed of a silicon nitride oxide film having a nitrogen content of not less than 5 atomic % and less than 25 atomic %. A gate electrode is provided thereon at 5 a predetermined position.
[0067] In FIG. 1A, a silicon nitride film 104 b and a silicon oxide film 104 c are formed thereon. The silicon nitride film 104b was formed while controlling the film formation rate, so that the compressive stress was given. The compressive stress of this film 104 b was within the range of −2×10 8 to 1×10 9 Pa.
[0068] FIG. 1B shows a structure in which a silicon oxide film 104 d and a silicon nitride film 104 e are formed on the gate insulating film 104 a. The silicon oxide film 104 d has a stress of 5×10 9 Pa or less, and compressive stress may be applied by the silicon nitride film 104 e formed thereon.
[0069] FIG. 1C shows a structure in which a silicon nitride film 104 f, a silicon oxide film 104 g, a silicon nitride film 104 h, and a silicon nitride oxide film 104 i are formed on the gate insulating film 104 a. The silicon nitride films 104 f and 104 h, and the silicon nitride oxide film 104 i having a nitrogen content of not less than 5 atomic % and less than 25 atomic % have compressive stress. By providing the films having the compressive stress on the source electrode 106 and the drain electrode 107 , it was possible to more effectively give the stress to the active layer 103 .
Embodiment Mode 2
[0070] A second embodiment mode for carrying out the invention will be described with reference to FIGS. 2A to 2 D. In FIGS. 2A to 2 D, a first insulating layer 202 is formed on a substrate 201 having an insulating surface. Similarly to Embodiment Mode 1 , a nitrogen-rich silicon nitride oxide film 202 a having a nitrogen content of not less than 25 atomic % and less than 50 atomic %, and a silicon nitride oxide film 202 b having a nitrogen content of not less than 5 atomic % and less than 25 atomic % are provided. The nitrogen-rich silicon nitride oxide film 202 a has tensile stress. An active layer 203 is a crystalline semiconductor film fabricated from an amorphous semiconductor film by a method such as a laser annealing method or a thermal annealing method, and as the need arises, a channel formation region 203 a , LDD regions 203 b , a source region 203 c , and a drain region 203 d are provided. Contact holes are provided in part of a second insulating layer 204 so that a source electrode 206 and a drain electrode 207 are provided. Although the second insulating layer 204 is laminated on the active layer 203 , in the case of top gate type TFTs as shown in FIGS. 2A to 2 D, a gate insulating film 204 a is first provided, which is formed of a silicon nitride oxide film having a nitrogen content of not less than 5 atomic % and less than 25 atomic %. A gate electrode is provided thereon at a predetermined position.
[0071] FIG. 2A shows a structure in which a silicon oxide film 204 b and a silicon nitride oxide film 204 c are formed on the gate insulating film 204 a . The nitrogen content of the silicon nitride oxide film 204 c was made not less than 5 atomic % and less than 25 atomic %, so that compressive stress was generated. Thus, such a structure is made that the stress is applied to the active layer 203 from the nitrogen-rich silicon nitride oxide film 202 a and the silicon nitride oxide film 204 c . Here, the film having the compressive stress was provided on the source electrode 206 and the drain electrode 207 , so that it was possible to more effectively give the stress to the active layer 203 .
[0072] FIG. 2B shows a structure in which a silicon nitride oxide film 204 d , a silicon oxide film 204 e , and a silicon nitride oxide film 204 f are provided on the gate insulating film 204 a . Then, such a structure is made that stress is applied to the active layer 203 from the nitrogen-rich silicon nitride oxide film 202 a and the silicon nitride oxide films 204 d and 204 f.
[0073] FIG. 2C shows a structure in which a silicon oxide film 204 g , a silicon nitride oxide film 204 h having compressive stress, and a silicon nitride oxide film 204 i are provided on the gate insulating film 204 a . FIG. 2D shows a structure in which a silicon oxide film 204 j , a silicon nitride oxide film 204 k , and a silicon nitride oxide film 204 l are provided. In order to change the internal stress from the tensile stress to the compressive stress by controlling the composition ratio of the nitrogen content and the oxygen content of the silicon nitride oxide film, it was sufficient if the mixture ratio of gases of SiH 4 , N 2 O, and NH 3 used for film formation was changed, which was easily performed. In the case where the silicon nitride oxide film having an internal stress of 5×10 8 Pa or more in absolute value was provided, it was appropriate that the film was not formed to be in contact with the active layer 203 , but was provided through a film having a low stress, such as a silicon oxide film.
Embodiment 1
[0074] This embodiment will be described with reference to FIGS. 5A to 7 D as an example of a bottom gate type TFT. First, a glass substrate, for example, a #1737 substrate of Corning Inc. was prepared as a substrate 601 . A gate electrode 602 was formed on the substrate 601 . Here, a tantalum (Ta) film was formed to a thickness of 200 nm by using a sputtering method. The gate electrode 602 may be a two-layer structure of a tantalum nitride film (film thickness of 50 nm) and a Ta film (film thickness of 250 nm). The Ta film was formed by a sputtering method using an Ar gas while Ta was used as a target, and when sputtering was made with a mixture gas of the Ar gas added with a Xe gas, it was possible to make an absolute value of an internal stress 2×10 8 Pa or less ( FIG. 5A ).
[0075] Then, a first insulating layer 603 and an amorphous semiconductor layer 604 were continuously formed without opening to the air. The first insulating layer 603 was formed of a nitrogen-rich silicon nitride oxide film 603 a (film thickness of 50 nm) and a silicon nitride oxide film 603 b (film thickness of 125 nm). The nitrogen-rich silicon nitride oxide film 603 a was formed by plasma CVD method from a mixture gas of SiH 4 , N 2 O and NH 3 . The amorphous semiconductor layer 604 was also formed to a thickness of 20 to 100 nm, preferably 40 to 75 nm by using the plasma CVD method ( FIG. 5B ).
[0076] Then, a heat treatment at 450 to 550° C. for 1 hour was carried out. By this heat treatment, hydrogen was released from the first insulating layer 603 and the amorphous semiconductor layer 604 , so that it was possible to give tensile stress. Thereafter, a crystallizing step was carried out for the amorphous semiconductor layer 604 , so that a crystalline semiconductor layer 605 was formed. In the crystallizing step here, a laser annealing method or a thermal annealing method may be used. In the laser annealing method, for example, KrF excimer laser light (wavelength 248 nm) was used, a linear beam was formed, and crystallization of the amorphous semiconductor layer was carried out under the conditions that an oscillation pulse frequency was 30 Hz, a laser energy density was 100 to 500 mJ/cm 2 , and an overlap rate of the linear beam was 96%. Here, as the amorphous semiconductor layer was crystallized, volume shrinkage occurred, and the tensile stress of the formed crystalline semiconductor layer was increased ( FIG. 5C ). Next, an insulating film 606 was formed to be in contact with the thus formed crystalline semiconductor layer 605 . Here, a silicon nitride oxide film was formed to a thickness of 200 nm. Thereafter, by a patterning method using exposure from a rear surface, a resist mask 607 was formed to be in contact with the insulating film 606 . Here, the gate electrode 602 became a mask, so that the resist mask 607 was formed in a self-aligning manner. As shown in the drawing, the size of the resist mask became slightly smaller than the width of the gate electrode since light went around ( FIG. 5D ). The insulating film 606 was etched by using the resist mask 607 , and after a channel protecting film 608 was formed, the resist mask 607 was removed. By this step, the surface of the crystalline semiconductor layer 605 except a region being in contact with the channel protecting film 608 was exposed. This channel protecting film 608 functioned to prevent addition of an impurity into a channel region in a subsequent impurity addition step ( FIG. 5E ).
[0077] Next, a resist mask 609 covering a part of an n-channel TFT and a p-channel TFT was formed by patterning using a photomask, and a step of adding an impurity element to give an n-type was carried out to the region where the surface of the crystalline semiconductor layer 605 was exposed. Then, a first impurity region (n + -type region) 610 a was formed. In this embodiment, since phosphorus was used as the impurity element to give the n-type, phosphine (PH 3 ) was used in an ion doping method, and the dose amount was made 5×10 14 atoms/cm 2 and the acceleration voltage was made 10 keV. The pattern of the resist mask 609 was suitably set by an operator, so that the width of the n + -type region was determined, and it was possible to easily obtain an n − -type region having a desired width and a channel formation region ( FIG. 6A ).
[0078] After the resist mask 609 was removed, a second insulating film 611 was formed. Here, a silicon nitride oxide film (film thickness of 50 nm) having a nitrogen content of not less than 5 atomic % and less than 25 atomic % and having compressive stress, which was shown in the embodiment 1, was formed by a plasma CVD method. The silicon nitride oxide film had the compressive stress ( FIG. 6B ).
[0079] Next, a step of adding an impurity element to give the n-type was carried out to the crystalline semiconductor layer having the surface on which the masking insulating film 611 was provided, so that a second impurity region (n − -type region) 612 was formed. However, in order to add the impurity through the masking insulating film 611 to the crystalline semiconductor layer thereunder, it was necessary to suitably set the condition in view of the thickness of the masking insulating film 611 . Here, the dose amount was 3×10 13 atoms/cm 2 , and the acceleration voltage was made 60 keV. The second impurity regions 612 formed in this way functioned as LDD regions ( FIG. 6C ).
[0080] Next, a resist mask 614 covering the n-channel TFT was formed, and a step of adding an impurity element to give a p-type was carried out to a region where the p-channel TFT was to be formed. Here, boron (B) was added by an ion doping method using diborane (B 2 H 6 ). The dose amount was 4×10 15 atoms/cm 2 , and the acceleration voltage was made 30 keV ( FIG. 6D ).
[0081] Thereafter, after a step of activating the impurity elements by a laser annealing method or a thermal annealing method was carried out, a heat treatment (300 to 500° C., 1 hour) was carried out in a hydrogen atmosphere, so that the whole was hydrogenated ( FIG. 7A ).
[0082] Hydrogenating may be carried out by hydrogen produced by making plasma. Thereafter, the channel protecting film 608 and the masking insulating film 611 were selectively removed by a fluoric acid based etching solution, and the crystalline semiconductor layer was etched into a desired shape by a well-known patterning technique ( FIG. 7B ).
[0083] Through the foregoing steps, a source region 615 , a drain region 616 , LDD regions 617 and 618 , and a channel formation region 619 of the n-channel TFT were formed. Besides, a source region 621 , a drain region 622 , and a channel formation region 620 of the p-channel TFT were formed. Next, a second insulating layer was formed to cover the n-channel TFT and the p-channel TFT. In the second insulating layer, an insulating film 623 made of a silicon oxide film was first formed to a thickness of 1000 nm ( FIG. 7C ).
[0084] Then, contact holes were formed, and source electrodes 624 and 626 , and drain electrodes 625 and 627 were formed. Further, as a second insulating layer, a silicon nitride oxide film 628 was formed on the insulating film 623 made of the silicon oxide film to cover the source electrodes 624 and 626 , and the drain electrodes 625 and 627 . The silicon nitride oxide film 628 was made to have a nitrogen content of not less than 5 atomic % and less than 25 atomic %, and was made to have the compressive stress. After the state shown in FIG. 7D was obtained, a heat treatment was finally carried out in a hydrogen atmosphere, and the whole was hydrogenated, so that the n-channel TFT and the p-channel TFT were completed. It was also possible to realize the hydrogenating step by exposing the whole to a hydrogen atmosphere of plasma.
Embodiment 2
[0085] An example of a semiconductor device including an n-channel TFT and a p-channel TFT using the fabricating steps of Embodiment 1 will be described with reference to FIGS. 8A to 8 C. FIGS. 8A to 8 C show an inverter circuit as a basic structure of a CMOS circuit. By combining such an inverter circuit, it is possible to construct a basic circuit such as a NAND circuit and a NOR circuit, or to construct a further complicated shift register circuit, buffer circuit, and the like. FIG. 8A is a view corresponding to a top view of a CMOS circuit, and FIG. 8B is a sectional structural view taken along dotted line A-A′ in FIG. 8A .
[0086] In FIG. 8 B, both the n-channel TFT and the p-channel TFT are formed on the same substrate. In the p-channel TFT, a gate electrode 902 is formed, and a nitrogen-rich silicon nitride oxide film 903 having tensile stress and a silicon nitride oxide film 904 are provided as a first insulating layer thereon. An active,layer made of a crystalline semiconductor film is formed to be in contact with the first insulating layer, and a p + -region 912 (drain region), a p+-region 915 (source region), and a channel formation region 914 are provided. A second insulating layer is provided to be in contact with this semiconductor layer, and here, a silicon oxide film 917 and a silicon nitride oxide film 919 are formed. A source electrode 920 and a drain electrode 918 are formed through contact holes provided in the silicon oxide film. On the other hand, in an active layer of the n-channel TFT, an n + -type region 905 (source region), an n + -type region 911 (drain region), a channel formation region 909 , and an n − -type region between the n + -type region and the channel formation region are provided. Similarly, contact holes are formed in the silicon oxide film 917 as an interlayer insulating film, and a source electrode 916 and a drain electrode 918 are provided.
[0087] Such a CMOS circuit can be applied to a peripheral driver circuit of an active matrix type liquid crystal display device, a driver circuit for an EL (Electro luminescence) type display device, a reading circuit of a contact-type image sensor, and the like.
Embodiment 3
[0088] This embodiment will be described with reference to FIGS. 9A to 9 E and FIGS. 10A to 10 C. Here, a description will be made on an example in which an n-channel TFT and a p-channel TFT are fabricated on the same substrate, and an inverter circuit as a basic structure of a CMOS circuit is formed. In FIG. 9A, a first insulating layer is formed on a substrate 701 having an insulating surface. Here, a nitrogen-rich silicon nitride oxide film 702 having a nitrogen content of not less than 25 atomic % and less than 50 atomic % was formed to a thickness of 20 to 100 nm, typically a thickness of 50 nm, and a silicon nitride oxide film 703 having a nitrogen content of not less than 5 atomic % and less than 25 atomic % was formed to a thickness of 50 to 500 nm, typically 150 to 200 nm. The nitrogen-rich silicon nitride oxide film 702 has tensile stress. A second island-like semiconductor film 704 , a first island-like semiconductor film 705 , and a gate insulating film 706 were formed. The gate insulating 706 was formed of a silicon nitride oxide film. The island-like semiconductor films were formed by separating a crystalline semiconductor film, which was formed from an amorphous semiconductor film by a method such as a laser annealing method or a thermal annealing method, by a well-known technique ( FIG. 9A ).
[0089] As a semiconductor material which can be applied here, silicon (Si), germanium (Ge), silicon germanium alloy, and silicon carbide can be enumerated. In addition, a compound semiconductor material such as gallium arsenide may be used. The semiconductor film is formed to a thickness of 10 to 100 nm, typically 50 nm. Hydrogen is contained in an amorphous semiconductor film formed by a plasma CVD method at a rate of 10 to 40 atomic %. Although the amorphous semiconductor film has arbitrary internal stress from compressive stress to tensile stress by fabricating conditions, when a step of heat treatment at 400 to 500° C. was carried out prior to a step of crystallization to remove hydrogen from the film, the internal stress was almost changed to the tensile stress.
[0090] Then, resist masks 707 and 708 covering the second island-like semiconductor film 704 and the channel formation region of the first island-like semiconductor film 705 were formed. At this time, a resist mask 709 may also be formed on a region where a wiring is formed. Then, a step of forming a second impurity region was carried out by adding an impurity element to give an n-type. Here, phosphorus (P) was added by an ion doping method using phosphine (PH 3 ). In this step, for the purpose of adding phosphorus through the gate insulating film 706 to the island-like semiconductor layer thereunder, the acceleration voltage was set as high as 80 keV. It is preferable that the concentration of phosphorus added to the island-like semiconductor layer is within the range of 1×10 16 to 1×10 19 atoms/cm 3 , and here, it was made 1×10 18 atoms/cm 3 . Then, regions 710 and 711 where phosphorus was added into the semiconductor layer were formed. Part of the regions functioned as LDD regions ( FIG. 9B ).
[0091] Then, a conductive layer 712 was formed on the surface of the gate insulating film 706 . The conductive layer 712 is formed using a conductive material containing an element selected from Ta, Ti, Mo, and W as its main ingredient. It is appropriate that the thickness of the conductive layer 712 is 100 to 500 nm, preferably 150 to 400 nm. The thin film of Ta, Ti, W, Mo, or the like fabricated by a sputtering method had a high compressive stress. However, it was possible to effectively decrease the stress by adding an Xe gas in addition to an Ar gas at the time of film formation by sputtering ( FIG. 9C ).
[0092] Next, resist masks 713 to 716 were formed. The resist mask 713 is for forming a gate electrode of the p-channel TFT, and the resist masks 715 and 716 are for forming a gate wiring and a gate bus line. The resist mask 714 was formed to cover the whole surface of the first island-like semiconductor film 705 , and was provided to be made a mask to prevent addition of an impurity in a next step. An unnecessary portion of the conductive layer 712 was removed by a dry etching method, so that a second gate electrode 717 , a gate wiring 719 , a gate bus line 720 were formed. Here, in the case where a residual after etching remained, it was appropriate that an ashing process was carried out. While the resist masks 713 to 716 were made to remain as they were, an impurity element to give a p-type was added to a part of the second island-like semiconductor film 704 where the p-channel TFT was formed, so that a third impurity region was formed. Here, boron was used as the impurity element and was added by an ion doping method using diborane (B 2 H 6 ). Also in this step, the acceleration voltage was made 80 keV, and boron was added at a concentration of 2×10 20 atoms/cm 3 . As shown in FIG. 9 D, third impurity regions 721 and 722 where boron was added at a high concentration were formed.
[0093] After the resist masks provided in FIG. 9D were removed, resist masks 723 to 725 were again formed. These are for forming a gate electrode of the n-channel TFT, and a first gate electrode 726 was formed by a dry etching method. At this time, the first gate electrode 726 was formed to overlap with part of the second impurity regions 710 and 711 through the gate insulating film ( FIG. 9E ).
[0094] Next, resist masks 729 to 731 were formed. The resist mask 730 was formed to cover the first gate electrode 726 and into such a shape that it overlapped with part of the second impurity regions 710 and 711 . This is for determining an offset amount of LDD regions. Then, a step of forming a first impurity region was carried out by adding an impurity element to give an n-type, so that a first impurity region 732 which became a source region and a first impurity region 733 which became a drain region were formed. Also in this step, for the purpose of adding phosphorus through the second insulating layer 706 to the semiconductor layer thereunder, the acceleration voltage was set as high as 80 keV. The concentration of phosphorus in this region is high as compared with the step of adding the first impurity element to give the n-type, and it is preferable that the concentration is made 1×10 19 to 1×10 21 atoms/cm 3 , and here, it was made 1×10 20 atoms/cm 3 ( FIG. 10A ).
[0095] Then, a silicon oxide film 734 with a thickness of 1000 nm was formed on the surfaces of the gate insulating film 706 , the first and second gate electrodes 726 and 717 , a gate wiring 727 , and a gate bus line 728 . Thereafter, a heat treatment was carried out. It was necessary to carry out this treatment in order to activate the impurity elements added at each concentration and to give the n-type or p-type. This step may be carried out by a thermal annealing method using an electric heating furnace, the foregoing laser annealing method using an excimer laser, or a rapid thermal annealing method (RTA method) using a halogen lamp. However, in the laser annealing method, although activation can be made at a low substrate heating temperature, it is difficult to make activation to a region concealed under the gate electrode. Here, the activation was made by the thermal annealing method. The heat treatment was carried out in a nitrogen atmosphere at 300 to 600° C., preferably 350 to 550° C., here, 450° C. for 2 hours. In this heat treatment, hydrogen of 3 to 90% may be added in the nitrogen atmosphere. Further, it is appropriate that after the heat treatment, a step of hydrogenating process is carried out in a hydrogen atmosphere of 3 to 100% at 150 to 500° C., preferably 300 to 450° C. for 2 to 12 hours. The hydrogenating process may be carried out by hydrogen produced by making plasma at a substrate temperature of 150 to 500° C., preferably 200 to 450° C. In all events, hydrogen compensated defects remaining in the semiconductor layer or its interface, so that it was possible to improve the characteristics of the TFT.
[0096] After a predetermined resist mask was formed, the silicon oxide film 734 was subjected to an etching process so that contact holes reaching a source region and a drain region of each TFT were formed. Then, source electrodes 736 and 737 and a drain electrode 738 were formed. Although not shown, in this embodiment, the respective electrodes were used as a three-layer electrode in which a Ti film having a thickness of 100 nm, an Al film containing Ti and having a thickness of 300 nm, and a Ti film having a thickness of 150 nm were continuously formed by a sputtering method. Further, a silicon nitride oxide film 735 having a nitrogen content of from 5 atomic % to 25 atomic % was formed on all surfaces thereof. This film had compressive stress. When a second hydrogenating process was carried out in this state, it was possible to further improve the characteristics of the TFT. Also in this step, it was appropriate that a heat treatment at 300 to 450° C., preferably 300 to 350° C. for 1 to 6 hours was carried out in a hydrogen atmosphere of 1 to 5%. Alternatively, it was possible to make hydrogenating by exposing the whole to hydrogen produced by making plasma.
[0097] Through the steps described above, the first insulating layer was composed of the nitrogen-rich silicon nitride oxide film 702 having the tensile stress and the silicon nitride oxide film 703 , and the second insulating layer was composed of the gate insulating film 706 made of the silicon nitride oxide film, the silicon oxide film 734 , and the silicon nitride oxide film 735 . The p-channel T° FI was formed in a self-aligning manner, and the n-channel TFT was formed in a nonself-aligning manner.
[0098] A channel formation region 742 , first impurity regions 745 and 746 , and second impurity regions 743 and 744 were formed in the n-channel TFT of the CMOS circuit. Here, in the second impurity regions, regions (GOLD (gate overlapped drain) regions) 743 a and 744 a overlapping with the gate electrode, and regions (LDD regions) 743 b and 744 b not overlapping with the gate electrode were formed, respectively. The first impurity region 745 became a source region, and the first impurity region 746 became a drain region. On the other hand, in the p-channel TFF, a channel formation region 739 , and third impurity regions 740 and 741 were formed. The third impurity region 740 became a source region, and the third impurity region 741 became a drain region ( FIG. 10B ).
[0099] FIG. 10C is a top view showing an inverter circuit. An A-A′ sectional structure of a TFT portion, a B-B′ sectional structure of a gate wiring portion, and a C-C′ sectional structure of a gate bus line portion correspond to FIG. 10B . In the present invention, the gate electrode, the gate wiring, and the gate bus line are formed of the first conductive layer. In FIGS. 9A to 9 E and FIGS. 10A to 10 C, although the CMOS circuit formed by complementarily combining the n-channel TFT and the p-channel TFT is shown as an example, the present invention can also be applied to an NMOS circuit using an n-channel TFT, a pixel portion of a liquid crystal display device, an EL display device, a reading circuit of an image sensor, and the like.
Embodiment 4
[0100] In this embodiment, a method of fabricating an active matrix substrate in which a pixel portion (pixel matrix circuit) and a CMOS circuit as a base of a driver circuit provided at its periphery are formed at the same time will be described with reference to FIGS. 11A to 13 B.
[0101] First, as a first insulating layer, a nitrogen-rich first silicon nitride oxide film 1102 a was formed to a thickness of 50 to 500 nm, typically 100 nm on a substrate 1101 , and further, a second silicon nitride oxide film 1102 b was formed to a thickness of 100 to 500 nm, typically 200 nm. The nitrogen content of the nitrogen-rich first silicon nitride oxide film 1102 a was made not less than 25 atomic % and less than 50 atomic %. The nitrogen-rich first silicon nitride oxide film 1102 a was formed of SiH 4 , N 2 O and NH 3 , and as shown in FIG. 19 , the film had tensile stress. The internal stress was kept even to a heating treatment attendant on a crystallizing step or a gettering step. Further, island-like crystalline semiconductor films 1103 , 1104 and 1105 , and a gate insulating film 1106 were formed. The island-like crystalline semiconductor films were formed in such a manner that a crystalline semiconductor film was formed from an amorphous semiconductor film by a crystallizing method using a catalytic element, and this film was processed and separated into island-like regions. The gate insulating film 1106 was a silicon nitride oxide film formed from SiH 4 and N 2 O, and had compressive stress. Here, the film was formed to a thickness of 10 to 200 nm, preferably 50 to 150 nm ( FIG. 11A ).
[0102] Next, resist masks 1107 to 1111 were formed to cover the island-like semiconductor film 1103 , and channel formation regions of the island-like semiconductor films 1104 and 1105 . At this time, the resist mask 1109 may be formed in a region where a wiring is formed. Then, an impurity element to give an n-type was added so that second impurity regions were formed. Here, phosphorus (P) was added by an ion doping method using phosphine (PH 3 ). In this step, for the purpose of adding phosphorus through the gate insulating film 1106 to the island-like semiconductor film thereunder, the acceleration voltage was set 65 keV. It is preferable that the concentration of phosphorus added to the island-like semiconductor is within the range of 1×10 16 to 1×10 19 atoms/cm 3 , and here, it was made 1×10 18 atoms/cm 3 . Then, regions 1112 to 1116 where phosphorus was added were formed. Part of the regions are made the second impurity regions functioning as LDD regions ( FIG. 11B ).
[0103] Thereafter, the resist masks were removed and a conductive layer 1117 was formed on the whole surface. The conductive layer 1117 is formed by using a conductive material containing an element selected from Ta, Ti, Mo, and W as its main ingredient. It is appropriate that the thickness of the conductive layer 1117 is 100 to 1000 nm, preferably 150 to 400 nm. Here, the film was formed of Ta by a sputtering method using a mixture gas of Ar and Xe ( FIG. 11C ).
[0104] Next, a gate electrode of a p-channel TFT, gate wirings of a CMOS circuit and a pixel portion, and gate bus lines were formed. Since a gate electrode of an n-channel TFT was formed in a subsequent step, resist masks 1119 and 1123 were formed so that the conductive layer 1117 remained on the whole surface over the island-like semiconductor film 1104 . Unnecessary portions of the conductive layer 1117 were removed by a dry etching method. Etching of Ta was carried out by a mixture gas of CF 4 and O 2 . Then, a gate electrode 1124 , gate wirings 1126 and 1128 , and a gate bus line 1127 were formed. Then, a step of adding a third impurity element to give a p-type was carried out to part of the island-like semiconductor film 1103 where the p-channel TFT was to be formed, while the resist masks 1118 to 1123 were made to remain as they were. Here, boron was used as the impurity element and was added by an ion doping method using diborane (B 2 H 6 ). Also in this step, the acceleration voltage was made 80 keV, and boron was added at a concentration of 2×10 20 atoms/cm 3 . As shown in FIG. 12 A, third impurity regions 1130 and 1131 where boron was added at the high concentration were formed.
[0105] After the resist masks provided in FIG. 12A were removed, resist masks 1124 to 1130 were newly formed. These were for forming gate electrodes of n-channel TFTs, and gate electrodes 1131 to 1133 were formed by a dry etching method. At this time, the gate electrodes 1131 to 1133 were formed to overlap with part of the second impurity regions 1112 to 1116 ( FIG. 12B ).
[0106] Then, new resist masks 1135 to 1141 were formed. The resist masks 1136 , 1139 , and 1140 were formed into such a shape as to cover the gate electrodes 1131 to 1133 of the n-channel TFTs and part of the second impurity regions. Here, the resist masks 1136 , 1139 and 1140 are respectively for determining an offset amount of LDD regions. Then, a step of forming first impurity regions was carried out by adding an impurity element to give an n-type. Then, first impurity regions 1143 and 1144 which became source regions and first impurity regions 1142 , 1145 and 1146 which became drain regions were formed. Also in this step, phosphorus was added through the gate insulating film 1106 to the island-like semiconductor film thereunder. The concentration of phosphorus in this region is high as compared with the step of adding the first impurity element to give the n-type, and it is preferable that the concentration is made 1×10 19 to 1×10 21 atoms/cm 3 , and here, it was made ×10 20 atoms/cm 3 . At this time, also in part of the source and drain regions of the p-channel TFT, regions 1180 and 1181 where phosphorus was added were formed. However, the concentration of phosphorus in this region is about half of the concentration of boron, and the conductivity remains the p-type ( FIG. 12C ).
[0107] After the steps to FIG. 12C were completed, a silicon oxide film 1147 was formed. Here, TEOS (Tetraethyl Orthosilicate) was used as a raw material, and the film was formed to a thickness of 1000 nm by a plasma CVD method. In this state, a heat treatment at 400 to 800° C. for a 1 to 24 hours, for example, at 525° C. for 8 hours was carried out. By this step, it was possible to activate the added impurity elements to give the n-type and the p-type. Further, the regions 1142 to 1146 , 1180 and 1181 where phosphorus was added became gettering sites, so that it was possible to segregate the catalytic element remaining in the step of crystallization into these regions. As a result, it was possible to remove the catalytic element from at least channel formation regions. It is appropriate that after this heat treatment, a step of hydrogenating process is carried out in a hydrogen atmosphere of 3 to 100% at 150 to 500° C., preferably 300 to 450° C. for 2 to 12 hours. Alternatively, the hydrogenating process may be carried out with hydrogen produced by making plasma at a substrate temperature of 150 to 500° C., preferably 200 to 450° C. In all events, hydrogen compensated defects remaining in the semiconductor layer or its interface, so that it was possible to improve the characteristics of the TFT ( FIG. 13A ).
[0108] Thereafter, the silicon oxide film 1147 was patterned so that contact holes reaching a source region and a drain region of each TFT were formed. Then, source electrodes 1149 , 1150 and 1151 , and drain electrodes 1152 and 1153 were formed. Although not shown, in this embodiment, each of the electrodes was used as a three-layer electrode in which a Ti film having a thickness of 100 nm, an Al film containing Ti and having a thickness of 300 nm, and a Ti film having a thickness of 150 nm were continuously formed by a sputtering method. When a second hydrogenating process was carried out in this state, it was possible to further improve the characteristics of the TFT. Also in this step, it was appropriate that a heat treatment at 300 to 450° C., preferably 300 to 350°