DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] The following detailed explanations of FIGS. 1 - 3 and of the preferred embodiments reveal the methods and apparatus of the present invention. FIG. 1 is a generalized functional block diagram of an integrated beamformer/modem architecture in accordance with an exemplary embodiment of the present invention. The beamformer/modem architecture of the present invention can be employed in any communication device that transmits or receives signals from other communication devices. As used herein and in the claims, a “communication device” includes any device, mobile or stationary, that is capable of transmitting and/or receiving communication signals, including but not limited to: a handheld or body-mounted radio; any type of mobile or wireless telephone (e.g., analog cellular, digital cellular, PCS or satellite-based); a pager, beeper or PDA device; a radio or transceiver carried on, built into or embedded in a ground-based or airborne vehicle; any portable electronic device equipped with wireless reception/transmission capabilities, including multimedia terminals capable of receiving/transmitting audio, video and/or data information; and any device mounted in a fixed location with transmission/reception capabilities. The architecture of the present invention is particularly useful in any transceiver communication device requiring the use of directed antenna beams to transmit signals to and receive signals from a plurality of other communication devices used in transmission of audio, video and/or data information including, but not limited to, base stations of wireless communication systems, mobile communication devices, airborne communication systems, and communications satellites.

[0028] Referring to FIG. 1 , the transceiver beamformer/modem architecture includes a plurality E of transmit/receive antenna elements 10 ₁ , 10 ₂ , . . . , 10 _E forming a phased array antenna which is electronically steerable via digital beamforming. Antenna elements 10 may have any hardware configuration suitable for operating at the frequency and bandwidth required by the communication system in which the transceiver is used. In the specific implementation shown in FIG. 1 , the transceiver employs time-division duplexing (TDD) in which the transceiver is alternately in a transmit and receive mode, relying on the phased array antenna for both signal transmission and reception. Accordingly, each antenna element 10 _i has a corresponding RF switching element 12 _i selectively connecting the antenna element to the transmitter system and the receiver system. RF switching elements 12 _i can be a RF transmit/receive switches, circulators, diplexers, hybrid splitters or any other device suitable for selective connecting the antenna elements to the transmit and receive circuitry. It should be understood, however, that the invention is not limited to a TDD architecture, and the present invention can be employed with both simultaneous and non-simultaneous transmit/receive schemes.

[0029] On the receiver side, each of the antenna elements 10 ₁ , 10 ₂ , . . . , 10 _E is coupled to a respective bandpass filter 14 ₁ , 14 ₂ , . . . , 14 _E which attenuates signal frequencies outside the filter's pass band. Each antenna element 10 _i can simultaneously receive signals on a plurality of different frequency channels F within the receiver pass band (frequency division multiplexing FDM). Each frequency channel is in turn time-division multiplexed (TDM), such that the system employs both time division multiple access (TDMA) and frequency division multiple access (FDMA) channelizing. The filtered RF signal from each element 10 ₁ , 10 ₂ , . . . , 10 _E is amplified by a corresponding low-noise amplifier (LNA) 16 ₁ , 16 ₂ , . . . , 16 _E and then processed by an analog RF down-converter (DC) 18 ₁ , 18 ₂ , . . . , 18 _E which down-converts the RF signal to an intermediate frequency (IF). For each of the E IF signals, a corresponding analog-to-digital (A/D) converter 19 ₁ , 19 ₂ , . . . , 19 _E digitally samples the IF signal at a wideband input sampling rate Fs ₁ , and the digital IF signal is received by a bank of digital down-converters (DDC) 20 to perform frequency division multiplexing (FDM) de-channelization.

[0030] The DDC bank 20 includes a digital down-converter for each of the F frequency channels of each of the E antenna elements for a total of F×E digital down-converters. In practice, it may be possible under certain circumstances to perform digital down-conversion with fewer than F×E actual DDC devices, as will be explained herein in greater detail. DDC bank 20 down-converts the digital IF signal to a baseband frequency by decimating the digital IF signal and FIR filtering to bring the signal in each frequency channel of each antenna element down to baseband. Specifically, each DDC selects every R ^th sample for inclusion in the baseband signal while discarding the intervening R-1 samples, such that each DDC produces a decimated signal for a particular element and frequency channel at a sampling rate of 1 $\begin{array}{cc}{\mathrm{Fs}}_2=\frac{{\mathrm{Fs}}_1}{R}& \left(1\right)\end{array}$

[0031] The factor R represents the narrowband rate reduction which facilitates multiplexing the multiple elements and frequency channels in order to share baseband processing circuitry. A frequency division multiplexer (FDM) channel numerically controlled oscillator bank 22 comprises F NCOs which are respectively tuned to the center frequency of the F frequency channels. The FDM channel NCO bank 22 supplies the F different frequency signals used by DDC bank 20 to perform the complex multiplying required to bring each of the F frequency channel signals from each of the E antenna elements down to baseband, which are then filtered by FIR filters.

[0032] As shown in FIG. 1 , each of the digital baseband signals generated in parallel by the F×E DDCs is time multiplexed by multiplexer (MUX) 24 into a serial signal having a rate of 2 $\begin{array}{cc}{\mathrm{Fs}}_3=\frac{{\mathrm{Fs}}_1·E·F}{R}& \left(2\right)\end{array}$

[0033] The time-multiplexed serial baseband output signal of multiplexer 24 is processed at baseband as described below to detect data symbols for each of C user channels. It should be understood that the various data rates described herein relate to upper limits constrained by the relationships between factors such as the wideband sample rate, the number and bandwidth of frequency and time channels, the decimation/interpolation factor, the number of antenna elements, the number of users channels and input/output symbol rates. Accordingly, a particular architecture can be designed to operate up to particular clock rates in accordance with these relationships. However, these rate relationships do not imply that the hardware must be operated at the maximum designed rate. Thus, for example, while Fs ₃ is shown in equation (2) to as “equal to” a particular expression, it will be understood that this expression represents an upper limit on the permissible value of Fs ₃ ; in operation, Fs ₃ can be set at an appropriate rate up to the value of this expression.

[0034] On the transmitter side, baseband signals are generated at the rate Fs ₃ and supplied to a demultiplexer (DEMUX) 26 . The serial baseband signal stream includes time-multiplexed signals for each antenna element on each user channel. Demultiplexer 26 converts the serial baseband signal to F×E parallel signals, each having a rate of Fs ₂ , which are respectively received by F×E digital up-converters (DUC) of a DUC bank 28 which performs FDM channelization of the baseband signals. Receiving the center frequencies of the F frequency channels from FDM channel NCO bank 22 , DUC bank 28 performs the complex multiplying required to up-convert E signals (one for each antenna element) on each of the F channel frequencies into E digital IF signals. Further, to bring the sampling rate up to the wideband sampling rate Fs ₁ , required by the digital-to-analog converters 29 ₁ , 29 ₂ , . . . , 29 _E corresponding to antenna elements 10 ₁ , 10 ₂ , . . . , 10 _E , DUC bank 28 interpolates each of the E digital IF signals by the factor of R. After digital-to-analog conversion, the analog IF signal for each of E antenna elements is up-converted to RF by respective analog up-converters 30 ₁ , 30 ₂ , . . . , 30 _E and amplified by respective power amplifiers 32 ₁ , 32 ₂ , . . . , 32 _E . With RF switching elements 12 ₁ , 12 ₂ , . . . , 12 _E positioned to connect the transmit circuitry to respective antenna elements 10 ₁ , 10 ₂ , . . . , 10 _E , the amplified RF signals are transmitted via the antenna elements in accordance with the beamforming applied in the baseband processing.

[0035] Beamforming in a multi-user modem or base station applications in the prior art has principally taken a non-integrated or detached approach. In some cases, beamforming rotation and combining is done in analog in the front-end UC/DC circuitry of the modem. In other cases, beamforming is performed using either analog or digital approaches as a distinct external apparatus from the modem. The approach of the present invention is to incorporate beamforming directly into the modem architecture. To accomplish beamforming, the appropriate relative signal phase and amplitude must be applied to the individual antenna elements to form an antenna beam which has a desired shape and points in a particular direction. To support signal modulation and demodulation, baseband processors typically perform the functions of carrier phase tracking (involving carrier phase rotation) and automatic gain control (AGC) (i.e., adjusting the amplitude of the baseband signal to be within the operational range of downstream devices), although baseband processors do not generally process carrier phase and amplitude on an antenna-element-by-antenna-element basis. In accordance with the present invention, beamforming is integrated into baseband processing such that beamforming computations are performed in a manner requiring only additional adders, due to integration with the existing modulation/demodulation carrier phase rotation and the AGC/power-control scaling functions.

[0036] An important novel aspect of the present invention is the independent processing of each antenna element all the way from the antenna elements down to individual baseband channel-level processing. While increasing the baseband computational complexity by a factor of the number of antenna elements E, this approach affords significant performance advantages to each user channel, permitting completely independent antenna beam patterns to be achieved per channel when receiving, as well as individual contributions to the beam pattern when transmitting.

[0037] Baseband processing is described in connection with transmission and reception of data symbols associated with a plurality of users. A flow diagram summarizing the signal processing operations associated with modulating and transmitting data symbols is shown in FIG. 2 , while a flow diagram summarizing the signal processing operations associated with receiving and demodulating data symbols is shown in FIG. 3 . Referring to FIGS. 1 and 2 , C independent data streams of symbols are received in parallel on C user channels at a certain data rate. The input data symbols from the C user channels are time multiplexed by multiplexer 34 into a serial signal having a data rate C times the input symbol rate, with each user channel receiving the fraction 1/C of the time slots (operation 100 in FIG. 2 ). The serial signal is processed by a baseband modulator bank 36 comprising C baseband modulators which respectively generate in a time-multiplexed series baseband signals from the input data symbols of the C user channels for processing by shared baseband processor 38 .

[0038] Since beamforming is to be performed at baseband, for each input data symbol on each user channel, baseband modulator bank 36 must generate E copies of each symbol (operation 102 ). Consequently, the data rate of the time-multiplexed signal out of baseband modulator bank 36 is the input data symbol rate times the number of user channels C times the number of antenna elements E, and for each input data symbol time slot, baseband modulator bank 36 produces E identical baseband modulated signals in E corresponding time slots. The output of the baseband modulator bank 36 , which is supplied to shared baseband processor 38 , is serialized in this manner so that shared baseband processor 38 can be implemented with a single complex multiplier and a single automatic gain control element. Shared baseband processor 38 applies different phases and scaling to each of the E copies of each symbol.

[0039] Shared baseband processor 38 includes a carrier phase accumulator bank 40 comprising a single numerically controlled oscillator (NCO) controlled in a time-multiplex manner via a memory bank of phase values corresponding to each user channel C (for both modulation and demodulation). The NCO supplies a rolling phase for the respective data channels to a phase adder 42 in a time-multiplexed manner. A bank of beam rotation weights 44 contains beamforming weights in the form of phase rotations for each channel and each antenna element, which are supplied to phase adder 42 channel-by-channel and element-by-element in a time-multiplexed manner. With C independent user channels, E different antenna elements and both transmit and receive beam steering, beam rotation weight bank 44 includes C×E×2 beamforming phase rotations. Phase adder 42 receives the beamforming rotation weights and adjusts the phase supplied by the carrier phase accumulator bank NCO 40 in accordance with the beamforming phases of the particular antenna elements. A sin/cos lookup table 46 is indexed by the adjusted phase value generated by phase adder 42 and supplies the corresponding sine/cosine multiplicands to a complex multiplier 48 for adjusting the phases of the input time-multiplex baseband signals on a time-slot-by-time-slot basis (operation 104 ).

[0040] The phase-adjusted baseband signal in each time slot is then adjusted in amplitude by a scalar multiplier 50 based on scaling information received from beam scaling and AGC/power control processor 52 (operation 106 ). Like the bank of beam rotation weights 44 , scaling processor 52 applies different scaling on a time-slot basis in accordance with the beam scaling to be applied to a particular antenna element for each user channel and for both signal transmission and reception power control, resulting in C×E×2 different scaling functions. For example, for received signals being demodulated, the automatic gain control adjusts the signal level to be within the operational range of downstream processing, simultaneously taking into account the relative scaling of the different antenna elements for proper beamforming.

[0041] By incorporating the individual antenna element phase rotations required to form a beam pattern into baseband signal rotations already required for each channel for carrier tracking, only a modest hardware impact occurs (this impact is shown in FIG. 1 by the dotted box enclosing adder 42 and beam rotation weights 44 ). This is because the process of carrier tracking already rotates each complex baseband sample by some amount on the unit circle between 0 and 2π radians. The complexity of this rotation is the same, regardless of the amount of rotation. Thus, by adding the desired beamforming rotation to the sample-by-sample desired carrier tracking rotation, a new sum rotation is formed. This sum rotation is then applied to the existing complex multiplier 48 , which simultaneously performs carrier tracking and beam phasing, at the incremental cost of the adder 42 used to compute the rotation sum. In the same manner, the magnitude scaling component of beam weighting is incorporated into the existing AGC or power-control scalar multiplication. If the multiplication of the slowly changing beam scaling weight with the slowly changing AGC or power-control factor can be performed in software (which already calculates those individual values), then this second aspect of the beamforming computation is essentially achieved without additional hardware cost.

[0042] The phase and gain adjusted serial baseband signal stream produced by shared baseband processor is received by demultiplexer 26 and processed as previously described. Specifically, demultiplexer 26 converts the serial baseband signal to F×E parallel signals (operation 108 ) which are digitally up-converted by DUC bank 28 to produce E parallel digital IF signals corresponding to the E antenna elements (operation 110 ), which are then up-converted to RF at the analog front end and transmitted (operation 112 ).

[0043] Ultimately, the TDMA/FDMA transmission scheme must support transmission of the data symbols on each of the C user channels. The relationship between the input/output data symbol rate of the C user channels and the front end processing rates can be understood as follows. Recall that each of the F frequency-multiplexed channels is time division multiplexed (TDM) to support T users simultaneously. The instantaneous bandwidth of any one of the F frequency-multiplexed channel is equal to the number of TDM users on that channel times the maximum data rate of the users. Thus, for example, if 10 TDM users each having at 1 kbps maximum data rate are sharing one FDM channel, then that FDM channel itself is running at a 10 kbps rate. The overall number of user channels C is then related to the number of frequency channels F by the relationship C=F×T.

[0044] In the TDD example shown in FIG. 1 , shared baseband processor 38 can also be used in a time-multiplexed manner to process the baseband signal samples generated from received RF signals. Referring to FIG. 3 , wideband RF signals received at each of the E antenna elements are down-converted to IF and digitized (operation 200 ), digitally down-converted to baseband to form F×E parallel baseband signals (operation 202 ) and then time multiplexed to form a serial baseband signal stream at F×E the parallel data rate (operation 204 ) in the manner previously described. Shared baseband processor 38 operates on the serial baseband signal stream on a time-slot-by-time-slot basis to adjust the phase and amplitude of the time-multiplexed baseband samples.

[0045] In the receive case, the NCO's of the carrier phase accumulator bank 40 respectively track the carrier phase of the signal in each of the C user channels based on feedback from a phase discriminator within the corresponding baseband demodulator 58 . The bank of beam rotation weights 44 supplies beamforming weights for each channel and each antenna element in a time-multiplexed manner to adjust the rolling phase from the carrier tracker via adder 42 in accordance with the receive antenna beam. The sin/cos lookup table 46 is indexed by the adjusted phase value generated by phase adder 42 and supplies the corresponding sine/cosine multiplicands to complex multiplier 48 for adjusting the phases of the received time-multiplexed baseband signals on a time-slot-by-time-slot basis (operation 206 ). The phase adjusted baseband signal in each time slot is then adjusted in amplitude by multiplier 50 based on the required AGC and antenna element beam scaling (operation 208 ). Thus, beamforming for both modulation and demodulation can be seen to be implemented using the primarily existing baseband carrier rotation/AGC/power-control computational hardware. The beamformer/demodulator function can be used to compute the direction of arrival (DOA) of each user signal as it is processed. This not only accomplishes tracking of the received beam pattern on the signal, but also provides a known bearing for use during transmit beamforming.

[0046] The phase and amplitude adjusted baseband samples are supplied to a beamformer combiner bank 54 which, for each user channel C, combines at baseband the E simultaneously-received antenna element signals. That is, the antenna element signals forming a particular receive antenna beam via their appropriate phase and amplitude adjustments are combined to realize the resultant signal received via the particular antenna beam. The serial output data stream from beamformer combiner bank 54 has a data rate of 3 $\begin{array}{cc}{\mathrm{Fs}}_4=\frac{{\mathrm{Fs}}_1·C}{R}& \left(3\right)\end{array}$

[0047] The output of beamformer/combiner bank 54 is supplied to a channel equalizer bank 56 comprising C channel equalizers which perform channel equalization on the C respective user channel signals. The output of channel equalizer bank 56 is supplied to a baseband demodulator 58 which demodulates the baseband signals for each of the C user channels. A demultiplexer 60 serial-to-parallel converts the output of baseband demodulator 58 , and the C parallel signals undergo joint detection 62 to produce C soft detect output symbols.

[0048] As illustrated in FIG. 1 , non-simultaneous transmit/receive cases, such as TDD, allow FDM Channel-NCO-Bank and Beamforming/Carrier-Rotation/AGC/Power-Control functions to be time-shared between modulation and demodulation computation. Identical mathematical functionality is required during both modulation and demodulation, but operating on different signal data and different state information such as FDM frequency channel, carrier frequency offset, NCO phase, beam weights, and AGC/Power-Control values. Thus, the computational hardware is reused in both modes, while appropriate signal data must be routed to the hardware, and appropriate state vectors retrieved from local storage (e.g., random access memory (RAM)) and routed to the hardware. In FIG. 1 , signal data is routed at the correct time by synchronizing the switching of the RF switching elements 12 _1-E as well as closing either switches 64 and 66 to connect the shared baseband processor 38 to the receiver/demodulator circuitry or switches 68 and 70 to connect the shared baseband processor to the modulation/transmitter circuitry; internal state vectors are represented by the boxes that have depth (e.g., carrier phase accumulator bank, which is implemented as a single hardware accumulator connected to a RAM containing C*2 accumulated phase words).

[0049] It is also possible in a TDD-type system to share much of the computational complexity of the DDC bank and DUC bank (for purposes of clarity, this potential sharing is not shown in FIG. 1 ). In both cases, for instance, F*E wideband complex multiplies must be performed for TDM tuning. Furthermore, F*E FIR filters must be implemented at the wideband Fs ₁ , rate, using identical filter coefficients in both cases (for the DDC case, the filter is decimating by a factor of R, and for the DUC case the filter is interpolating by a factor of R), essentially the same hardware is required to perform the filtering operation, allowing a single efficient structure to perform both functions.

[0050] If non-beamforming prior-art modem architectures were merely extended to support multiple elements, wideband computational complexity would be increased by a factor of E. Another important aspect of the present invention is the manner in which this additional signal processing complexity due to beamforming is implemented. By exploiting several architectural innovations that perform this extended processing in a non-obvious manner, the additional capabilities are obtained at reduced implementation cost. Firstly, in the wideband DDC/DUC processing, the prior art (or extrapolation thereof) technique would simply repeat DDC/DUC modules on a per-element basis. According to the present invention, the DDC and DUC modules are broken down into constituent functions of NCO, complex multiplication, and interpolation/decimation FIR filtering. While the state vectors of those functions are unique and must be maintained for each element and frequency, both up-converting and down-converting, the computation is almost identical. Therefore, the present invention shares that processing between elements, frequencies, up-conversion, and down-conversion as is appropriate given the processing required by the input sampling rate Fs ₁ , and the arithmetic processing rate Fp. For example, if Fp/Fs ₁ , is four, then a single physical DDC/DUC hardware resource can actually be shared across four elements or frequencies. Furthermore, in a time-multiplexed transmit/receive scenario, a single computational hardware implementation can serve as both DDC and DUC. As previously mentioned, in a TDD system, the DDC and DUC NCOs produce the same frequency waveform for a given frequency channel, and can thus be directly shared.

[0051] As has already been noted, significant complexity exists in the baseband portion of the beamforming base station modem. This is true for both arithmetic computation, as well as variety and multiple-rates of data operands for frequency bands, channel time slots, and antenna elements. Additional novel features of the present invention specifically address the organization of this complexity, to produce a dataflow architecture that can be effectively implemented on a VLSI, FPGA or ASIC type device. The typically large interpolation/decimation factor R is leveraged and used to multiplex/demultiplex the F×E streams of complex data from/to the DDC/DUC processing functions. This approach reduces the wiring interconnect complexity compared to other approaches. If R is greater than the product F×E, the sequential frequency/element data stream can likely be demodulated and beamformed by a single processing unit, as shown in FIG. 1 ; otherwise, multiple units would service the excess computational demand. This also applies to the beamformer/combiner function. In a TDD system, where modulation and demodulation do not occur at the same time, this carrier-tracking/beamforming hardware is also shared for both modulation and demodulation. In an FDD system, twice the capacity would be required, either through R being at least 2×F×E, or through an additional computational block.

[0052] As illustrated in FIG. 1 , the additional functions of baseband modulation, channel equalizer, baseband demodulation, and detection are achieved through distinct hardware blocks. In the manner just described, a single instance of these processing blocks can handle all C user channels, in this case where R is greater than or equal to C. Since this modem jointly demodulates many (C) users simultaneously, advanced signal processing techniques such as joint detection are readily enabled by the present invention.

[0053] Although beamforming on each user channel C requires a relatively large amount of beamforming computation to be performed (E*C complex multiply-accumulates per sample), this computation is at baseband, thus leveraging the sampling rate reduction of 1/R due to filtering and decimation in the DDC. Consequently, the beamforming computation rate in the share baseband processor is given by 4 $\begin{array}{cc}{\mathrm{Fs}}_5=\frac{2·{\mathrm{Fs}}_1·E·C}{R}& \left(4\right)\end{array}$

[0054] If 2×E×C can be set to be approximately equal to R, then it can be seen that the entire beamforming computation for all user channels, transmit and receive, can be accomplished with a single complex multiply-accumulator running at the input sample rate Fs ₁ . This example is for the case of transmit/receive multiplexing.

[0055] The present invention improves the state of the art by mitigating the growth in wideband hardware complexity due to beamforming through novel restructuring of fundamental transceiver building blocks. At the same time, baseband hardware complexity growth is also minimized. The complex weighting required for beamforming potentially represents the largest impact of all. However, by incorporating the element rotations required to form a beam pattern into baseband signal rotations already required for each channel for carrier tracking, only a modest hardware impact occurs.

[0056] One of the principal advantages of the present invention is the potential for dramatically increasing processing capability in applications where there is a limited hardware resource. For example, where the digital signal processing associated with up/down-converting and modulation/demodulation are to be implemented on field programmable gate arrays (FPGA), there is a fixed resource and a finite number of processing/memory elements that can be formed on the chip. Consider an example where the signals being processed are voice circuits in a cellular base station, where typical processing rates are 10 to 20 kHz. If modem processing is performed at clock rates on this order, a tremendous waste of expensive hardware resources results, since, regardless of the processing rates, the modem processing requires complex multipliers, random access memories, arithmetic logic, oscillators, and other signal processing hardware to be formed in the FPGA. According to the present invention, by employing time-multiplexing in the modem processing between user channels, antenna elements and modulation/demodulation, and by operating the FPGA at 10 MHz to accommodate the time-multiplex a thousand times more voice signal processing can be performed on a comparable FPGA with roughly the same amount of circuitry therein. Thus, in additional to cost savings, the invention is advantageous in any application where smaller size and weight would be beneficial, such as in handheld or airborne units.

[0057] The present invention advantageously permits an element snapshot memory to operate at narrowband sampling rates, allowing an eased implementation for any snapshot operations required. Furthermore, these snapshots occur after narrowband channel filtering, thus containing only received signals of interest for that frequency band.

[0058] Further, integration of the beamformer with the demodulator in the present invention allows advanced adaptive algorithms to be implemented that can be enhanced by the feedback of post-demodulation metrics such as carrier-SNR/phase, symbol-SNR/phase, and error control decoding metrics.

[0059] In accordance with another aspect of the present invention, the beamformer spatial processing for each user channel is integrated with demodulation functionality, such as adaptive equalization temporal processing, allowing more complex algorithms to be implemented that jointly perform spatial/temporal optimization.

[0060] While the present invention has been described in the context of multiple user channels and certain features of the present invention are most advantageously exploited in this context, it will be understood that the present invention is nevertheless useful in the context of a single user channel or only a few user channels, and can be employed in devices such as mobile communication devices serving only a single end-user at a time. Further, the baseband time-multiplexing and shared processing techniques described herein can be employed in systems using only one of TDMA and FDMA, and has applicability in virtually any multi-user communication system employing multiplexing, including those employing code division multiple access (CDMA).

[0061] The present invention performs demodulation and detection of potentially all visible user channels in the antenna field of view. This capability facilitates the joint detection (rather than individual) of all channels simultaneously, which is known in the prior art to substantially increase cellular capacity. The present invention further enables the combined processing of beamforming, equalization, and joint detection in a single demodulation process.

[0062] Having described preferred embodiments of new and improved integrated beamformer/modem architecture, it is believed that other modifications, variations and changes will be suggested to those skilled in the art in view of the teachings set forth herein. It is therefore to be understood that all such variations, modifications and changes are believed to fall within the scope of the present invention as defined by the appended claims. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.