Title:
Semiconductor device and method of fabricating the same
Document Type and Number:
Kind Code:
A1

Abstract:
Provided is a semiconductor device and a method of fabricating the semiconductor device, in which electric characteristics of a gate insulating film thereof in the vicinity of an element isolation region are equal to electric characteristics of the gate insulating film at portions other than the vicinity of the element isolation region. A semiconductor device of the present invention includes a semiconductor substrate, shallow trench isolation regions formed in the semiconductor substrate, source and drain regions formed in the semiconductor substrate, the source and drain regions sandwiching a surface of the semiconductor substrate to define a channel, gate insulating films having equal thicknesses in a central portion of the channel and in portions contacting with on the shallow trench isolation regions, and gate electrodes formed on the gate insulating films.
Inventors:
Goda, Akira (Kanagawa-ken, JP)
Noguchi, Mitsuhiro (Kanagawa-ken, JP)
Hazama, Hiroaki (Tokyo, JP)
Application Number:
10/058946
Publication Date:
10/17/2002
Filing Date:
01/30/2002
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Referenced by:
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Export Citation:
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Assignee:
KABUSHIKI KAISHA TOSHIBA (Tokyo, JP)
Primary Class:
257/E27.103
International Classes:
(IPC1-7): H01L029/00
Attorney, Agent or Firm:
FOURTH FLOOR,OBLON SPIVAK MCCLELLAND MAIER & NEUSTADT PC (1755 JEFFERSON DAVIS HIGHWAY, ARLINGTON, VA, 22202, US)
Claims:

What is claimed is:



1. A semiconductor device comprising: a semiconductor substrate; shallow trench isolation regions formed in trenches provided in the semiconductor substrate; a pair of source and drain regions formed in the semiconductor substrate, said pair of source and drain regions using a surface of the semiconductor substrate sandwiched therebetween as a channel; a gate insulating film formed on the semiconductor substrate, in which film thicknesses thereof at a central portion of the channel and at portions contacting with the shallow trench isolation regions are equal; and a gate electrode formed on the gate insulating film.

2. The semiconductor device according to claim 1, wherein the gate insulating film includes: a first insulating film comprised of silicon and nitrogen as main constituent elements thereof; and a second insulating film formed on the first insulating film, said second insulating film being different from the first insulating film in main constituent elements, and film thickness of the second insulating film at a central portion of the channel and at portions contacting with the shallow trench isolation regions are equal.

3. The semiconductor device according to claim 1, wherein the gate insulating film includes; a first insulating film comprised of silicon and nitrogen as main constituent elements thereof; and a third insulating film formed under the first insulating film and on the semiconductor substrate, said third insulating film being different from the first insulating film in main constituent elements, and film thicknesses of the third insulating film at a central portion of the channel and at portions contacting with the shallow trench isolation regions are equal.

4. The semiconductor device according to claim 1, wherein the gate insulating film includes: a first insulating film comprised of silicon and nitrogen as main constituent elements thereof; a second insulating film formed on the first insulating film, said second insulating film being different from the first insulating film in main constituent elements; and a third insulating film formed under the first insulating film and on the semiconductor substrate, said third insulating film being different from the first insulating film in main constituent elements, and film thicknesses of the first insulating film, the second insulating film and the third insulating film, respectively, are equal at a central portion of the channel and at portions abutting on the shallow trench isolation regions.

5. The semiconductor device according to any one of claims 2 to 4, wherein the gate electrode is formed on the shallow trench isolation regions without interposition of the first insulating film.

6. The semiconductor device according to any one of claims 1 to 4, wherein a width of a portion of the semiconductor substrate, the portion being sandwiched between the shallow trench isolation regions, is not more than a width of a portion of the gate electrode, the portion being sandwiched between the shallow trench isolation regions.

7. The semiconductor device according to any one of claims 2 to 4, wherein a width of a portion of the semiconductor substrate, the portion being sandwiched between the shallow trench isolation regions is not more than a width of a portion of the first insulating film, the portion being sandwiched between the shallow trench isolation regions.

8. The semiconductor device according to claim 5, wherein a width of the first insulating film in a direction of the channel is equal to a width of the gate electrode in the direction of the channel.

9. The semiconductor device according to claim 5, wherein the gate electrode contains impurities, and an impurity concentration of the gate electrode at a portion contacting with the gate insulating film is equal to an impurity concentration thereof at portions contacting with upper planes of the shallow trench isolation regions.

10. The semiconductor device according to claim 5, wherein the gate electrode is made of polycrystalline silicon containing impurities, and the gate electrode is a continuous film without interposition of a natural oxide film therein.

11. A semiconductor device comprising: a semiconductor substrate; first shallow trench isolation regions formed in trenches provided in the semiconductor substrate; a first pair of source and drain regions formed in the semiconductor substrate, said first pair of source and drain regions using a surface of the semiconductor substrate sandwiched therebetween as a first channel; a first gate insulating film formed on the semiconductor substrate, in which film thicknesses thereof at a central portion of the first channel and at portions contacting with the first shallow trench isolation regions are equal; a first gate electrode formed on the first gate insulating film; second shallow trench isolation regions formed in trenches provided in the semiconductor substrate; a second pair of source and drain regions formed in the semiconductor substrate, said second pair of source and drain regions using a surface of the semiconductor substrate sandwiched therebetween as a second channel; a second gate insulating film formed on the semiconductor substrate, in which film thicknesses thereof at a central portion of the second channel and at portions contacting with the second shallow trench isolation regions are equal; and a second gate electrode formed on the second gate insulating film.

12. The semiconductor device according to claim 11, wherein the first shallow trench isolation regions and the second shallow trench isolation regions have concave portions on upper ends individually thereof, and depths of the concave portions provided on the first shallow trench isolation regions are smaller than depths of the concave portions provided on the second shallow trench isolation regions.

13. The semiconductor device according to claim 11, wherein upper surfaces of the first shallow trench isolation regions are formed into convex shapes, and the second shallow trench isolation regions have concave portions on upper ends thereof.

14. The semiconductor device according to claim 11, wherein the first gate insulating film includes: a first insulating film comprised of silicon and nitrogen as main constituent elements thereof; a second insulating film formed on the first insulating film, said second insulating film being different from the first insulating film in main constituent elements; and a third insulating film formed under the first insulating film and on the semiconductor substrate, said third insulating film being different from the first insulating film in main constituent elements, and the second gate insulating film is a silicon oxide film excluding nitrogen as a main constituent element thereof.

15. The semiconductor device according to any one of claims 11 to 14, wherein the first gate electrode and the second gate electrode are made of polycrystalline silicon films, which are doped with impurities of conductivity types opposite to each other.

16. The semiconductor device according to any one of claims 11 to 14, further including: a memory section having a plurality of the first gate electrodes; and a peripheral circuit section having a plurality of the second gate electrodes, wherein impurities of a first conductivity type are doped in a first number of the first gate electrode out of the plurality of the first gate electrodes, impurities of a second conductivity type are doped in a second number of the first gate electrodes, impurities of the first conductivity type are doped in a first number of the second gate electrode out of the plurality of the second gate electrodes, and impurities of the second conductivity type are doped in a second number of the second gate electrodes.

17. The semiconductor device according to any one of claims 11 to 14, wherein film thickness of the first gate electrode is equal to film thickness of the second gate electrodes.

18. The semiconductor device according to claim 16, wherein the memory section includes memory transistors and selective transistors, the peripheral circuit section includes peripheral circuit transistors, and the selective transistors have constitutions of the gate electrodes and the gate insulating films thereof, the constitutions being identical to constitutions of the gate electrodes and the gate insulating films of any of the memory transistors and the peripheral circuit transistors.

19. A method of fabricating a semiconductor device comprising: forming a gate insulating film on a semiconductor substrate; forming trenches in the semiconductor substrate after forming the gate insulating film; forming shallow trench isolation regions by filling the trenches with insulating materials; and forming a gate electrode on the gate insulating film and the shallow trench isolation regions.

20. A method of fabricating a semiconductor device comprising: forming a first insulating film on a semiconductor substrate; forming a second insulating film on the first insulating film; forming trenches in the second insulating film, the first insulating film and the semiconductor substrate; forming shallow trench isolation regions by filling the trenches with insulating materials; removing the second insulating film such that the shallow trench isolation regions protrude from an upper surface of the first insulating film; and forming a gate electrode on the first insulating film exposed and the shallow trench isolation regions.

21. The method of fabricating a semiconductor device according to claim 20, wherein forming a first insulating film is forming a stacked insulating film including a charge storing insulating film capable of storing electric charges.

22. A method of fabricating a semiconductor device comprising: forming a first gate insulating film on a semiconductor substrate at a memory section and at a peripheral circuit section, said first gate insulating film being comprised of a multilayer film including a silicon nitride film; forming trenches in the semiconductor substrate at the memory section and the peripheral circuit section after forming the first gate insulating film; forming shallow trench isolation regions by filling the trenches with insulating materials; forming a second gate insulating film at the peripheral circuit section by thermal oxidation after removing the silicon nitride film out of the first gate insulating film at the peripheral circuit section; and forming a gate electrode on the first gate insulating film, on the second insulating film and on the shallow trench isolation regions at the memory section and at the peripheral circuit section.

23. A method of forming a semiconductor device comprising: forming a first gate insulating film on a semiconductor substrate at a peripheral circuit section, which includes a high-withstand-voltage transistor region and a low-voltage transistor region, and at a memory section; removing the first gate insulating film in the low-voltage transistor region of the peripheral circuit section and at the memory section; forming a second gate insulating film over a surface of all constituents on the semiconductor substrate; forming trenches in the semiconductor substrate at the memory section and at the peripheral circuit section after forming the second gate insulating film; forming shallow trench isolation regions by filling the trenches with insulating materials; forming a low-voltage transistor gate insulating film and a high-withstand-voltage transistor gate insulating film at the peripheral circuit section by thermal oxidation, after removing the silicon nitride film out of the second gate insulating film at the peripheral circuit section; and forming a gate electrode on the gate insulating film at the memory section, on the low-voltage transistor gate insulating film, on the high-withstand-voltage transistor gate insulating film and on the shallow trench isolation regions.

24. The method of fabricating a semiconductor device according to claim 23, wherein a plurality of gate electrodes are formed in the memory section and a plurality of gate electrodes are formed in the peripheral circuit section simultaneously while forming a gate electrode, and after forming a gate electrode, the method further includes: doping impurities of a first conductivity type into a first number of the gate electrodes at the peripheral circuit section; doping impurities of a second conductivity type into a second number of the gate electrodes at the peripheral circuit section; doping impurities of the first conductivity type into the first number of the gate electrodes at the memory section; and doping impurities of the second conductivity type into the second number of the gate electrodes at the memory section.

25. A method of fabricating a semiconductor device comprising: forming a first gate insulating film on a semiconductor substrate at a memory section including a memory cell transistor region and a selective transistor region and at a peripheral circuit section including a low-voltage transistor region and a high-withstand-voltage transistor region; removing the first gate insulating film in the low-voltage transistor region of the peripheral circuit section and at the memory section; forming a second gate insulating film comprised of a multilayer film including a silicon nitride film; forming trenches in the semiconductor substrate at the memory section and at the peripheral circuit section after forming the second gate insulating film; forming shallow trench isolation regions by filling the trenches with insulating materials; forming a low-voltage transistor gate insulating film and a high-withstand-voltage transistor gate insulating film at the peripheral circuit section by thermal oxidation, after removing the silicon nitride film out of the second gate insulating film in the selective transistor region of the memory section and at the peripheral circuit section; and forming a gate electrode on the gate insulating film in the memory cell transistor region, on the gate insulating film in the selective transistor region, on the low-voltage transistor gate insulating film, on the high-withstand-voltage transistor gate insulating film and on the shallow trench isolation regions.

26. A semiconductor device comprising: a semiconductor substrate; an element region of a first conductivity type formed in the semiconductor substrate, said element region having four sides substantially; a source electrode and a drain electrode formed on two opposing sides of the element region, respectively, said source electrode and said drain electrode being of a conductivity type reverse to the first conductivity type; a first gate insulating film provided on the element region; a charge storing region provided on the first gate insulating film, including an insulating film capable of storing data as well as electrically writable and erasable, said charge storing region having two edges on two sides without the source electrode and the drain electrode formed thereon; and at least one gate electrode provided on the charge storing region, said gate electrode being formed in a manner that distance of two opposing sides without formation of the source electrode and the drain electrode on a lower plane of the gate electrode is made shorter than distance between two edges on the two opposing sides on an upper plane of the charge storing region without formation of the source electrode and the drain electrode.

27. The semiconductor device according to claim 26, wherein the distance of the two opposing sides without formation of the source electrode and the drain electrode on the lower plane of the gate electrode is shorter than the distance between the two edges of the charge storing region by a value in a range from 10 nm to 100 nm.

28. The semiconductor device according to claim 26, wherein the distance between the two edges of the charge storing region is longer than distance of the two opposing sides of the element region without formation of the source electrode and the drain electrode on a plane of the element region facing the first gate insulating film.

29. The semiconductor device according to claim 26, wherein the distance between the two edges of the charge storing region is longer than distance of the two opposing sides of the element region without formation of the source electrode and the drain electrode on a plane of the element region facing the first gate insulating film by a value in a range from 1 nm to 30 nm.

30. A semiconductor device comprising: a semiconductor substrate; an element region of a first conductivity type formed in the semiconductor substrate, said element region having four sides substantially; a first gate insulating film provided on the element region; a source electrode and a drain electrode formed in the semiconductor substrate, said source electrode and said drain electrode being of a conductivity type reverse to the first conductivity type; a charge storing region provided on the first gate insulating film, said charge storing region including: an insulating film capable of storing data as well as electrically writable and erasable; two edges on two opposing sides; and in a state where at least the source electrode and the drain electrode are in a conductive state when a direction of currents flowing on the element region is defined as a first direction and a direction orthogonal to the first direction on the semiconductor substrate is defined as a second direction, two edges in the second direction on an upper plane of the charge storing region; at least one gate electrode provided on the charge storing region, said gate electrode being formed in a manner that lengths of two sides in the second direction on a lower plane of the gate electrode are made shorter than distance between the two edges of the charge storing region in the second direction on an upper plane of the charge storing region; and at least two current terminals connected to the source electrode and the drain electrode, respectively, to detect a state of data storage of the charge storing region depending on any one of a conductive state and an interrupted state between the source electrode and the drain electrode.

31. The semiconductor device according to claim 30, wherein the lengths of the two sides of the gate electrode in the second direction on a plane facing the charge storing region are made shorter than the distance between the two edges of the charge storing region in the second direction by a value in a range from 10 nm to 100 nm.

32. The semiconductor device according to claim 30, wherein the distance between the two edges of the charge storing region in the second direction on a plane facing the first gate insulating film of the element region is made longer than a length of the element region in the second direction.

33. The semiconductor device according to claim 30, wherein distance between the two edges of the charge storing region in the second direction on a plane facing the first gate insulating film of the element region is made longer than a length of the element region in the second direction by a value in a range from 1 nm to 30 nm.

34. A semiconductor device comprising: a semiconductor substrate; an element region formed in the semiconductor substrate; a first gate insulating film provided on the element region; at least one gate electrode; an element isolation region formed on the semiconductor substrate, said element isolation region abutting on at least a part of the gate electrode; and a charge storing region provided on the first gate insulating film, said charge storing region including an insulating film capable of storing data as well as electrically writable and erasable and having an edge positioned in the element isolation region.

35. The semiconductor device according to claim 34, wherein the edge of the charge storing region penetrates into the element isolation region by a value in a range from 0.5 nm to 15 nm.

36. The semiconductor device according to any one of claims 26 to 35, wherein the gate electrode includes: a lower conductor defined by a rectangular region having two sides substantially parallel to the first direction and two sides substantially parallel to the second direction; and an upper conductor having any pair of the two opposing sides substantially parallel to the first direction and the two opposing sides substantially parallel to the second direction of the lower conductor in common, said upper conductor being provided for electrically connecting lower conductors in a plurality of adjacent gate electrodes.

37. The semiconductor device according to any one of claims 26 to 35, further comprising: a sidewall insulating film formed on a sidewall portion of the gate electrode, wherein assuming that a face of the sidewall insulating film contacting with the gate electrode is a first side, an edge of the charge storing insulating film facing the gate electrode is formed beyond the first side to a side without formation of the gate electrode.

38. The semiconductor device according to any one of claims 26 to 35, further comprising: a second gate insulating film provided on the charge storing region, wherein the gate electrode is formed on the second gate insulating film.

39. A semiconductor device comprising: a semiconductor substrate; an element region of a first conductivity type formed on the semiconductor substrate, said element region having four sides substantially; a first gate insulating film formed on the element region; a charge storing region formed on the first gate insulating film, having an insulating film capable of storing data as well as electrically writable and erasable; at least one gate electrode provided on the charge storing region; a source electrode and a drain electrode of a conductivity type reverse to the first conductivity type, said electrodes being formed on two opposing sides of the element region, respectively; and a second gate insulating film disposed between the charge storing region and the gate electrode, said second gate insulating film being formed thicker at a portion of the second gate insulating film under edges of the gate electrode than a portion of the second gate insulating film under a central portion of the gate electrode facing the charge storing region, regarding two sides of the second gate insulating film without formation of the gate electrode and the drain electrode.

40. The semiconductor device according to claim 39, wherein a thickness of the second gate insulating film is formed thicker by a thickness in a range from 0.5 nm to 50 nm at the portion under the edges of the gate electrode than the portion of the second gate insulating film under the central portion of the gate electrode facing the charge storing region, regarding two sides of the second gate insulating film without formation of the gate electrode and the drain electrode.

41. A semiconductor device comprising: a semiconductor substrate; an element region of a first conductivity type formed on the semiconductor substrate, said element region having four sides substantially; a first gate insulating film provided on the element region; a charge storing region provided on the first gate insulating film, said charge storing region being comprised of an insulating film capable of storing data as well as writable and erasable and having two edges on two opposing sides; at least one gate electrode provided on the charge storing region; a source electrode and a drain electrode of a conductivity type reverse to the first conductivity type, said electrodes being provided in the semiconductor substrate; current terminals provided in the source electrode and the drain electrode, respectively, for detecting a state of storage of the charge storing region depending on any one of a conductive state and an interrupted state between the source electrode and the drain electrode; and a second gate insulating film disposed between the charge storing region and the gate electrode, in a case where a direction of currents flowing at least between the current terminals in a conductive state is defined as a first direction and a direction perpendicular to the first direction on the semiconductor substrate is defined as a second direction, a thickness of portions of the second gate insulating film under edges of the gate electrode in the second direction being thicker than a thickness of the second gate insulating film in the second direction under a central portion of the gate electrode facing the charge storing region.

42. The semiconductor device according to claim 41, wherein a thickness of the second gate insulating film is formed thicker by a thickness in a range from 0.5 nm to 50 nm at the portions under the edges of the gate electrode in the second direction than the portion of the second gate insulating film under the central portion of the gate electrode facing the charge storing region.

43. The semiconductor device according to any one of claims 39 to 42, wherein a thickness of the first gate insulating film is formed thicker at portions under the edges of the gate electrode than a portion of the first gate insulating film under a central portion of the gate electrode facing the charge storing region.

44. The semiconductor device according to any one of claims 39 to 42, wherein the gate electrode has a stacked conductor region comprised of at least two layers of a lower conductor and an upper conductor in an order from beneath, the lower conductor is defined by a rectangular region having two sides substantially parallel to the first direction and two sides substantially parallel to the second direction, and the upper conductor has any pair of the two opposing sides substantially parallel to the first direction and the two opposing sides substantially parallel to the second direction of the lower conductor in common, said upper conductor being provided for electrically connecting a plurality of the adjacent lower conductors.

45. The semiconductor device according to any one of claims 26 to 35, and 39 to 42 further comprising: an element isolation region disposed adjacently to at least a part of the gate electrode, said element isolation region including an element isolation trench formed by self-alignment with respect to at least any one of the gate electrode, the first gate insulating film, the charge storing insulating film and the second gate insulating film.

46. The semiconductor device according to any one of claims 26 to 35, and 39 to 42, wherein a plurality of the gate electrodes are disposed on the semiconductor substrate, and the charge storing layers of the plurality of the gate electrodes are severed among the gate electrodes adjacent to one another.

47. The semiconductor device according to any one of claims 26 to 35, and 39 to 42, further comprising: an element isolation region disposed adjacently to at least a part of the first gate electrode, said element isolation region including a high-density impurity region provided in the semiconductor substrate.

Description:

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application is based upon and claims benefit of priority from the prior Japanese Patent Application No. 2001-29174, filed on Feb. 6, 2001 and Japanese Patent Application No. 2001-317620, filed on Oct. 16, 2001; the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a semiconductor device, more specifically, to a minute semiconductor device requiring high-grade characteristics of a gate insulating film therein and a method of fabricating the same.

[0004] 2. Description of the Related Art

[0005] A memory cell comprised of a so-called metal oxide nitride oxide semiconductor (hereinafter referred to as “MONOS”: metal-silicon oxide film-silicon nitride film-silicon oxide film-semiconductor) is known as one type of electrically writable and erasable non-volatile semiconductor memory devices, which stores data by trapping electric charges inside a silicon nitride film. A MONOS memory is capable of writing and erasing operations with relatively low voltage compared with a floating-gate memory. In addition, the MONOS memory cell comprised of a single layer gate structure has a smaller aspect ratio of a gate in comparison with the floating-gate memory cell that requires a multilayer gate structure. Therefore, the MONOS memory cell has an advantage that it is suitable for miniaturizing of elements therein.

[0006] A cross section of a conventional MONOS memory cell prepared by local oxidation (LOCOS) isolation is illustrated in FIG. 94 .

[0007] In FIG. 94, a tunnel insulating film 101 of a memory cell is formed on a semiconductor substrate 100 , and an element isolation region 102 with a film thickness greater than that of the tunnel insulating film 101 is formed so as to sandwich the tunnel insulating film 101 . On the surfaces of the element isolation region 102 and the tunnel insulating film 101 , formed is a charge storing layer 103 made of a silicon nitride film. A barrier insulating film 104 is formed on the charge storing layer 103 . Furthermore, a gate electrode 105 is formed on the barrier insulating film 104 .

[0008] Incidentally, shallow trench isolation (STI) is becoming an important technology instead of the conventional LOCOS isolation as miniaturizing progresses. In particular, as an element isolation method suitable for floating-gate non-volatile memories, self-aligned STI is proposed (“A 0.67 μm 2 SELF-ALIGNED SHALLOW TRENCH ISOLATION CELL (SA-STI CELL) FOR 3V-only 256 Mbit NAND EEPROMs” IEDM Tech. Dig. 1994 pp 61-64). There, a gate insulating film formed under a floating gate is made in a thickness greater than other parts at an edge of a gate electrode. In the self-aligned STI, by forming element isolation trenches by self-alignment with respect to the floating gate, which is a charge storing layer, concentration of electric fields at the element isolation trenches attributable to penetrating of a part of the gate electrode into the element isolation edge is prevented. As a result, unevenness of cell characteristics can be improved whereby high reliability is achieved.

[0009] In FIG. 1 and FIG. 3 ( a ) among others in Japanese Patent Publication No. 4-12573, disclosed is a structure of a MONOS non-volatile semiconductor memory device arranged to allow a gate insulating film in a region of an interface with a surrounding selective oxide film to reside entirely inside a trench in order to prevent a sidewalk phenomenon.

[0010] It should be further noted that FIG. 4 among others in Japanese Patent Publication No. 11-330277 discloses the fact that a non-volatile memory using an insulating film as a charge storing layer as in MONOS shows inferior read-disturb characteristics.

[0011] The following problems arise in the above-described conventional semiconductor device.

[0012] An oxide film is formed thick at an element isolation edge 106 attributable to an influence by thermal oxidation for forming an element isolation region, which results in deterioration of write operation and erase operation characteristics in that region. In other words, since the thickness of the insulating film grows large at the element isolation edge, electric fields thereabout are weakened and thresholds are thereby lowered.

[0013] Since electric charges are trapped in the silicon nitride film which is the insulating film in the MONOS structure, carriers do not move within the charge storing layer. For this reason, when a write pulse is supplied, only a channel edge is left low in a threshold. Such phenomenon is observed as a subthreshold leakage or a hump with respect to transistor characteristics. The phenomenon referred to as sidewalk is problematic in the MONOS memory cell because the phenomenon narrows a writing/erasing window thereof.

[0014] According to the above-mentioned Japanese Patent Publication No. 4-12573, a trench is provided in a semiconductor substrate and an insulating film is provided inside the trench. However, the thickness of the film is larger near an element isolation region thereof. Accordingly, control characteristics are deteriorated due to occurrence of concentration of electric fields thereabout.

BRIEF SUMMARY OF THE INVENTION

[0015] A feature of the present invention is a semiconductor device including: a semiconductor substrate; shallow trench isolation regions formed in trenches provided in the semiconductor substrate; a pair of source and drain regions formed in the semiconductor substrate, the pair of source and drain regions using a surface of the semiconductor substrate sandwiched therebetween as a channel; a gate insulating film formed on the semiconductor substrate, in which film thicknesses thereof at a central portion of the channel and at portions contacting with the shallow trench isolation regions are equal; and a gate electrode formed on the gate insulating film.

[0016] Another aspect of the present invention is a semiconductor device including: a semiconductor substrate; first shallow trench isolation regions formed in trenches provided in the semiconductor substrate; a first pair of source and drain regions formed in the semiconductor substrate, the first pair of source and drain regions using a surface of the semiconductor substrate sandwiched therebetween as a first channel; a first gate insulating film formed on the semiconductor substrate, in which film thicknesses thereof at a central portion of the first channel and at portions contacting with the first shallow trench isolation regions are equal; a first gate electrode formed on the first gate insulating film; second shallow trench isolation regions formed in trenches provided in the semiconductor substrate; a second pair of source and drain regions formed in the semiconductor substrate, the second pair of source and drain regions using a surface of the semiconductor substrate sandwiched therebetween as a second channel; a second gate insulating film formed on the semiconductor substrate, in which film thicknesses thereof at a central portion of the second channel and at portions contacting with the second shallow trench isolation regions are equal; and a second gate electrode formed on the second gate insulating film.

[0017] Another aspect of the present invention is a method of fabricating a semiconductor device, including: forming a gate insulating film on a semiconductor substrate; forming trenches in the semiconductor substrate after forming the gate insulating film; forming shallow trench isolation regions by filling the trenches with insulating materials; and forming a gate electrode on the gate insulating film and the shallow trench isolation regions.

[0018] Another aspect of the present invention is a method of fabricating a semiconductor device, including: forming a first insulating film on a semiconductor substrate; forming a second insulating film on the first insulating film; forming trenches in the second insulating film, the first insulating film and the semiconductor substrate; forming shallow trench isolation regions by filling the trenches with insulating materials; removing the second insulating film such that the shallow trench isolation regions protrude from an upper surface of the first insulating film; and forming a gate electrode on the first insulating film exposed and the shallow trench isolation regions.

[0019] Another aspect of the present invention is a method of fabricating a semiconductor device, including: forming a first gate insulating film on a semiconductor substrate at a memory section and at a peripheral circuit section, the first gate insulating film being comprised of a multilayer film including a silicon nitride film; forming trenches in the semiconductor substrate at the memory section and the peripheral circuit section after forming the first gate insulating film; forming shallow trench isolation regions by filling the trenches with insulating materials; forming a second gate insulating film at the peripheral circuit section by thermal oxidation after removing the silicon nitride film out of the first gate insulating film at the peripheral circuit section; and forming a gate electrode on the first gate insulating film, on the second insulating film and on the shallow trench isolation regions at the memory section and at the peripheral circuit section.

[0020] Another aspect of the present invention is a method of fabricating a semiconductor device, including: forming a first gate insulating film on a semiconductor substrate at a peripheral circuit section, which includes a high-withstand-voltage transistor region and a low-voltage transistor region, and at a memory section; removing the first gate insulating film in the low-voltage transistor region of the peripheral circuit section and at the memory section; forming a second gate insulating film over a surface of all constituents on the semiconductor substrate; forming trenches in the semiconductor substrate at the memory section and at the peripheral circuit section after forming the second gate insulating film; forming shallow trench isolation regions by filling the trenches with insulating materials; forming a low-voltage transistor gate insulating film and a high-withstand-voltage transistor gate insulating film at the peripheral circuit section by thermal oxidation, after removing the silicon nitride film out of the second gate insulating film at the peripheral circuit section; and forming a gate electrode on the gate insulating film at the memory section, on the low-voltage transistor gate insulating film, on the high-withstand-voltage transistor gate insulating film and on the shallow trench isolation regions.

[0021] Another aspect of the present invention is a method of fabricating a semiconductor device, including: forming a first gate insulating film on a semiconductor substrate at a memory section including a memory cell transistor region and a selective transistor region and at a peripheral circuit section including a low-voltage transistor region and a high-withstand-voltage transistor region; removing the first gate insulating film in the low-voltage transistor region of the peripheral circuit section and at the memory section; forming a second gate insulating film comprised of a multilayer film including a silicon nitride film; forming trenches in the semiconductor substrate at the memory section and at the peripheral circuit section after forming the second gate insulating film; forming shallow trench isolation regions by filling the trenches with insulating materials; forming a low-voltage transistor gate insulating film and a high-withstand-voltage transistor gate insulating film at the peripheral circuit section by thermal oxidation, after removing the silicon nitride film out of the second gate insulating film in the selective transistor region of the memory section and at the peripheral circuit section; and forming a gate electrode on the gate insulating film in the memory cell transistor region, on the gate insulating film in the selective transistor region, on the low-voltage transistor gate insulating film, on the high-withstand-voltage transistor gate insulating film and on the shallow trench isolation regions.

[0022] Another aspect of the present invention is a semiconductor device including; a semiconductor substrate; an element region of a first conductivity type formed in the semiconductor substrate, the element region having four sides substantially; a source electrode and a drain electrode formed on two opposing sides of the element region, respectively, the source electrode and the drain electrode being of a conductivity type reverse to the first conductivity type; a first gate insulating film provided on the element region; a charge storing region provided on the first gate insulating film, including an insulating film capable of storing data as well as electrically writable and erasable, the charge storing region having two edges on two sides without the source electrode and the drain electrode formed thereon; and at least one gate electrode provided on the charge storing region, the gate electrode being formed in a manner that distance of two opposing sides without formation of the source electrode and the drain electrode on a lower plane of the gate electrode is made shorter than distance between two edges on the two opposing sides on an upper plane of the charge storing region without formation of the source electrode and the drain electrode.

[0023] Another aspect of the present invention is a semiconductor device including: a semiconductor substrate; an element region of a first conductivity type formed in the semiconductor substrate, the element region having four sides substantially; a first gate insulating film provided on the element region; a source electrode and a drain electrode formed in the semiconductor substrate, the source electrode and the drain electrode being of a conductivity type reverse to the first conductivity type; a charge storing region provided on the first gate insulating film, the charge storing region including: an insulating film capable of storing data as well as electrically writable and erasable; two edges on two opposing sides; and in a state where at least the source electrode and the drain electrode are in a conductive state when a direction of currents flowing on the element region is defined as a first direction and a direction orthogonal to the first direction on the semiconductor substrate is defined as a second direction, two edges in the second direction on an upper plane of the charge storing region; at least one gate electrode provided on the charge storing region, the gate electrode being formed in a manner that lengths of two sides in the second direction on a lower plane of the gate electrode are made shorter than distance between the two edges of the charge storing region in the second direction on an upper plane of the charge storing region; and at least two current terminals connected to the source electrode and the drain electrode, respectively, to detect a state of data storage of the charge storing region depending on any one of a conductive state and an interrupted state between the source electrode and the drain electrode.

[0024] Another aspect of the present invention is a semiconductor device including: a semiconductor substrate; an element region formed in the semiconductor substrate; a first gate insulating film provided on the element region; at least one gate electrode; an element isolation region formed on the semiconductor substrate, the element isolation region abutting on at least a part of the gate electrode; and a charge storing region provided on the first gate insulating film, the charge storing region including an insulating film capable of storing data as well as electrically writable and erasable and having an edge positioned in the element isolation region.

[0025] Another aspect of the present invention is a semiconductor device including: a semiconductor substrate; an element region of a first conductivity type formed on the semiconductor substrate, the element region having four sides substantially; a first gate insulating film formed on the element region; a charge storing region formed on the first gate insulating film, having an insulating film capable of storing data as well as electrically writable and erasable; at least one gate electrode provided on the charge storing region; a source electrode and a drain electrode of a conductivity type reverse to the first conductivity type, the electrodes being formed on two opposing sides of the element region, respectively; and a second gate insulating film disposed between the charge storing region and the gate electrode, the second gate insulating film being formed thicker at a portion of the second gate insulating film under edges of the gate electrode than a portion of the second gate insulating film under a central portion of the gate electrode facing the charge storing region, regarding two sides of the second gate insulating film without formation of the gate electrode and the drain electrode.

[0026] Another aspect of the present invention is a semiconductor device including: a semiconductor substrate; an element region of a first conductivity type formed on the semiconductor substrate, the element region having four sides substantially; a first gate insulating film provided on the element region; a charge storing region provided on the first gate insulating film, the charge storing region being comprised of an insulating film capable of storing data as well as writable and erasable and having two edges on two opposing sides; at least one gate electrode provided on the charge storing region; a source electrode and a drain electrode of a conductivity type reverse to the first conductivity type, the electrodes being provided in the semiconductor substrate; current terminals provided in the source electrode and the drain electrode, respectively, for detecting a state of storage of the charge storing region depending on any one of a conductive state and an interrupted state between the source electrode and the drain electrode; and a second gate insulating film disposed between the charge storing region and the gate electrode, in a case where a direction of currents flowing at least between the current terminals in a conductive state is defined as a first direction and a direction perpendicular to the first direction on the semiconductor substrate is defined as a second direction, a thickness of portions of the second gate insulating film under edges of the gate electrode in the second direction being thicker than a thickness of the second gate insulating film in the second direction under a central portion of the gate electrode facing the charge storing region.

BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently embodiments of the invention, and together with the general description given above and the detailed description of the invention given below, serve to explain the principles of the invention.

[0028] FIG. 1 is a cross-sectional view in a row direction, showing a constitution of a memory section according to a first embodiment of the present invention.

[0029] FIG. 2 is a cross-sectional view in the row direction, showing a constitution of a memory section of a prototype of the first embodiment.

[0030] FIG. 3 is an enlarged view of an edge portion of a shallow trench isolation region in the row direction of the memory section of the prototype of the first embodiment.

[0031] FIG. 4 is a graph showing voltage-current characteristics in a write operation mode for respective regions of a memory cell transistor of the prototype of the first embodiment.

[0032] FIG. 5 is another graph showing the voltage-current characteristics in the write operation mode of the memory cell transistor of the prototype of the first embodiment.

[0033] FIG. 6 is a graph showing voltage-current characteristics in a write operation mode and an erase operation mode of the memory cell transistor of the prototype of the first embodiment.

[0034] FIG. 7 is a cross-sectional view in the row direction of a high-voltage transistor of the first embodiment.

[0035] FIG. 8 is a cross-sectional view in the row direction of a low-voltage transistor of the first embodiment.

[0036] FIG. 9 is a plan view showing a constitution of the memory section of the first embodiment.

[0037] FIG. 10 is a cross-sectional view in a column direction of the memory section of the first embodiment.

[0038] FIG. 11 is a circuit diagram showing a NAND string of the memory section of the first embodiment.

[0039] FIG. 12A is a cross-sectional view in the row direction, showing one step of a method of fabricating a memory cell transistor and a selective transistor of the first embodiment; FIG. 12B is a cross-sectional view in the row direction, showing one step of a method of fabricating a low-voltage transistor of the first embodiment; and FIG. 12C is a cross-sectional view in the row direction, showing one step of a method of fabricating a high-withstand-voltage transistor of the first embodiment.

[0040] FIG. 13A is a cross-sectional view in the row direction, showing one step of the method of fabricating the memory cell transistor and the selective transistor of the first embodiment; FIG. 13B is a cross-sectional view in the row direction, showing one step of the method of fabricating the low-voltage transistor of the first embodiment; and FIG. 13C is a cross-sectional view in the row direction, showing one step of the method of fabricating the high-withstand-voltage transistor of the first embodiment.

[0041] FIG. 14A is a cross-sectional view in the row direction, showing one step of the method of fabricating the memory cell transistor and the selective transistor of the first embodiment; FIG. 14B is a cross-sectional view in the row direction, showing one step of the method of fabricating the low-voltage transistor of the first embodiment; and FIG. 14C is a cross-sectional view in the row direction, showing one step of the method of fabricating the high-withstand-voltage transistor of the first embodiment.

[0042] FIG. 15A is a cross-sectional view in the row direction, showing one step of the method of fabricating the memory cell transistor and the selective transistor of the first embodiment; FIG. 15B is a cross-sectional view in the row direction, showing one step of the method of fabricating the low-voltage transistor of the first embodiment; and FIG. 15C is a cross-sectional view in the row direction, showing one step of the method of fabricating the high-withstand-voltage transistor of the first embodiment.

[0043] FIG. 16A is a cross-sectional view in the row direction, showing one step of the method of fabricating the memory cell transistor and the selective transistor of the first embodiment; FIG. 16B is a cross-sectional view in the row direction, showing one step of the method of fabricating the low-voltage transistor of the first embodiment; and FIG. 16C is a cross-sectional view in the row direction, showing one step of the method of fabricating the high-withstand-voltage transistor of the first embodiment.

[0044] FIG. 17A is a cross-sectional view in the row direction, showing one step of the method of fabricating the memory cell transistor and the selective transistor of the first embodiment; FIG. 17B is a cross-sectional view in the row direction, showing one step of the method of fabricating the low-voltage transistor of the first embodiment; and FIG. 17C is a cross-sectional view in the row direction, showing one step of the method of fabricating the high-withstand-voltage transistor of the first embodiment.

[0045] FIG. 18A is a cross-sectional view in the row direction, showing one step of the method of fabricating the memory cell transistor and the selective transistor of the first embodiment; FIG. 18B is a cross-sectional view in the row direction, showing one step of the method of fabricating the low-voltage transistor of the first embodiment; and FIG. 18C is a cross-sectional view in the row direction, showing one step of the method of fabricating the high-withstand-voltage transistor of the first embodiment.

[0046] FIG. 19A is a cross-sectional view in the row direction, showing one step of the method of fabricating the memory cell transistor and the selective transistor of the first embodiment; FIG. 19B is a cross-sectional view in the row direction, showing one step of the method of fabricating the low-voltage transistor of the first embodiment; and FIG. 19C is a cross-sectional view in the row direction, showing one step of the method of fabricating the high-withstand-voltage transistor of the first embodiment.

[0047] FIG. 20A is a cross-sectional view in the row direction, showing one step of the method of fabricating the memory cell transistor and the selective transistor of the first embodiment; FIG. 20B is a cross-sectional view in the row direction, showing one step of the method of fabricating the low-voltage transistor of the first embodiment; and FIG. 20C is a cross-sectional view in the row direction, showing one step of the method of fabricating the high-withstand-voltage transistor of the first embodiment.

[0048] FIG. 21A is a cross-sectional view in the row direction, showing one step of the method of fabricating the memory cell transistor and the selective transistor of the first embodiment; FIG. 21B is a cross-sectional view in the row direction, showing one step of the method of fabricating the low-voltage transistor of the first embodiment; and FIG. 21C is a cross-sectional view in the row direction, showing one step of the method of fabricating the high-withstand-voltage transistor of the first embodiment.

[0049] FIG. 22A is a cross-sectional view in the row direction, showing one step of the method of fabricating the memory cell transistor and the selective transistor of the first embodiment; FIG. 22B is a cross-sectional view in the row direction, showing one step of the method of fabricating the low-voltage transistor of the first embodiment; and FIG. 22C is a cross-sectional view in the row direction, showing one step of the method of fabricating the high-withstand-voltage transistor of the first embodiment.

[0050] FIG. 23A is a cross-sectional view in the row direction, showing one step of the method of fabricating the memory cell transistor and the selective transistor of the first embodiment; FIG. 23B is a cross-sectional view in the row direction, showing one step of the method of fabricating the low-voltage transistor of the first embodiment; and FIG. 23C is a cross-sectional view in the row direction, showing one step of the method of fabricating the high-withstand-voltage transistor of the first embodiment.

[0051] FIG. 24A is a cross-sectional view in the row direction, showing one step of the method of fabricating the memory cell transistor and the selective transistor of the first embodiment; FIG. 24B is a cross-sectional view in the row direction, showing one step of the method of fabricating the low-voltage transistor of the first embodiment; and FIG. 24C is a cross-sectional view in the row direction, showing one step of the method of fabricating the high-withstand-voltage transistor of the first embodiment.

[0052] FIG. 25A is a cross-sectional view in the row direction, showing one step of the method of fabricating the memory cell transistor and the selective transistor of the first embodiment; FIG. 25B is a cross-sectional view in the row direction, showing one step of the method of fabricating the low-voltage transistor of the first embodiment; and FIG. 25C is a cross-sectional view in the row direction, showing one step of the method of fabricating the high-withstand-voltage transistor of the first embodiment.

[0053] FIG. 26A is a cross-sectional view in the row direction, showing one step of the method of fabricating the memory cell transistor and the selective transistor of the first embodiment; FIG. 26B is a cross-sectional view in the row direction, showing one step of the method of fabricating the low-voltage transistor of the first embodiment; and FIG. 26C is a cross-sectional view in the row direction, showing one step of the method of fabricating the high-withstand-voltage transistor of the first embodiment.

[0054] FIG. 27A is a cross-sectional view in the row direction, showing one step of the method of fabricating the memory cell transistor and the selective transistor of the first embodiment; FIG. 27B is a cross-sectional view in the row direction, showing one step of the method of fabricating the low-voltage transistor of the first embodiment; and FIG. 27C is a cross-sectional view in the row direction, showing one step of the method of fabricating the high-withstand-voltage transistor of the first embodiment.

[0055] FIG. 28 is a cross-sectional view in the column direction, showing a constitution of a memory section of a second embodiment.

[0056] FIG. 29 is a circuit diagram showing a NAND string of the memory section of the second embodiment.

[0057] FIG. 30A is a top plan view of a semiconductor device of a prototype of a third embodiment; FIG. 30B is a cross-sectional view taken along the “C-D” line of FIG. 30A showing the semiconductor device of the prototype of the third embodiment; and FIG. 30C is a cross-sectional view taken along the “E-F” line of FIG. 30A showing the semiconductor device of the prototype of the third embodiment.

[0058] FIG. 31A is an equivalent circuit diagram corresponding to the cross section of FIG. 30B relevant to the semiconductor device of the prototype of the third embodiment; FIG. 31B is an equivalent circuit diagram corresponding to the cross section of FIG. 30C relevant to the semiconductor device of the prototype of the third embodiment; and FIG. 31C is a graph showing characteristics between drain currents and gate voltage of the semiconductor device corresponding to the prototype of the third embodiment.

[0059] FIG. 32A is a top plan view of a semiconductor device of the third embodiment; FIG. 32B is a cross-sectional view taken along the “G-H” line of FIG. 32A showing the semiconductor device of the third embodiment; and FIG. 32C is a cross-sectional view taken along the “I-J” line of FIG. 32A showing the semiconductor device of the third embodiment.

[0060] FIG. 33A is an equivalent circuit diagram corresponding to the cross section of FIG. 32B relevant to the third embodiment; FIG. 33B is an equivalent circuit diagram corresponding to the cross section of FIG. 32C relevant to the third embodiment; FIG. 33C is an equivalent circuit diagram showing simplification of FIG. 33A ; and FIG. 33D is an equivalent circuit diagram showing simplification of FIG. 33B .

[0061] FIG. 34 is an enlarged cross-sectional view of a part of FIG. 32C which is the cross-sectional view of the semiconductor device according to the third embodiment.

[0062] FIG. 35A is a cross-sectional view showing one step of a method of fabricating the semiconductor device according to the third embodiment, corresponding to a cross section taken along the “I-J” line of FIG. 32A ; and FIG. 35B is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the third embodiment, corresponding to a cross section taken along the “G-H” line of FIG. 32A .

[0063] FIG. 36A is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the third embodiment, corresponding to the cross section taken along the “I-J” line of FIG. 32A ; and FIG. 36B is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the third embodiment, corresponding to the cross section taken along the “G-H” line of FIG. 32A .

[0064] FIG. 37A is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the third embodiment, corresponding to the cross section taken along the “I-J” line of FIG. 32A ; and FIG. 37B is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the third embodiment, corresponding to the cross section taken along the “G-H” line of FIG. 32A .

[0065] FIG. 38A is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the third embodiment, corresponding to the cross section taken along the “I-J” line of FIG. 32A ; and FIG. 38B is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the third embodiment, corresponding to the cross section taken along the “G-H” line of FIG. 32A .

[0066] FIG. 39A is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the third embodiment, corresponding to the cross section taken along the “I-J” line of FIG. 32A ; and FIG. 39B is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the third embodiment, corresponding to the cross section taken along the “G-H” line of FIG. 32A .

[0067] FIG. 40A is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the third embodiment, corresponding to the cross section taken along the “I-J” line of FIG. 32A ; and FIG. 40B is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the third embodiment, corresponding to the cross section taken along the “G-H” line of FIG. 32A .

[0068] FIG. 41A is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the third embodiment, corresponding to the cross section taken along the “I-J” line of FIG. 32A ; and FIG. 41B is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the third embodiment, corresponding to the cross section taken along the “G-H” line of FIG. 32A .

[0069] FIG. 42A is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the third embodiment, corresponding to the cross section taken along the “I-J” line of FIG. 32A ; and FIG. 42B is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the third embodiment, corresponding to the cross section taken along the “G-H” line of FIG. 32A .

[0070] FIG. 43A is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the third embodiment, corresponding to the cross section taken along the “I-J” line of FIG. 32A ; and FIG. 43B is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the third embodiment, corresponding to the cross section taken along the “G-H” line of FIG. 32A .

[0071] FIG. 44 is a cross-sectional view showing a semiconductor device according to a modified example of the third embodiment, corresponding to a part of a cross section taken along the “I-J” line of FIG. 32A .

[0072] FIG. 45 is a cross-sectional view showing one step of a method of fabricating the semiconductor device according to the modified example of the third embodiment, corresponding to the cross section taken along the “I-J” line of FIG. 32A .

[0073] FIG. 46 is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the modified example of the third embodiment, corresponding to the cross section taken along the “I-J” line of FIG. 32A .

[0074] FIG. 47 is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the modified example of the third embodiment, corresponding to the cross section taken along the “I-J” line of FIG. 32A .

[0075] FIG. 48 is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the modified example of the third embodiment, corresponding to the cross section taken along the “I-J” line of FIG. 32A .

[0076] FIG. 49 is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the modified example of the third embodiment, corresponding to the cross section taken along the “I-J” line of FIG. 32A .

[0077] FIG. 50A is a top plan view of a semiconductor device of a prototype of a fourth embodiment; FIG. 50B is a cross-sectional view taken along the “K-L” line of FIG. 50A showing the semiconductor device of the prototype of the fourth embodiment; and FIG. 50C is a cross-sectional view taken along the “M-N” line of FIG. 50A showing the semiconductor device of the prototype of the fourth embodiment.

[0078] FIG. 51A is an equivalent circuit diagram corresponding to the cross section of FIG. 50B relevant to the semiconductor device of the prototype of the fourth embodiment; FIG. 51B is an equivalent circuit diagram corresponding to the cross section of FIG. 50C relevant to the semiconductor device of the prototype of the fourth embodiment; and FIG. 51C is a graph showing characteristics between drain currents and gate voltage of the semiconductor device corresponding to the prototype of the fourth embodiment.

[0079] FIG. 52A is a top plan view of a semiconductor device of the fourth embodiment; FIG. 52B is a cross-sectional view taken along the “O-P” line of FIG. 52A showing the semiconductor device of the fourth embodiment; and FIG. 52C is a cross-sectional view taken along the “Q-R” line of FIG. 52A showing the semiconductor device of the fourth embodiment.

[0080] FIG. 53A is an equivalent circuit diagram corresponding to the cross section of FIG. 52B relevant to the fourth embodiment; FIG. 53B is an equivalent circuit diagram showing simplification of FIG. 53A ; FIG. 53C is an equivalent circuit diagram corresponding to the cross section of FIG. 52C relevant to the third embodiment; and FIG. 53D is an equivalent circuit diagram showing simplification of FIG. 53C .

[0081] FIG. 54A is a cross-sectional view showing one step of a method of fabricating the semiconductor device according to the fourth embodiment, corresponding to a cross section taken along the “Q-R” line of FIG. 52A ; and FIG. 54B is a cross-sectional view showing one step of a method of fabricating the semiconductor device according to the fourth embodiment, corresponding to a cross section taken along the “O-P” line of FIG. 52A .

[0082] FIG. 55A is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the fourth embodiment, corresponding to the cross section taken along the “Q-R” line of FIG. 52A ; and FIG. 55B is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the fourth embodiment, corresponding to the cross section taken along the “O-P” line of FIG. 52A .

[0083] FIG. 56A is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the fourth embodiment, corresponding to the cross section taken along the “Q-R” line of FIG. 52A ; and FIG. 56B is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the fourth embodiment, corresponding to the cross section taken along the “O-P” line of FIG. 52A .

[0084] FIG. 57A is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the fourth embodiment, corresponding to the cross section taken along the “Q-R” line of FIG. 52A ; and FIG. 57B is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the fourth embodiment, corresponding to the cross section taken along the “O-P” line of FIG. 52A .

[0085] FIG. 58A is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the fourth embodiment, corresponding to the cross section taken along the “Q-R” line of FIG. 52A ; and FIG. 58B is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the fourth embodiment, corresponding to the cross section taken along the “O-P” line of FIG. 52A .

[0086] FIG. 59A is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the fourth embodiment, corresponding to the cross section taken along the “Q-R” line of FIG. 52A ; and FIG. 59B is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the fourth embodiment, corresponding to the cross section taken along the “O-P” line of FIG. 52A .

[0087] FIG. 60A is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the fourth embodiment, corresponding to the cross section taken along the “Q-R” line of FIG. 52A ; and FIG. 60B is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the fourth embodiment, corresponding to the cross section taken along the “O-P” line of FIG. 52A .

[0088] FIG. 61A is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the fourth embodiment, corresponding to the cross section taken along the “Q-R” line of FIG. 52A ; and FIG. 61B is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the fourth embodiment, corresponding to the cross section taken along the “O-P” line of FIG. 52A .

[0089] FIG. 62A is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the fourth embodiment, corresponding to the cross section taken along the “Q-R” line of FIG. 52A ; and FIG. 62B is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the fourth embodiment, corresponding to the cross section taken along the “O-P” line of FIG. 52A .

[0090] FIG. 63 is a cross-sectional view showing a semiconductor device according to a modified example of the fourth embodiment, corresponding to a part of the cross section taken along the “Q-R” line of FIG. 52A .

[0091] FIG. 64A is a top plan view of a semiconductor device of a fifth embodiment; FIG. 64B is a cross-sectional view taken along the “S-T” line of FIG. 64A showing the semiconductor device of the fifth embodiment; and FIG. 64C is a cross-sectional view taken along the “U-V” line of FIG. 64A showing the semiconductor device of the fifth embodiment.

[0092] FIG. 65A is an equivalent circuit diagram corresponding to the cross section of FIG. 64B relevant to the semiconductor device of the fifth embodiment; FIG. 64B is an equivalent circuit diagram corresponding to the cross section of FIG. 64C relevant to the semiconductor device of the fifth embodiment; and FIG. 65C is a graph showing characteristics between drain currents and gate voltage of the semiconductor device of the fifth embodiment.

[0093] FIG. 66 is an enlarged cross-sectional view of a part of FIG. 64C which is the cross-sectional view of the semiconductor device according to the fifth embodiment.

[0094] FIG. 67 is an enlarged cross-sectional view of a part of FIG. 64B which is the cross-sectional view of the semiconductor device according to the fifth embodiment.

[0095] FIG. 68A is a cross-sectional view showing one step of a method of fabricating the semiconductor device according to the fifth embodiment, corresponding to a cross section taken along the “S-T” line of FIG. 64 A, and FIG. 68B is a cross-sectional view showing one step of a method of fabricating the semiconductor device according to the fifth embodiment, corresponding to a cross section taken along the “U-V” line of FIG. 64A .

[0096] FIG. 69A is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the fifth embodiment, corresponding to the cross section taken along the “S-T” line of FIG. 64A ; and FIG. 69B is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the fifth embodiment, corresponding to the cross section taken along the “U-V” line of FIG. 64A .

[0097] FIG. 70A is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the fifth embodiment, corresponding to the cross section taken along the “S-T” line of FIG. 64A ; and FIG. 70B is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the fifth embodiment, corresponding to the cross section taken along the “U-V” line of FIG. 64A .

[0098] FIG. 71A is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the fifth embodiment, corresponding to the cross section taken along the “S-T” line of FIG. 64A ; and FIG. 71B is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the fifth embodiment, corresponding to the cross section taken along the “U-V” line of FIG. 64A .

[0099] FIG. 72A is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the fifth embodiment, corresponding to the cross section taken along the “S-T” line of FIG. 64A ; and FIG. 72B is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the fifth embodiment, corresponding to the cross section taken along the “U-V” line of FIG. 64A .

[0100] FIG. 73A is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the fifth embodiment, corresponding to the cross section taken along the “S-T” line of FIG. 64A ; and FIG. 73B is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the fifth embodiment, corresponding to the cross section taken along the “U-V” line of FIG. 64A .

[0101] FIG. 74A is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the fifth embodiment, corresponding to the cross section taken along the “S-T” line of FIG. 64A ; and FIG. 74B is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the fifth embodiment, corresponding to the cross section taken along the “U-V” line of FIG. 64A .

[0102] FIG. 75A is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the fifth embodiment, corresponding to the cross section taken along the “S-T” line of FIG. 64A ; and FIG. 75B is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the fifth embodiment, corresponding to the cross section taken along the “U-V” line of FIG. 64A .

[0103] FIG. 76A is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the fifth embodiment, corresponding to the cross section taken along the “S-T” line of FIG. 64A ; and FIG. 76B is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the fifth embodiment, corresponding to the cross section taken along the “U-V” line of FIG. 64A .

[0104] FIG. 77A is a top plan view of a semiconductor device of a sixth embodiment; FIG. 77B is a cross-sectional view taken along the “W-X” line of FIG. 77A showing the semiconductor device of the sixth embodiment; and FIG. 77C is a cross-sectional view taken along the “Y-Z” line of FIG. 77A showing the semiconductor device of the sixth embodiment.

[0105] FIG. 78A is an equivalent circuit diagram corresponding to the cross section of FIG. 77B relevant to the semiconductor device of the sixth embodiment; FIG. 78B is an equivalent circuit diagram corresponding to the cross section of FIG. 77C relevant to the semiconductor device of the sixth embodiment; and FIG. 78C is a graph showing characteristics between drain currents and gate voltage of the semiconductor device of the sixth embodiment.

[0106] FIG. 79 is an enlarged cross-sectional view of a part of FIG. 78C which is the cross-sectional view of the semiconductor device according to the sixth embodiment.

[0107] FIG. 80A is a cross-sectional view showing one step of a method of fabricating the semiconductor device according to the sixth embodiment, corresponding to a cross section taken along the “Y-Z” line of FIG. 77A ; and FIG. 80B is a cross-sectional view showing one step of a method of fabricating the semiconductor device according to the sixth embodiment, corresponding to a cross section taken along the “W-X” line of FIG. 77A .

[0108] FIG. 81A is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the sixth embodiment, corresponding to the cross section taken along the “Y-Z” line of FIG. 77A ; and FIG. 81B is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the sixth embodiment, corresponding to the cross section taken along the “W-X” line of FIG. 77A .

[0109] FIG. 82A is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the sixth embodiment, corresponding to the cross section taken along the “Y-Z” line of FIG. 77A ; and FIG. 82B is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the sixth embodiment, corresponding to the cross section taken along the “W-X” line of FIG. 77A .

[0110] FIG. 83A is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the sixth embodiment, corresponding to the cross section taken along the “Y-Z” line of FIG. 77A ; and FIG. 83B is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the sixth embodiment, corresponding to the cross section taken along the “W-X” line of FIG. 77A .

[0111] FIG. 84A is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the sixth embodiment, corresponding to the cross section taken along the “Y-Z” line of FIG. 77A ; and FIG. 84B is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the sixth embodiment, corresponding to the cross section taken along the “W-X” line of FIG. 77A .

[0112] FIG. 85A is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the sixth embodiment, corresponding to the cross section taken along the “Y-Z” line of FIG. 77A ; and FIG. 85B is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the sixth embodiment, corresponding to the cross section taken along the “W-X” line of FIG. 77A .

[0113] FIG. 86A is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the sixth embodiment, corresponding to the cross section taken along the “Y-Z” line of FIG. 77A ; and FIG. 86B is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the sixth embodiment, corresponding to the cross section taken along the “W-X” line of FIG. 77A .

[0114] FIG. 87A is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the sixth embodiment, corresponding to the cross section taken along the “Y-Z” line of FIG. 77A ; and FIG. 87B is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the sixth embodiment, corresponding to the cross section taken along the “W-X” line of FIG. 77A .

[0115] FIG. 88A is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the sixth embodiment, corresponding to the cross section taken along the “Y-Z” line of FIG. 77A ; and FIG. 88B is a cross-sectional view showing one step of the method of fabricating the semiconductor device according to the sixth embodiment, corresponding to the cross section taken along the “W-X” line of FIG. 77A .

[0116] FIG. 89 is a cross-sectional view showing a semiconductor device according to a modified example of the sixth embodiment, corresponding to a part of a cross section taken along the “Y-Z” line of FIG. 77A .

[0117] FIG. 90A is a circuit diagram showing one memory cell in a semiconductor device of a seventh embodiment, and FIG. 90 B is a top plan view showing a structure of the memory cell in the semiconductor device of the seventh embodiment.

[0118] FIG. 91A is a cross-sectional view of the semiconductor device of the seventh embodiment, corresponding to a cross section taken along the “III-IV” line of FIG. 90B ; and FIG. 91B is a cross-sectional view of the semiconductor device of the seventh embodiment, corresponding to a cross section taken along the “I-II” line of FIG. 90B .

[0119] FIG. 92 is a circuit diagram showing a reading mode of one memory cell in the semiconductor device of the seventh embodiment.

[0120] FIG. 93A is a circuit diagram showing a read operation mode of one memory cell in an AND-type EEPROM which is a modified example of the seventh embodiment, and FIG. 93B is a circuit diagram showing a read operation mode of a memory cell in a NOR-type EEPROM which is another modified example of the seventh embodiment.

[0121] FIG. 94 is a cross-sectional view of a conventional MONOS (metal-silicon oxide film-silicon nitride film-silicon oxide film-semiconductor) memory cell using shallow trench isolation formed by a selective thermal oxidation method.

DETAILED DESCRIPTION OF THE INVENTION

[0122] Now, embodiments of the present invention will be described with reference to the accompanying drawings. Concerning the description in the drawings, identical or similar parts are denoted by identical or similar marks. Nevertheless, it should be noted that the drawings are schematic; accordingly, relations between thicknesses and plane dimensions, ratios of thicknesses of respective layers or the like are different from reality. Therefore, the concrete thicknesses or the dimensions should be judged with reference to the description hereunder. It should be further noted that the drawings also include portions that are different in the relations of dimensions or the ratios from one another.

First Embodiment

[0123] A prototype in the case of forming a MONOS cell of a floating-gate flash memory by a self-aligned shallow trench isolation (hereinafter referred to as “SA-STI”) process is illustrated in FIG. 2 .

[0124] Here, a plurality of shallow trench isolation regions 2 are formed on a semiconductor substrate 1 . A tunnel insulating film 3 made of a silicon oxide film is formed in the vicinity of a surface of the semiconductor substrate between two adjacent shallow trench isolation regions 2 . A charge storing layer 4 made of a silicon nitride film is formed on the tunnel insulating film 3 . A block insulating film 5 made of a silicon oxide film is formed on the charge storing layer 4 . This block insulating film 5 is integrated with the shallow trench isolation regions 2 of the same material. A gate electrode 6 is formed on the block insulating film 5 and the shallow trench isolation regions 2 .

[0125] In this case, a portion of the gate electrode 6 sandwiched by the shallow trench isolation regions 2 is first formed, then after formation of the shallow trench isolation regions 2 , the gate electrode 6 is additionally formed on the shallow trench isolation regions 2 . That is, although the gate electrode seems one item, the gate electrode is formed by different steps depending on location thereof. Accordingly, a gate insulating film includes a natural oxide film.

[0126] Adoption of such a structure can improve a sidewalk phenomenon in comparison with a MONOS using LOCOS isolation. Moreover, since the charge storing layer 4 is not formed on the shallow trench isolation regions 2 , data loss that has been conventionally caused owing to movement of electric charges to an adjacent cell via the charge storing layer 4 on the element isolation regions can be prevented.

[0127] In the case of using the SA-STI as described above, there is almost no thickening of gate edges (edges of the gate electrode 6 sandwiched by the shallow trench isolation regions 2 ) of the tunnel insulating film 3 . However, when a surface of the semiconductor is subjected to oxidation for recovery from defects after formation of the trenches, a bird's beak appears on polycrystalline silicon that constitutes the gate electrode 6 , whereby the block insulating film 5 is thickened at edges of the shallow trench isolation regions and a bird's beak 7 is resultantly caused. Specifically, an enlarged view of a contacting portion of the shallow trench isolation region 2 with the gate electrode 6 is illustrated in FIG. 3 .

[0128] In addition, as the polycrystalline silicon constituting the gate electrode 6 recedes due to oxidation, a protrusion 8 of the shallow trench isolation region 2 is formed. As described above, the charge storing layer protrudes out from the gate electrode 6 extending over the width of the gate electrode 6 sandwiched by the shallow trench isolation regions 2 , whereby the charge storing layer has a greater length according to the cross section in FIG. 2 and a protrusion 9 is formed as shown therein.

[0129] Here, since electric fields adequate for writing/erasing are not applied to the protrusion 9 in FIG. 2 from the gate electrode 6 upon application of voltage to the gate electrode 6 , a threshold in such a region 9 can not be controlled.

[0130] Specifically, subthreshold characteristics in a writing mode of a cell of a semiconductor memory device are illustrated in FIG. 4 . A reference numeral [ 1 ] denotes the characteristic at a central portion of a channel thereof, and the characteristic at a channel edge (an interface with the element isolation region) as denoted by a reference numeral [ 2 ] has a feature that a threshold for writing is lower than that of the central portion. This is attributable to a decrease in a current for writing caused by abatement of electric fields for writing owing to thickening of the gate insulating film at the edges. The subthreshold characteristics of the cell as a whole become one having a hump in a low-voltage portion thereof, as denoted by a reference numeral [ 3 ] in FIG. 5 .

[0131] Subthreshold characteristics in both the writing operation mode and an erase operation mode are plotted in FIG. 6 . The characteristic in the write operation mode is denoted by a reference numeral [ 4 ] and the characteristic in the erase operation mode is denoted by a reference numeral [ 5 ]. Since a threshold at the channel edge is