DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] In FIG. 1 , the reference 1 denotes a semiconductor substrate, for example, made of silicon and comprising a substrate region ZA bounded laterally by a lateral isolation region STI of the shallow trench type. The production of a such lateral isolation region STI is in itself completely known by those skilled in the art and will not be described here in detail.

[0016] Starting from the structure illustrated in FIG. 1, a multilayer comprising a first layer 2 is formed from a silicon-germanium alloy, and is surmounted by a second layer 3 formed from silicon, as illustrated in FIG. 2 a. These layers are formed by selective epitaxy, known by those skilled in the art. That is, the silicon-germanium grows only on the substrate region ZA and does not grow on the lateral isolation region STI. Likewise, the silicon layer 3 grows only on the silicon-germanium layer 2 .

[0017] The respective thicknesses of the layer 2 and the layer 3 are on the order of 20 nm. In fact, the material forming the layer 2 is more generally a material that can be removed selectively with respect to silicon, and which preferably ensures that there is lattice continuity with the silicon during the epitaxy. Thus, an Si _1-x Ge _x alloy (where 0<×≦1) may be chosen, for example. Si _1-x Ge _x alloys are recommended as they can be easily removed selectively, either by a well-known oxidizing chemistry (such as a solution containing 40 ml of 70% HNO ₃ +20 ml H ₂ O ₂ +5 ml of 0.5% HF) or by isotropic plasma etching.

[0018] Preferably, Si _1-x Ge _x alloys having a high germanium content will be used since the selectivity of the etching with respect to silicon increases with an increase in the germanium content in the alloy. It is also possible to use Si _1-x-y Ge _x C _y alloys (where 0<x≦0.95; 0<y≦0.05) which behave like Si _1-x Ge _x alloys with regard to selective removal but induce less stress with the silicon layers.

[0019] Next, an insulating layer 4 made, for example, from silicon dioxide is then formed by oxidation. This layer 4 covers the silicon layer 3 and will be used to form subsequently the gate oxide layer of the transistor. Next, the gate 5 of the transistor is produced conventionally by depositing a gate material, for example, polysilicon, and then by etching this material so as to form the gate. In this regard, as illustrated in FIG. 2 b, which shows a plan view of the device of FIG. 2 a, it may be seen that the gate 5 forms a bridge transversely straddling the substrate region ZA and bearing on the two sides of this region ZA on the lateral isolation region STI.

[0020] The next step ( FIG. 3 ) comprises selectively etching the first layer 2 of the multilayer. This selective etching is illustrated by the arrows GS in FIG. 3 . This selective etching may be carried out as indicated above by an oxidizing chemistry or else by an isotropic plasma etching, and will result in the complete removal of the layer 2 of the multilayer so as to form a tunnel 20 beneath the layer 3 . This layer 3 is mechanically held by the gate 5 , which rests, as indicated above, on the lateral isolation region STI.

[0021] It should be noted here that the selective etching GS of the silicon-germanium layer is preferably preceded by local deoxidation at the lateral isolation region STI, so as to be able to access the silicon-germanium layer 2 more easily. This is not detrimenal to the quality of the lateral isolation, since this lateral isolation is not critical because the transistor is insulated with respect to the substrate ZA. This local deoxidation results, in the method of implementation described here, in deoxidation of the structure resulting in shrinkage of the layer 4 on each side of the gate 5 .

[0022] The etching of the tunnel 20 is followed by an oxidation so as to fill this tunnel with an insulating material 21 ( FIG. 4 ), for example, with silicon dioxide. This oxidation also leads to the layer 4 being reformed. The insulating material 21 will ensure isolation of the conduction channel of the transistor which will be formed in the silicon layer 3 .

[0023] As illustrated in FIG. 5 , the transistor T will then be completed in the conventional manner by a first implementation of dopants so as to form the source and drain extension regions. This first dopant implantation is followed by the formation of isolating spacers 6 flanking the edges of the gate 5 . A second implantation of higher dose will then be carried out on each side of the spacers, so as to form the source S and drain D regions. The subsequent steps include, in particular, of producing the metal contact areas on the source, drain and gate regions of the transistor.

[0024] The transistor T according to the invention has a conduction channel 30 isolated from the gate 5 by a gate oxide layer 40 . This conduction channel itself is isolated from the substrate 1 by a layer 21 made of an insulating material. Moreover, the source S and drain D regions are also completely isolated vertically from the substrate by the insulating layer 21 . Finally, the transistor T is isolated laterally from other transistors formed on the same integrated circuit by lateral isolation regions STI of the shallow trench type.

[0025] The invention is not limited to the methods of implementation and embodiments that have just been described, but embraces all the variations thereof. Thus, although it is preferable to carry out the implantations of the source and drain extension regions and the source and drain implantations after the step of etching the tunnel, so as to again obtain better silicon-germanium etching selectivity with respect to silicon, it would also be conceivable to produce the transistor entirely before etching the first layer of the multilayer 2 so as to form the tunnel 20 .