DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0016] Please refer to FIG. 2 . FIG. 2 is a cross-sectional diagram of a trenched flash memory cell 30 formed on a silicon substrate 32 according to the present invention. As shown in FIG. 2 , the silicon substrate 32 is a silicon-on-insulator (SOI) substrate or a single crystal silicon substrate, over which a memory array area and a periphery circuits region are predetermined. At least a P-well 34 and a N-well (not shown) are formed within the silicon substrate 32 in the memory array area.

[0017] In a better embodiment of the present invention, the trenched flash memory cell 30 comprises two stacked gates 42 buried in the P-well 34 within the silicon substrate 32 , a common source 36 positioned on the surface of the silicon substrate 32 between the two stacked gates 42 , two drains 38 positioned on the silicon substrate 32 at an opposing side of each stacked gate 42 , and a dielectric layer 40 positioned on the surfaces of the common source 36 and the drains 38 to isolate the stacked gate 42 from the common source 36 and the drains 38 . The stacked gate 42 is composed of a tunnel oxide layer 44 , a floating gate 46 , an ONO dielectric layer 48 , and a controlling gate 50 stacked, respectively, and partially buried in the silicon substrate 32 . In addition, a spacer 52 is formed on either side of each stacked gate 42 . A silicide layer 54 is also formed on the surfaces of the stacked gates 42 and the common source 36 to reduce resistance.

[0018] Please refer to FIG. 3 . FIG. 3 is a top view of the trenched flash memory cell 30 shown in FIG. 2 . As illustrated in FIG. 3, a plurality of shallow trench isolation structures 56 are formed to produce two active areas 58 within the silicon substrate 32 . The active areas 58 , comprising a plurality of trenches 61 buried in the silicon substrate 32 , are perpendicular to a plurality of parallel word lines 60 . Furthermore, a bit line 62 is positioned between two word lines 60 .

[0019] Please refer to FIG. 4 to FIG. 11 . FIG. 4 to FIG. 11 are schematic diagrams of a method of fabricating the trenched flash memory cell 30 on the silicon substrate 32 according to the present invention. As shown in FIG. 4 , which is a sectional view along line AA′ of FIG. 3 , the present invention method first involves the use of a shallow trench isolation process. During this process, conventional photolithographic and etching methods are used to form a plurality of shallow trench isolation structures 56 in the silicon substrate 32 . An active area 58 , enclosed by the shallow trench isolation structures 56 , is then defined on the surface of the silicon substrate 32 . Thereafter, a chemical vapor deposition (CVD) process is performed to form an oxide layer 64 to fill each of the shallow trench isolation structures 56 . A photoresist layer (not shown) is formed to cover both the periphery circuits region and the N-well portion in the memory array area, followed by a first ion implantation process to form a buried N ⁺ doped region 35 on the surface of the P-well 34 within the active area 58 . An isolation layer 40 is then formed on the surface of the silicon substrate 32 . The isolation layer 40 may be a silicon dioxide layer formed by a plasma-enhanced chemical vapor deposition (PECVD) method.

[0020] As shown in FIG. 5 , which is a sectional view along line BB′ of FIG. 3, a photoresist layer 66 is subsequently formed on the surface of the isolation layer 40 and patterned by a photolithographic process to predetermine the position of two trenches 61 . As shown in FIG. 6 , an etching process is performed using the photoresist layer 66 as a mask to both remove the isolation layer 40 to a predetermined depth within the P-well 34 and to form two trenches 61 within the P-well 34 . The two trenches 61 divide the doped region 35 into a common source 36 positioned between the two trenches 61 , and two drains 38 positioned an opposing side of each trench 61 . A thermal oxidation process is then performed to grow a silicon dioxide layer on the inner surface of the trenches 61 so as to function as a tunnel oxide layer 44 .

[0021] Next, as shown in FIG. 7, a CVD process is used to deposit a doped polysilicon layer (not shown) on the surface of the silicon substrate 32 . To avoid completely filling the trenches 61 , the thickness of deposition of the doped polysilicon layer is controlled to be approximately half to three quarters of the radius of the trench 61 . Thereafter, the doped polysilicon layer is removed except in the region within the trenches 61 so as to form a floating gate 46 in the trenches 61 .

[0022] As shown in FIG. 8 , an oxide-nitride-oxide (ONO) process is performed so as to form an ONO dielectric layer 48 on the silicon substrate 32 in the memory array area. A CVD process is then used to deposit another doped polysilicon layer 49 on the entire surface of the silicon substrate 32 , including the silicon substrate 32 in the periphery circuits region. The doped polysilicon layer 49 fills in the trenches 61 . Thereafter, a photo and etching process (PEP) is performed to etch a portion of the doped polysilicon layer 49 as well as to form two controlling gates 50 above each of the two trenches 61 , as shown in FIG. 9 . In other words, two word lines 60 as shown in FIG. 3 are formed crossing the active areas 58 . As well, the PEP simultaneously forms a plurality of gates (not shown) in the periphery circuits region. Thereafter, a photoresist layer 68 is formed on the surface of the silicon substrate 32 , followed by a photolithographic process to form an opening in the photoresist layer 68 to expose the isolation layer 40 in the region between the two controlling gates 50 .

[0023] Next, as shown in FIG. 10, a self-alignment source (SAS) etching process is performed using the patterned photoresist layer 68 as a mask to remove the isolation layer 40 positioned between the two controlling gates 50 down to the surface of the common source 36 . The method of removing the isolation layer 40 involves using a fluorocarbon plasma to selectively etch between silicon dioxide (the isolation layer 40 ) and doped polysilicon (the common source 36 ). And if necessary, a portion of the common source 36 is over etched to ensure the complete removal of the isolation layer 40 between the two controlling gates 50 . In addition, the silicon dioxide filled in the shallow trench isolation structures 56 adjacent to the common sources 36 , as shown in FIG. 3 , is also selectively removed down to the surface of the silicon substrate 32 during this process.

[0024] Thereafter, the photoresist layer 68 is again used as a mask to perform a second ion implantation process, using the N-type dopants such as arsenic atoms to heavily implant the common source 36 , to finish fabrication of the stacked gate 42 . The photoresist layer 68 is then removed, followed by the deposition of a silicon nitride layer (not shown). Next, an anisotropic etching process is performed to etch back a portion of the silicon nitride layer so as to form a spacer 52 , using the remaining silicon nitride layer, on either vertical sidewall of each stacked gate 42 .

[0025] At last, as shown in FIG. 1, a titanium (Ti), cobalt (Co), nickel (Ni) or tungsten (W) metal layer (not shown) is formed on the surface of the silicon substrate 32 . A thermal processing is then used to induce a reaction between the metal layer and the silicon in the common source 36 , so that a self-alignment silicide (salicide) layer 54 is formed to function in reducing sheet resistance. Simultaneously, the salicide layer 54 is also formed on the silicon substrate 32 between the common sources 36 , connecting with the salicide layer 54 positioned atop each of the common sources 36 to form the bit line 62 , as shown in FIG. 3 , to complete the fabrication of the trenched flash memory cell 30 of the present invention.

[0026] The present invention method uses the PEP of forming the trenches 61 to simultaneously form a self-alignment source 36 between the two trenches 61 . Furthermore, the active areas 58 not occupied by the stacked gate 42 and the common source 36 automatically form the drains 38 . As a result, subsequent photolithographic processes are unnecessary to define the drain 38 and source 36 . As well, the source 36 and drain 38 of the trenched flash memory cell 30 horizontally surround the floating gate 46 such that the channel length between the floating gate 46 and the source 36 /drain 38 is increased. As a result, the Fowler Nordheim tunneling technique facilitates both data storage and removal during operation of the trenched flash memory cell 30 by injecting electrons into the floating gate 46 or neutralizing the electrons in the floating gate 46 . For example, when the controlling gate 50 is applied a high voltage, the drain 38 is negatively biased and the source 36 is floated, electrons are emitted from the drain 38 into the floating gate 46 to be stored. Conversely, when the controlling gate 50 is grounded or negatively biased, the source 36 is applied a high voltage and the drain 38 is floated, electrons stored in the floating gate 46 are ejected.

[0027] In contrast to the prior art of fabricating the flash memory cell, the method of the present invention uses a trench structure buried in the silicon substrate to form the stacked gate. Hence, the coupling surface area between the floating gate and the controlling gate is increased via the increase in depth or width of the stacked gate buried in the silicon substrate. Most importantly, integration of the elements subsequently formed on the substrate is not affected and the accessing speed of the flash memory cell is increased. In addition, the present invention uses a self-aligned technique to form the common source and the drains, and thus, prevents damage resulting from the conventional source/drain process. Also, the present invention forms the salicide layer on the surface of both the gate and the source to reduce resistance to improve the electrical performance and the quality of the flash memory cell.

[0028] Those skilled in the art will readily observe that numerous modifications and alterations of the device may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.