DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0067] Embodiment 1

[0068] A brief structure of the present invention is as shown in FIG. 10 , however, in accordance with the present embodiment, in an MRAM constituted by a selective transistor and a TMR device, there is shown a structure relating to a method of manufacturing a semiconductor memory apparatus in which a writing word line is formed below a data line. A transistor employs a normal transistor formed on a Si substrate surface. A description will be in detail given below of the structure while following to the manufacturing process.

[0069] At first, a p-type semiconductor substrate 901 is prepared, and an area separating between devices 1501 for separating MOSFET is formed by using a known selective oxidation method and a shallow grooved isolation. FIG. 13 shows a plan layout of a device separation area of a memory array portion. In the present embodiment, there is employed the shallow grooved isolation capable of flattening a surface. Accordingly, at first, a separation groove having a depth of about 0.3 micron is formed on the substrate by using a known dry etching method, damages on groove side walls or a bottom surface caused by the dry etching are removed, thereafter Si oxide films are accumulated with a thickness of about 0.7 micron by using a known chemical vapor deposition (CVD) method, the oxide films existing in the other portion than the groove are selectively polished in accordance with a known chemical mechanical polishing (CMP) method, and the oxide films buried in the groove are left. Next, two different conductive wells are formed by a high energy ion implantation. Next, after cleaning the surface of the semiconductor substrate, a gate oxide film 9 is grown in accordance with a thermal oxidation method. A polycrystal line silicon containing phosphorous of high concentration is accumulated on the surface of the oxide film, as a word line 802 and a gate electrode at a thickness of 100 nm. Of course, a polycrystal line silicon containing boron of high concentration in place of phosphorous may be used. In the present embodiment, the polycrystal line silicon is used as an electrode material, however, in order to reduce a gate resistance, it is of course possible to use a laminated film constituted by a metal and a polycrystal line silicon between which a barrier metal for restricting a reaction is provided. Further, a silicide film which does not react with the polycrystal line silicon may be used as this metal. Further, a silicon ticker film 14 is accumulated at 100 nm. Next, in accordance with the dry etching method, the gate electrode is formed in a peripheral circuit area, and the word line 802 is formed in the memory array as shown in FIG. 14 . Further, the gate electrode and a resist are formed as a mask and impurity ions are struck, whereby a diffusion layer is formed.

[0070] Next, in order to apply a self-aligned contact opening process, the silicon ticker films 1401 having a thickness of 50 nm are accumulated. Further, the oxide films 17 having a thickness of about 0.7 micron are accumulated, a flattening in accordance with a known CMP method is executed, the silicon oxide film is etched under a condition having a high selective ratio with respect to the silicon ticker film (the self-aligned contact opening process), and in the memory array, a contact hole is opened as shown in Fig.

[0071] Further, the polycrystal line silicon doping the impurity at a high concentration in accordance with the known CVD method is accumulated, and a conductive plug 1104 is formed by using the known CMP method. Further, tungsten forming a common ground line 1302 is accumulated at 100 nm and is processed so as to extend in parallel to the word line as shown in FIG. 16 . The tungsten forms a metal first wiring layer in the peripheral circuit.

[0072] Next, the oxide film 1701 having a thickness of about 0.7 micron is accumulated in accordance with the conventional CVD method, the flattening in accordance with the known CMP method is executed, the contact is opened and the memory array is made as shown in FIG. 17 . In this case, as is apparent from FIG. 17 , it is not necessary to use the self-aligned contact opening process, and it is easy in view of the process. Next, the polycrystal line silicon plug 1105 is formed in accordance with the known process. Of course, the tungsten may be employed in place of the polycrystal line silicon. Further, a laminated film of NiFe/Al ₂ O ₃ /CoFe forming the TMR device 502 is accumulated, is processed to a desired shape and is formed as shown in FIG. 18 . Next, after a film between the layers 1702 is accumulated and is flattened in accordance with the CMP method, the tungsten forming the bit line 602 is accumulated at 100 nm and is processed. A state at this time is shown in FIG. 19 .

[0073] Next, an insulating film between the layers 1703 is accumulated, and the tungsten forming the writing word line 702 is accumulated at 100 nm and is processed. This state is shown in FIG. 11 . Since the writing word line 702 is formed in a top layer, no restriction exists with respect to a layout, and as shown in FIG. 12 , it is possible to arrange so as to completely cover the TMR device 502 two-dimensionally. This is a great characteristic in a point of view of a reliability of a memory operation. Finally, two layers of metal wires are formed so as to obtain a desired semiconductor memory apparatus.

[0074] Embodiment 2

[0075] The present embodiment corresponds to a structure of making the writing transistor in the memory cell of the MRAM in a vertical type. As a great characteristic of the present embodiment, there can be listed up that it is possible to make the cell area 4 F 2 corresponding to about half of the normal DRAM.

[0076] The structure realized by the present embodiment is as shown in FIG. 20 . That is, the diffusion layer 1003 of the vertical selective transistor 401 is connected to the TMR device 504 , and the TMR device 504 is connected to the bit line 603 . The writing word line 704 is formed thereabove. A description will be in detail given below while following the manufacturing process.

[0077] At first, the transistor in the peripheral circuit is formed in accordance with the normal manufacturing process. The contact plug is formed after accumulating the insulating film between the layers 1704 , and a first metal wiring layer constituted by the tungsten is formed. In the memory array, the wiring layer is used as the common ground line 1303 . FIG. 21 shows a state at this time. Next, the insulating film between the layers is accumulated, the polycrystal line silicon plug containing the impurity at a high concentration is formed and the structure is formed as shown in FIG. 22 .

[0078] Next, the vertical transistor and the TMR portion are formed. In this case, the films are accumulated in the following order. At first, N+ layer ( 1004 ) doping the impurity forming the diffusion layer of the vertical transistor at a high concentration, a low concentration impurity layer ( 19 ) forming a channel portion and N+ layer ( 1005 ) forming the diffusion layer are accumulated. These form the transistor portion. Of course, at this time, the polycrystal line silicon mentioned above can be made a single crystal by using a method such as a laser anneal or the like. In this case, it goes without saying that a performance of the transistor is improved. Further, NiFe, Al ₂ O ₃ and CoFe are accumulated in this order as the films constituting the TMR device 505 . Further, as a stopper mask of the CMP, a plasma SiN 1402 is accumulated at 100 nm. Since the plasma SiN is used, there is an advantage that it is possible to reduce a thermal load applied to the TMR device. The laminated layer is processed in a simple line and space shape as shown in FIG. 23 . Sequentially, the insulating film between the layers 1706 is accumulated, the flattening is executed by the CMP, and CoFe forming the TMR is exposed. A state at this time is shown in FIG. 24 .

[0079] Next, the tungsten having a film thickness of 100 nm and forming the bit line 604 and the plasma oxide film 20 are accumulated. Sequentially, as shown in FIG. 25 , it is processed in the line and space shape which is previously formed and extends in a direction vertical to the common line. In accordance with this process, the bit line 604 and the TMR device 505 are electrically connected. In this case, in accordance with the present embodiment, for the purpose of reducing a capacity between the bit lines, a width of the bit line is made narrow. In particular, an ashing process is applied after exposing a bit line resist pattern.

[0080] Next, the word line of the selective transistor is formed. At first, for the purpose of preventing the word line and the bit line 604 from being electrically shorted, as shown in FIG. 26, a side wall oxide film 21 is formed in the bit line 604 . Further, the bit line 604 covered by the oxide film is formed as the mask and the ground laminated film is etched in a self-aligned manner, whereby the structure shown in FIG. 27 is obtained.

[0081] Sequentially, the gate oxide film having a film thickness of 10 nm is formed, the tungsten forming the word line is further accumulated and flattened and the structure shown in FIG. 28 is obtained. In the present embodiment, the tungsten is used, however, it is of course possible to use a laminated film constituted by the tungsten and the polycrystal line silicon between which the barrier metal is held, the polycide or the like. Next, the tungsten is processed in the line and space shape extending in the direction vertical to the bit line in accordance with the normal dry etching method. The state at this time is shown in FIG. 29 . As an effect of flattening the electrode material at a time of processing the word line 804 , an etching step becomes only a height of the bit line. In FIG. 29 , it corresponds to a step adding the height of the bit line 604 to the height of the cap oxide film 20 . In this case, in accordance with the present embodiment, the word line 804 of the selective transistor can be used as the writing word line. At this time, at a time of writing the data, the structure is made such that no surplus electric current flows, by applying an electric potential difference equal to or less than a threshold electric voltage of the selective transistor to both ends of the word line.

[0082] Finally, a necessary metal wire layer is formed and a desired semiconductor apparatus is obtained. In the present embodiment, a semiconductor memory apparatus having a minimum cell area can be realized by using the vertical transistor. Further, a simplification of the process and a reduction of the cost can be achieved by making the gate electrode of the selective transistor and the writing word line common.

[0083] In the present embodiment, the writing word line and the readout word line are made common, however, can be of course independent from each other. In this case, from the state shown in FIG. 29 , the desired writing word line may be formed by using the normal process after accumulating the insulating film between the layers.

[0084] Embodiment 3

[0085] The present embodiment relates to an MRAM having a vertical selective transistor in the same manner as that of the embodiment 2 . A great difference from the embodiment 2 is a thermal load applied to the TMR device. That is, in the embodiment 2 , the gate oxidation is executed after forming the TMR device, however, in the present embodiment 3 , the TMR device is formed after forming the gate oxide film. As a result, in accordance with the present embodiment, it is possible to reduce the thermal load applied to the TMR device so as to prevent the characteristic thereof from being deteriorated. Since a heat resistance of the TMR device is about 400° C., this is a great characteristic of the present embodiment. A description will be in detail given below of the present embodiment while following the manufacturing process.

[0086] In the present embodiment, the first metal wire layer in the peripheral circuit is used as the word line 805 of the selective transistor in the memory array. A state in the memory array at this time will be shown in FIG. 30 . In this case, in FIG. 30 , the transistor and the like formed within the substrate are not described. Sequentially, for the purpose of preventing the common ground line and the word line 805 which are formed later from being electrically shorted, the insulating film between the layers 1708 is accumulated at 50 nm. Next, the tungsten 23 forming the common ground line is accumulated at 50 nm. Further, the N+ layer 24 containing the impurity at a high concentration, the low concentration layer 2401 forming the channel and the N+ layer 2402 containing the impurity at a high concentration which form the vertical transistor, are accumulated in this order. Of course, at this time, the polycrystal line silicon mentioned above can be made a single crystal by using the method such as the laser anneal or the like. In this case, it goes without saying that the performance of the transistor is improved. The tungsten 2301 forming the plug for connecting the diffusion layer of the selective transistor and the TMR device later is accumulated thereon. The state at this time is shown in FIG. 31 . Next, the laminated film is processed in the line and space shape extending in the direction vertical to the previously formed word electrode 805 , and the structure shown in FIG. 32 is obtained.

[0087] Next, the gate insulating film 1601 is accumulated at 10 nm. In the present embodiment, the CVD method is used, however, the thermal oxidation film may be used. The state at this time is shown in FIG. 33 . Next, the polycrystal line silicon forming the gate electrode and containing the impurity at a high concentration is accumulated, a side wall film 2403 is formed in accordance with a normal etchback process, further the ground gate insulating film is removed and the structure shown in FIG. 34 is obtained. Next, the polycrystal line silicon film 2404 containing the impurity at a high concentration is buried and flattened in accordance with the CMP process, and the ground tungsten 2301 is exposed. The state at this time is shown in FIG. 35 . As a result, the previously formed word line 805 and the side wall polycrystal line silicon film 2403 are electrically connected. Sequentially, the polycrystal line silicon 2404 is etchbacked as shown in FIG. 36 . At this time, in order to prevent an offset of the transistor, it is important that the etchbacked surface does not descend from the boundary between the N+ layer 1007 forming the diffusion layer and the channel portion 1006 . An object of the etchback is to secure a short margin between the word electrode 2404 and the later formed TMR device.

[0088] Next, the oxide film 1709 is accumulated and flattened, the tungsten 2301 is exposed and the structure shown in FIG. 37 is obtained. Sequentially, silicon knight ride 1403 is accumulated at 100 nm, and is processed in a ling and space shape in accordance with the normal dry etching method. The state at this time is shown in FIG. 38 . Further, the silicon knight ride 1403 is formed as the mask, the tungsten 2301 , the oxide film 1709 and the polycrystal line silicon 1007 , 1901 , 1006 and 2404 are dry etched, and the structure shown in FIG. 39 is obtained. Next, the silicon oxide film 1710 is accumulated, and flattened in accordance with the CMP, the silicon knight ride 1403 is simultaneously removed, and the ground tungsten 2301 is exposed. The state at this time is shown in FIG. 40 .

[0089] Next, the TMR device is formed. NiFe 25 , Al ₂ O ₃ 26 and CoFe 27 are accumulated at this order, and the structure shown in FIG. 41 is obtained. The TMR laminated film is processed in accordance with the normal dry etching method. The state at this time is shown in FIG. 42 . Further, the silicon oxide film 1711 is accumulated and flattened, the CoFe 27 constituting the TMR device is exposed, and the structure shown in FIG. 43 is obtained. At this time, if the pitch of the word line 805 formed below is reduced, a freedom of layout is increased and it is possible to intend to reduce the writing electric current as a result of utilizing a shape anisotropy effect of the TMR.

[0090] Next, the bit line 605 is formed. For the purpose thereof, the tungsten 605 is accumulated at 100 nm, and is processed in the line and space shape shown in FIG. 44 . Sequentially, the writing word line is formed. The writing word line 705 is processed after accumulating and flattening the insulating film between the layers 1712 . The state at this time is shown in FIG. 45 . Finally, two layers of metal wire layers are formed in accordance with the normal process, and a desired semiconductor apparatus is obtained.

[0091] Embodiment 4

[0092] The embodiments mentioned above relate to 1 transistor-1 TMR type MRAM. A concept forming the writing word line above the bit line can be of course applied to 1 diode-1 TMR type MRAM employing a diode in place of the transistor. FIG. 46 shows a schematic view of a memory cell in the case mentioned above. At a time of writing the data, a positive bias is applied to the bit line. As a result of this, a PN junction becomes under a reverse bias state, and no electric current flows. On the contrary, at a time of reading out, a negative electric potential is applied to the bit line, and the junction is made under a regular bias state. It is possible to obtain a desired semiconductor memory apparatus a memory cell portion of which is shown in FIG. 47 as a cross sectional view, by using substantially the same manufacturing process as that mentioned in the embodiment 1. Of course, it goes without saying that the PN junction constituted by the polycrystal line silicon can be employed as the diode. In this case, the structure of the memory cell is as shown in FIG. 48 .

[0093] Embodiment 5

[0094] The present embodiment relates to an MRAM having a vertical path transistor for a logic embedded memory devices. In order to give a maximum performance to the peripheral transistor, the structure is made in accordance with the following order. At first, the memory cell transistor is formed. The state at this time is shown in FIG. 49 . Sequentially, a relative insulating film 1712 and 1713 in the peripheral circuit area is removed, the transistor is formed and the structure shown in FIG. 50 is obtained. Further, the TMR 506 is formed, and is flattened by the relative insulating film 1714 . The state at this time is shown in FIG. 51 . Since the heat resistance of the TMR is about 400° C., the TMR device property and the peripheral circuit performance are not deteriorated by forming in the order mentioned above. Next, after forming the conductive plug 1106 in the peripheral circuit area, the metal wire layer is formed, and the structure shown in FIG. 52 is obtained. The wire layer forms the bit line 606 in the memory array area, and forms the first metal wire layer 55 in the peripheral circuit area. Next, the relative insulating film 1715 is accumulated and flattened, and the writing word line 706 is formed. The state at this time is shown in FIG. 53 . Finally, a multi-level metallization is formed and a desired semiconductor memory apparatus is obtained.

[0095] In accordance with the present invention, in the MRAM utilizing the tunnel magnetic resistance, the following two effects can be obtained by forming the writing word line above the bit line. One of them is to simplify the process. Another of them is to improve a reliability of the memory operation, in particular, the writing operation. Further, it is possible to reduce the cell area in comparison with the conventional DRAM by applying the present invention to the MRAM having the vertical transistor.