DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0043] The memory device of the present invention is a multipurpose device that allows for a synchronous or asynchronous access using the same access protocol of a standard memory device, as depicted in FIG. 4 . The start of a conventional (asynchronous) read cycle takes place by inputting an address not consecutive to the previous one. Upon recognizing this condition, the address counters of the memory device acquire the external address and the read cycles of the two memory banks are simultaneously started. A block diagram of a preferred embodiment of the invention is depicted in FIG. 5 , while the main signals are depicted in FIG. 6 .

[0044] In an asynchronous cycle the two independent arrays of sense amplifiers SENSE_EVEN, SENSE_ODD of the two memory banks are enabled at the same time by the pulse UPDATE, but only the sense amplifiers of the memory bank in a state of priority identified by the logic value of the least significant bit A 0 of the address are enabled. This is done for placing the read data on the internal data bus.

[0045] In the phase that immediately follows the start of a read cycle, when it is acknowledged that the address has been acquired in the counters and the carry has propagated, if the first bank in priority is the ODD bank the block CONTROL_LOGIC generates a first increment pulse for the counter EVEN on the relative bank EVEN of which the read cycle pertaining to the next successive address takes place.

[0046] By doing so, reading of the bank having priority evolves freely because this bank will be called first to deliver the data read to the output. At the same time the incremented address for the successive reading on the other bank is prepared. This is the start of a burst interleaved synchronous read process.

[0047] The same increment signal for the bank that is not in priority stimulates the respective circuit SENSE CTRL TIMING managing the sense amplifiers SENSE_EVEN, SENSE_ODD. This is so that the array of sense amplifiers, the managing circuit SENSE CTRL TIMING, the dummy equalization structures, etc., will process the increment pulse as a normal request of an asynchronous reading and will be restarted, while the sense amplifiers of the bank in priority, being independent from those of the other bank, will continue to evolve through the reading phase.

[0048] The control circuit will continue to monitor the signals coming from the block SENSE CTRL TIMING of the bank in priority and, as soon as it generates the signal DLATCH for transferring the read data to the latch in cascade of the sense amplifiers, will produce the pulse LOAD for loading the read data in the output latch. The falling (trailing) edge of the pulse LOAD establishes that the bank that has just terminated the reading is ready to start a new read cycle. A new increment signal will be produced only for the counter of this bank, and besides stimulating the generation of the new internal address, will restart the reading exclusively for this bank.

[0049] Once again the control circuit waits for information coming from the external input bus or from the self-adapting structure of the SENSE CTRL TIMING to enable the outputting of data of the other bank. This is done by the generation of a new pulse LOAD or the start a new asynchronous read cycle. The above described operations may repeat themselves indefinitely, alternating the sequence.

[0050] The signal OEn (Output Enable) is a low-active external command for enabling the output buffers. Thus, if the signal assumes the logic level 0, the data of the bank in priority are transferred to the output buffers and are made available external the memory device.

[0051] The circuit for detecting address transitions TRANSITION_DETECTOR produces a detection pulse ATD_ADD starting from which the pulse signals that allow the comparison between the external address and the address stored in the address counters are generated. The address consecutive to the one of the last completed readings is present in the counter of the bank that is currently not in priority. If the external address is equal to this address, the relative data can be output and a new reading on this bank may start again.

[0052] Each time the external address EXT_ADD is modified, the block TRANSITION_DETECTOR produces a pulse ATD_ADD that is suitably delayed and stretched by the block DELAY&STRETCH. This block produces the signal COMPARE as a delayed and stretched version of the pulse ATD_ADD in order to account for the processing time of the signal NEW_ADDR.

[0053] At the same time the external address is compared with the address stored in counters of both banks. If the address is different from the one contained in both counters, the signal NEW_ADDR that represents the result of the comparison switches to 1. This indicates to the system that an address not consecutive to the previous one has been input and that an asynchronous reading cycle is required. Therefore, if NEW_ADDR=1 and COMPARE=1 then UPDATE is active, thus enabling the storing of the new address in the counters by enabling the pass gates that couple the output of INPUT_BUFFERS to the counters themselves. This also stimulates the blocks SENSE CTRL TIMING that manage the sense amplifiers SENSE_EVEN, SENSE_ODD of the two blocks during the various phases of the read cycle.

[0054] The blocks SENSE CTRL TIMING may be similar to that described in European Patent Application No. EP-00830068.3. That is, they are self-adaptive structures suitable to manage the timing of the read phases of the sense amplifiers. If A 0 =0, the two banks proceed in parallel during the first reading cycle and when the sense amplifiers terminate their evaluation phase, the read data are latched in their respective DATA_REGISTER. On the contrary, if A 0 =1 the reading cycle is started on the bank EVEN after having incremented the address present in its address counter.

[0055] In any case, in both situations the bank in priority (EVEN if A 0 =0, ODD if A 0 =1) continues executing its read cycle and outputs the read data, successively it increases the address contained in its address counter and restarts a new read cycle. Should the external address change and the new address be consecutive to the previous one, the signals ATD_ADD and COMPARE are generated again as discussed above.

[0056] Because at least one of the address counters contains “a copy”of the external address, the result of the comparison between the external address and the address stored in the counters will be positive and when COMPARE=1, NEW_ADDR=0. In this case, unlike in the previous case, the signal UPDATE remains disabled.

[0057] On the other side, because NEW_ADDR=0 when COMPARE=1 a read stimulation signal NEW_SYNC is produced by the AND gate in cascade to the block DELAY&STRETCH. The NEW SYNC signal contains the information relative to the fact that the user requires new data and that the address in which it is stored is consecutive to the previous one. Therefore, if the reading relative to this new address is terminated, that is, the sense amplifiers have already placed into the relative DATA_REGISTER latch the read data, the data is output and a new read cycle is started onto the same bank. This is after having incremented its address counter. If on the contrary the reading has not yet finished, the system waits for the end of the read cycle.

[0058] The memory device of the invention, if used always in an asynchronous mode, could be performing slightly less than a standard asynchronous memory device because of the delay introduced in the phase that immediately follows the change of the external address in order to recognize the required read mode, i.e., synchronous or asynchronous.

[0059] To prevent this drawback, a buffer provided with means for pre-charging the output node is used, as the one depicted in FIG. 14 . This buffer brings the output node to an intermediate voltage Vcc/2 between the voltages relative to the two logic states upon the internal generation of a precharge pulse PRE_CHARGE, and lets the voltage on the output node evolve freely when the data to output is available (LOAD=1). Using this approach, the performance of the memory device of the invention is practically unaffected by any additional delay when functioning in an asynchronous mode.

[0060] Referring to FIG. 5 , each time a pulse ATD is produced, the block CHARGE_CONTROL generates a precharge signal PRECHARGE of the output node, thus setting it at the voltage Vcc/2. The pulse ATD is obtained as a logic AND between the control pulses ATD_CEn and the address transition detection pulse ATD_ADD, and indicates that an address transition or a resume from a stand-by state has occurred.

[0061] The precharge phase of the output node stops when the block CONTROL_LOGIC enables the output of the data read by the sense amplifiers by way of the signals LOAD_EVEN and LOAD_ODD. This phase is further conditioned by the state of the signal DISABLE that sets in a high impedance state the outputs, and depends from the state of signals CEn and OEn. During the precharge of the output node and when the outputs are set in a high impedance state, the path from the DATA_REGISTER to the output buffer is interrupted because the signal OUTLATCH is forced low by the NOR gate input with the above mentioned signals PRE_CHARGE and DISABLE.

[0062] By monitoring the state of the external signals, CEn, OEn and A 0 and of the asynchronous internal signals generated by the two blocks SENSE CTRL TIMING that manage the reading phases and of the other internally generated signals NEW_SYNC, ATD and UPDATE, the block CONTROL_LOGIC controls the following. The start of a new read cycle and the increment of the address counters by generating the signals INC_EVEN and INC_ODD. The loading of the read data from the output latches of the sense structures of the two banks DATA_ODD_REGISTER, DATA_EV_REGISTER into the output register that precedes the output buffers by generating the signals LOAD_EVEN and LOAD_ODD. The start of asynchronous readings in the following cases: resume from stand-by state, and loss of synchronization due to excessively fast address changes (out of specifications).

[0063] The block CONTROL_LOGIC is formed by three main circuits, as depicted in FIG. 7 . These circuit include a load circuit, a generator, and a restart circuit. The load circuit LOAD_PULSER produces pulses for loading read data in the output register. The generator INC_PULSER generates increment pulses for the address counters and for starting new read cycles in the two banks. A restart circuit UPDATE_LOGIC recognizes irregular conditions in which an asynchronous read cycle must restart and generate the signals ATD_CEn and OK_UPDATE.

[0064] The single functional circuits are described below in a more detailed manner. The LOAD PULSER circuit has the following characteristics. It produces the pulses necessary for loading the read data in the latch that precedes the output buffer. During the first asynchronous reading it is stimulated by the signal DLATCH to produce the first load pulse LOAD. In the successive synchronous readings it is stimulated by the switching of the external address monitored by way of the signal NEW_SYNC. This circuit is also able to synchronize the user request of new data with its availability, and depending on the address A 0 , it allows the loading of the data EVEN or the data ODD.

[0065] A block diagram of a possible embodiment of the circuit is depicted in FIG. 8 , while FIG. 9 illustrates the time evolution of the main signals. In FIG. 8 a block PULSER is depicted for producing a pulse of a certain duration each time it is stimulated by a transition 0 to 1 of the signal LOAD_STIM. In the first asynchronous reading (FIRST=1), the signal LOAD_STIM is the logic AND between the logic negation of the external enabling command of the output buffer OE and the signal DLATCH_E_On. The first signal (OE) contains the information relative to the enabling of the output buffer of the memory, the second (DLATCH_E_On) contains the information that the reading in progress has ended and the respective data latches in cascade to the sense amplifiers SENSE EVEN, SENSE_ODD have been updated.

[0066] In the successive synchronous readings, LOAD_STIM coincides with the signal OK_LOAD (FIRST=0) that is produced when any one of the following conditions is verified: change of the external address with a new address consecutive to the previous one (NEW_SYNC=1); external enabling of the output bus (OE=1); and end of the reading on the bank in priority, i.e., the reading relative to the new address (DLATCH of the bank in priority=0).

[0067] The latch SR that produces the signal SYNC_OK is set every time a new address successive to the previous one is input (NEW_SYNC=1) and is reset when the output registers are updated by a LOAD pulse. The block ONLY_FALLING_EDGE_DELAY delays only the falling edge of the start signal UPDATE of an asynchronous reading by producing the signal UPDATE_DEL. This signal is logically inverted and ANDed with the output of the pulse generator PULSER, and its function is to interrupt an eventual pulse LOAD when a new asynchronous reading starts. Finally the demultiplexer controlled by the state of A 0 (formed by the gates I 3 and I 4 ) directs the pulse LOAD towards the bank in priority.

[0068] The main functions of the circuit INC PULSER are as follows. The pulses that are necessary to increment the addresses stored in the address counters of the two banks are produced and the asynchronous readings are started. The first increment is produced considering the propagation delay of the carry through the counter. The first increment is suppressed if the asynchronous reading starts from an address on the EVEN bank. The main functions also include producing at the end of the respective read cycles the next increments for each of the two banks, producing a signal FIRST capable of discriminating the first asynchronous reading from the successive synchronous readings, and updating the pointer to the banks EVEN and ODD as a function of the address A 0 .

[0069] The circuit includes a pulse generator PULSER stimulated by a signal output by the multiplexer formed by the two pass gates PG 1 , PG 2 . The multiplexer is controlled by the signal FIRST that discriminates the first asynchronous read cycle from the successive synchronous ones.

[0070] The signal FIRST is generated by a latch SR, set by the start signal UPDATE of the asynchronous reading and reset by the signal LOAD that enables the loading of the data read from the sense amplifiers, thus stating the end of the first asynchronous read cycle. Therefore, during the first asynchronous reading, the pulse generator PULSER is stimulated by a replica of the signal UPDATE, delayed by the block CARRY_DELAY, to account for the propagation delay of the carry bit through the counter.

[0071] During the following synchronous readings, PULSER is stimulated by the logic negation of the signal LOAD to allow, at the end of the pulse LOAD, the increment of the address counter and the start of a new reading on the bank that has just terminated the current read cycle.

[0072] The pulse output by the pulse generator is logically filtered in the following situations. In the case of a first asynchronous reading EVEN (A 0 =0 and FIRST=1), during which, as already stated, it is not necessary to increase the ODD bank because its address counter already contains the correct address. In this situation OK_INC=0 in the case of eventual increments being in progress at the start of a new asynchronous reading cycle (UPDATE=1) that update the content of the counters with the new external address.

[0073] The block ONLY_FALLING_EDGE_DELAY delays only the falling edge of the signal UPDATE producing the signal UPDATE_DEL that, when it is at the high logic level, filters the increment. The pulse INC is correctly directed to the banks EVEN and ODD through the demultiplexer formed by the AND gates I 4 and I 5 and controlled by the following. A first case is the signal A 0 when FIRST=0. In this case the increment is provided to the bank in priority that has just made available the read data. A second case is the logic negation of the signal A 0 when FIRST=1. In this case the increment is provided to the bank that is not in priority. In fact, if the first asynchronous reading starts on the bank ODD, the first increment pulse must be provided to the counter EVEN.

[0074] The main function of the restart circuit UPDATE LOGIC is to recognize the situations in which the memory must start a new asynchronous reading cycle by producing a start signal of asynchronous reading (OK_UPDATE=1). A possible embodiment of this restart circuit is depicted in FIG. 12 , and diagrams of the internal signals when the block is active are depicted in FIG. 13 .

[0075] An asynchronous reading cycle must start in the following cases. A first case is to resume from a stand-by state. In this case the block FALLING_EDGE_TRANSITION_DETECTOR produces, on the falling edge of the external command of enablement of the memory device CEn, a control pulse ATD_CEn that is logically negated and ORed with the signal START_UPDATE, thus generating the signal for starting an asynchronous reading cycle OK_UPDATE. A second case is the loss of synchronization caused by an excessive frequency with which the user requires data. For example, the user changes the address before the end of a first asynchronous reading cycle. In this situation the reading must restart and the state machine must return to its initial state. During synchronous mode, the user requires new data (changes the address X in X+1) before the cycle relative to the previous reading is completed. That is, the increment pulse for the address counter is produced while the data X is yet to be loaded in the output.

[0076] Each time the external address changes, a pulse ATD is generated and the block UPDATE_LOGIC must either produce the signal OK_UPDATE depending on a state of the memory device. The irregular situation in which the user requires new data (by changing the external address) before the end of the reading relative to the current address with the consequent outputting of the read data and the incrementing of the counter of the bank in priority, is recognized by detecting two consecutive pulses ATD not interleaved by a general increment pulse INC.

[0077] In fact, in the first asynchronous cycle, if during the reading the user inputs a different address, a new pulse ATD preceding the general increment pulse INC of the bank in priority is produced. The eventual first pulse INC provided to the bank not in priority is filtered by the signal FIRST by the gate I 5 .

[0078] Similarly, during synchronous reading, if the user changes two or more times the input address before the memory is able to load in output the read data and to restart the reading in the memory bank (INC=1), the generation of two or more successive ATD pulses, not interleaved with general increment pulses INC, makes the circuit detect an anomalous situation and restart a new asynchronous reading (OK_UPDATE=1). The frequency with which data are requested is greater than the maximum frequency of the system. Therefore, when the address stabilizes itself, the memory correctly provides the respective data and this happens because for such an address input out of synchronization an asynchronous reading is carried out.

[0079] In the LATCH L 1 is stored the information relative to the state of the process that begins with the request of new data (ATD=0) and terminates with the loading in output of the read data, with a consequent start of a new reading on the bank in priority (INC=1).

[0080] In particular, a pulse ATD after having been logically negated sets Q 1 to 1. Q 1 will be reset to 0 only by a general increment pulse INC, as long as it is not the INC pulse that is produced during the first asynchronous reading to increment the bank EVEN when the first asynchronous reading starts on the bank ODD. Such an INC pulse is in fact filtered by the AND gate I 5 by using the logic negation of the signal FIRST.

[0081] The signal Q 1 enables, at the end of the pulse ATD, to force to 1 the signal SET (I 4 ) which in turn sets to 1 the output WAIT of the LATCH L 2 . The signal WAIT, when at a high logic level, carries the information that a first pulse ATD has been detected. Therefore, a successive pulse ATDn arriving in this phase produces, through I 2 , a pulse START_UPDATE that in turn produces a restart signal OK_UPDATE of an asynchronous cycle.

[0082] This does not happen if the new pulse ATD is preceded by a pulse INC that resets the latch L 1 (Q 1 to 0) on the rising edge and the latch L 2 (WAIT to 0) on the falling edge, thus keeping the signal START_UPDATE disabled. The time evolution of the signals of this circuit, in the case in which there is a normal first asynchronous read cycle, is depicted in FIG. 13 a.

[0083] The situation in which the new ATD, produced by an abrupt change of address by the user, causes the generation of a pulse OK_UPDATE, is depicted in FIG. 13 b. FIG. 13 c highlights a possible time evolution of the signals in the case of a standard synchronous reading phase, while FIG. 13 d illustrates the situation in which the new pulse ATD follows a previous one without being preceded by a general increment pulse INC, thus causing the generation of the pulse OK_UPDATE.