DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] FIG. 1 is a block diagram showing a structure of a DRAM according to one embodiment of the present invention. First, structure and operation of the entire DRAM will be described. With reference to FIG. 1 , the DRAM includes an internal power supply potential (intVCC) generation circuit 1 , a clock generation circuit 2 , a row and column address buffer 3 , a row decoder 4 , a redundant row decoder 5 , a column decoder 6 , a memory mat 7 , an input buffer 11 and an output buffer 12 , and the memory mat 7 includes a memory array 8 , a redundant memory array 9 and a sense amplifier+input/output control circuit 10 .

[0029] The internal power supply potential generation circuit 1 receives an external power supply potential VCC and a ground potential GND to generate an internal power supply potential intVCC lower than the external power supply potential VCC and apply the same to the entire DRAM. The internal power supply potential intVCC can be tuned by a group of fuses provided in the internal power supply potential generation circuit 1 . The clock generation circuit 2 selects a predetermined operation mode to control the entire DRAM based on externally applied signals /RAS and /CAS.

[0030] The row and column address buffer 3 generates row address signals RA 0 to RAi and column address signals CA 0 to CAi based on externally applied address signals A 0 to Ai (i: an integer not less than 0) and applies the generated signals RA 0 to RAi and CA 0 to CAi to the row decoders 4 and 5 and the column decoder 6 , respectively.

[0031] The memory array 8 includes a plurality of memory cells disposed in a matrix each for storing 1-bit data. Each memory cell is arranged at a predetermined address determined by a row address and a column address.

[0032] The row decoder 4 designates a row address of the memory array 8 in response to the row address signals RA 0 to RAi applied from the row and column address buffer 3 . Provided in the redundant row decoder 5 is a group of fuses for programming a row address containing a defective memory cell in the memory array 8 and a row address replacing the row address in question in the redundant memory array 9 . When the row address signal RA 0 to RAi corresponding to the defective row address programmed by the group of fuses is applied, the row decoder 4 refrains from designating the row address in question and the redundant row decoder 5 designates a row address of the redundant memory array 9 programmed in place of the row address in question. In other words, a defective memory cell row containing a defective memory cell in the memory array 8 is replaced by a normal memory cell row in the redundant memory array 9 .

[0033] The column decoder 6 designates a column address of the memory array 8 in response to the column address signals CA 0 to CAi applied from the row and column address buffer 3 . The sense amplifier+input/output control circuit 10 connects a memory cell at an address designated by the row decoder 4 (or the redundant row decoder 5 ) and the column decoder 6 to one end of a data input/output line pair IOP. The other end of the data input/output line pair IOP is connected to the input buffer 11 and the output buffer 12 . The input buffer 11 , in a writing mode, applies eternally applied data Dj (j: natural number) to a memory cell selected through the data input/output line pair IOP in response to an externally applied signal /W. The output buffer 12 , in a reading mode, externally outputs read data Qi from a selected memory cell in response to an externally applied signal /OE.

[0034] FIG. 2 is a circuit block diagram showing a part of the structure of the memory mat 7 of the DRAM illustrated in FIG. 1 .

[0035] In FIG. 2 , the memory array 8 includes a plurality of memory cells MC disposed in a matrix, a word line WL provided corresponding to each row, and a bit line pair BL, /BL provided corresponding to each column.

[0036] Each memory cell MC is a well known memory cell including an N channel MOS transistor for access and a capacitor for storing information. The word line WL transmits output of the row decoder 4 to activate a memory cell MC in a selected row. The bit line pair BL, /BL inputs and outputs a data signal to and from a selected memory cell MC.

[0037] The redundant memory array 9 has the same structure as that of the memory array 8 with the only difference being that the number of rows is smaller than that of the memory array 8 . The memory array 8 and the redundant memory array 9 have the same number of columns and the bit line pair BL, /BL is shared by the memory array 8 and the redundant memory array 9 . The word line of the redundant memory array 9 is assumed to be a spare word line SWL.

[0038] The sense amplifier+input/output control circuit 10 includes the data input/out line pair IO, /IO (IOP), a column selection gate 13 , a sense amplifier 14 and an equalizer 15 provided corresponding to each column. The column selection gate 13 includes a pair of N channel MOS transistors connected between the bit line pair BL, /BL and the data input/output line pair IO, /IO. Gates of a pair of the N channel MOS transistors of each column selection gate are connected to the column decoder 6 through a column selection line CSL. When the column selection line CSL is brought to a logical high or “H” level of a selection level by the column decoder 6 , a pair of N channel MOS transistors is rendered conductive to couple the bit line pair BL, /BL and the data input/output line pair IO, /IO.

[0039] In response to sense amplifier activating signals SE, /SE attaining the “H” level and a logical low or “L” level, respectively, the sense amplifier 14 amplifies a small potential difference between the bit line pair BL, /BL to the internal power supply voltage intVCC. In response to a bit line equalizing signal BLEQ attaining an “H” level of an activation level, the equalizer 15 equalizes a potential of the bit line pair BL, /BL to a bit line potential VBL (=intVCC/2).

[0040] Next, operation of the DRAM shown in FIGS. 1 and 2 will be described. In the writing mode, the column decoder 6 brings a column selection line CSL in a column corresponding to the column address signal CA 0 to CAi to the “H” level of the selection level to render the column selection gate 13 of the column in question conductive.

[0041] The input buffer 11 applies the external write data Dj to the bit line pair BL, /BL of a selected column through the data input/out line pair IOP in response to the signal /W. The write data Dj is applied as a potential difference between the bit lines BL and /BL. Next, the row decoder 4 brings a word line WL in a row corresponding to the row address signal RA to RAi to the “H” level of the selection level, so that an N channel MOS transistor of the memory cell MC in the row in question becomes conductive. In a capacitor of the selected memory cell MC, electric charges are accumulated whose amount corresponds to a potential of the bit line BL or /BL.

[0042] In the reading mode, first the bit line equalizing signal BLEQ rises to the “L” level to stop equalization of the bit lines BL and /BL. Then, the row decoder 4 brings a word line WL in a row corresponding to the row address signal RA 0 to RAi to the “H” level of the selection level, so that an N channel MOS transistor of the memory cell MC in the row in question becomes conductive. Responsively, the potentials of the bit lines BL and /BL change a little according to the amount of electric charges in the capacitor of the activated memory cell MC.

[0043] Next, the sense amplifier activating signals SE and /SE attain the “H” level and the “L” level, respectively, to activate the sense amplifier 14 . When the potential of the bit line BL is a little higher than the potential of the bit line /BL, the potential of the bit line BL is brought to the “H” level and the potential of the bit line /BL is brought down to the “L” level. Conversely, when the potential of the bit line /BL is a little higher than the potential of the bit line BL, the potential of the bit line /BL is brought down to the “H” level and the potential of the bit line BL is brought down to the “L” level.

[0044] Next, the column decoder 6 brings a column selection line CSL in a column corresponding to the column address signal CA 0 to CAi to the “H” level of the selection level to render the column selection gate 13 of the column in question conductive. Data of the bit line pair BL, /BL of the selected column is applied to the output buffer 12 through the column selection gate 13 and the data input/output line pair IO, /IO. The output buffer 12 externally outputs the read data Qi in response to the signal /OE.

[0045] When the row address signal RA 0 to RAi corresponds to a row containing a defective memory cell MC, the spare word line SWL of the redundant memory array 9 is selected in place of the word line WL in the row containing the defective memory cell MC and the writing and reading operation is similarly conducted. Thus, such a semiconductor memory as a DRAM adopts a method of replacing defective rows and columns by spare rows and columns in order to improve a rate of good chips on a semiconductor wafer. In the following, detailed description will be made of a part related to a wafer test and a final test as characteristics of the present invention.

[0046] FIG. 3 is a circuit block diagram showing the structure of the internal power supply potential generation circuit 1 . In FIG. 3 , the internal power supply potential generation circuit 1 includes a low-pass filter 30 , a constant-current source 31 and a variable resistance circuit 32 .

[0047] The low-pass filter 30 includes a resistance element 33 and a capacitor 34 . The resistance element 33 is connected between the line of the external power supply potential VCC and a node N 30 and the capacitor 34 is connected between the node N 30 and the line of the ground potential GND. The external power supply potential VCC is applied to the node N 30 through the resistance element 33 .

[0048] The constant-current source 31 includes a resistance element 35 , P channel MOS transistors 36 to 38 and N channel MOS transistors 39 and 40 . The resistance element 35 and the MOS transistors 36 and 39 , the MOS transistors 37 and 40 , and the MOS transistor 38 and the variable resistance circuit 32 are respectively connected in series between the node N 30 and the line of the ground potential GND. Gates of the P channel MOS transistors 36 to 38 are all connected to a drain of the P channel MOS transistor 37 . Gates of the N channel MOS transistors 39 and 40 are both connected to a drain of the N channel MOS transistor 39 . The P channel MOS transistor 36 to 38 and the N channel MOS transistors 39 and 40 form current-mirror circuits, respectively. To the P channel MOS transistor 38 , a constant current Ic flows which has a value corresponding to a resistance value of the resistance element 35 , to a size ratio of the P channel MOS transistors 36 to 38 or the like.

[0049] The variable resistance circuit 32 , as illustrated in FIG. 4 , includes a plurality (four in the figure) of P channel MOS transistors 41 to 44 connected in series between an output node N 31 (drain of the P channel MOS transistor 38 ) of the constant-current source 31 and a node 51 , and a plurality (two in the figure) of P channel MOS transistors 45 and 46 connected in series between the node N 51 and the line of the ground potential GND. Gates of the P channel MOS transistors 41 to 44 are all grounded and gates of the P channel MOS transistors 45 and 46 are connected to their own drains. Each of the P channel MOS transistors 41 to 44 forms a resistance element and each of the P channel MOS transistors 45 and 46 forms a diode element.

[0050] The variable resistance circuit 32 further includes fuses 48 to 51 connected in parallel to the P channel MOS transistors 41 to 44 and an N channel MOS transistor 47 connected between the nodes N 31 and N 51 and having a gate receiving a signal LTB. The signal LTB is a signal which attains a “L” level of an inactivation level in ordinary operation and attains the “H” level of the activation level in a mode for returning to a state prior to laser trimming (LT). The pre-LT state return mode is a mode for returning the DRAM to a state before the fuses 48 to 51 are cut off by laser trimming, which is set by a so-called address key.

[0051] In ordinary operation, the signal LTB attains the “L” level of the inactivation level to render the N channel MOS transistor 47 non-conductive. At this time, assume that a value of a resistance between the nodes N 31 and N 51 is denoted as R and each threshold voltage of the P channel MOS transistors 45 and 46 is denoted as Vth, the internal power supply potential intVCC will be expressed as 2×Vth+R×Ic. Since the P channel MOS transistors 41 to 44 have resistance values different from each other, the internal power supply potential intVCC can be tuned at a stage of 2 ⁴ =16 by cutting off or not cutting off each of the fuses 48 to 51 . In the pre-LT state return mode, the signal LTB attains the “H” level of the activation level to render the N channel MOS transistor 47 conductive, so that a value of the resistance between the nodes N 31 and N 51 is returned to a value at a state before cut-off of the fuses 48 to 51 .

[0052] FIG. 5 is a circuit diagram showing a structure of a predecoder 4 a included in the row decoder 4 . In the following, the predecoder is provided with four word lines WL and one spare word line SWL for the simplicity of illustration and description.

[0053] In FIG. 5 , the predecoder 4 a includes gate circuits 60 to 63 and AND gates 64 to 67 . Each of the gate circuits 60 to 63 receives the row address signals RA 0 and RA 1 . The gate circuit 60 outputs a “H” level (1) only when both of the signals RA 0 and RA 1 are at a “L” level (0). The gate circuit 61 outputs the “H” level only when the address signals RA 0 and RA 1 are at the “H” level and the “L” level, respectively. The gate circuit 62 outputs the “H” level only when the signals RA 0 and RA 1 are at the “L” level and the “H” level, respectively. The gate circuit 63 outputs the “H” level only when the signals RA 0 and RA 1 are both at the “H” level.

[0054] Output signals of the gate circuits 60 to 63 are applied to ones of input nodes of the AND gates 64 to 67 , respectively. To the other input nodes of the AND gates 64 to 67 , a signal φA is applied. The signal φA is a signal which attains the “L” level in a stand-by mode and the “H” level in an active mode. Output signals of the AND gates 64 to 67 become predecoding signals X 0 to X 3 , respectively. The predecoding signals X 0 to X 3 are assigned to the four word lines WL, respectively.

[0055] At the stand-by, the signals X 0 to X 3 attain the “L” level. In the active mode, one of the signals X 0 to X 3 attains the “H” level (1) according to the row address signals RA 0 and RA 1 as shown in the table below. 1

[0056] FIG. 6 is a circuit block diagram showing the structure of the redundant row decoder 5 . In FIG. 6 , the redundant row decoder 5 includes fuses 70 a to 70 d , N channel MOS transistors 71 a to 71 d , 72 a to 72 d , 73 and 74 , a P channel MOS transistor 75 and a word driver 76 .

[0057] The P channel MOS transistor 75 is connected between the line of the internal power supply potential intVCC and a node N 70 and has a gate receiving a precharging signal /PC. In the stand-by mode, the signal /PC attains a “L” level of the activation level and in the activation mode, attains the “L” level of the activation level only for a predetermined time before the word lines WL and SWL are selected. When the signal /PC attains the “L” level of the activation level, the P channel MOS transistor 75 is rendered conductive to precharge the node N 70 to the “H” level.

[0058] Ones of terminals of the fuses 70 a to 70 d are all connected to the node N 70 . The N channel MOS transistors 71 a to 71 d are connected between the other terminals of the fuses 70 a to 70 d and the line of the ground potential, respectively, and have gates receiving the signals X 0 to X 3 , respectively. The N channel MOS transistors 72 a to 72 d are connected in parallel to the fuses 70 a to 70 c and have gates receiving the signal LTB.

[0059] The fuses 70 a to 70 d are assigned to four word lines WL. Each of the fuses 70 a to 70 d , when its corresponding word line WL is defective, is cut off in a case of replacing the word line WL in question with the spare word line SWL. Only one of the fuses 70 a to 70 d can be cut off.

[0060] When any one of the signals X 0 to X 3 (e.g. X 0 ) attains the “H” level of the activation level according to the row address signals RA 0 and RA 1 , the N channel MOS transistor 71 a corresponding to the signal X 0 is rendered conductive. When the fuse 70 a corresponding to the signal X 0 is not cut off, the level of the node N 70 is brought down from the “H” level to the “L” level, while when the fuse 70 a is cut off, the level of the node N 70 remains unchanged. The signal appearing on the node N 70 will be a hit signal φH. In the pre-LT state return mode, the signal LTB attains the “H” level of the activation level to render the N channel MOS transistors 72 a to 72 d conductive, so that the redundant row decoder 5 becomes equivalent to a state where none of the fuses 70 a to 70 d is cut off. Accordingly, in the pre-LT state return mode, the hit signal φH is brought from the “H” down to the “L” level without fail.

[0061] The N channel MOS transistor 73 is connected between the node N 70 and a gate of the N channel MOS transistor 74 and has a gate receiving the internal power supply potential intVCC. The N channel MOS transistor 73 is provided for protecting the N channel MOS transistor 74 . The N channel MOS transistor 74 has a drain receiving a word line selecting signal φR and a source connected to a control node 76 a of the word driver 76 . The word driver 76 brings the spare word line SWL to a “L” level of a non-selected level when the control node 76 a is at the “L” level and brings the spare word line SWL to the “H” level of the selection level when the control node 76 a is at the “H” level.

[0062] FIG. 7 is a circuit block diagram showing a structure of a row decoder unit circuit 4 included in the row decoder 4 . The row decoder unit circuit 4 is provided corresponding to each word line WL. Illustrated in FIG. 7 is the row decoder unit circuit 4 corresponding to a word line WL to which the predecoding signal X 0 is assigned. In FIG. 7 , the row decoder unit circuit 4 includes N channel MOS transistors 80 to 83 , a P channel MOS transistor 84 , an inverter 85 , a resistance element 86 and a word driver 87 .

[0063] The P channel MOS transistor 84 is connected between the line of the internal power supply potential intVCC and a node N 80 and has a gate receiving the precharging signal /PC. When the signal /PC maintains the “L” level of the activation level for a fixed time period, the P channel MOS transistor 84 is rendered conductive to precharge the node N 80 to the “H” level.

[0064] The N channel MOS transistor 80 is connected between the node N 80 and the line of the ground potential GND and has a gate receiving the corresponding predecoding signal X 0 . When the signal X 0 attains the “H” level of the activation level, the N channel MOS transistor 80 is rendered conductive, so that the level of the node N 80 falls from the “H” level to the “L” level.

[0065] The N channel MOS transistor 81 is connected between the node N 80 and an input node of the inverter 85 and has a gate receiving the internal power supply potential intVCC. The N channel MOS transistor 81 is provided for protecting the inverter 85 . An output signal of the inverter 85 is applied to a gate of the N channel MOS transistor 83 through the resistance element 86 . The N channel MO transistor 82 is connected between the gate of the N channel MOS transistor 83 and the line of the ground potential GND and has a gate receiving the hit signal φH. When the hit signal φH is at the “H” level of the activation level, the N channel MOS transistor 82 is rendered conductive to bring the gate of the N channel MOS transistor 83 to the “L” level, so that the N channel MOS transistor 83 is rendered conductive. In the pre-LT state return mode, since the hit signal φH is brought down from the “H” level to the “L” level without fail, the N channel MOS transistor 84 is rendered non-conductive, so that the level of an output signal of the inverter 85 is transmitted as it is to the gate of the N channel MOS transistor 83 .

[0066] The N channel MOS transistor 83 has a drain receiving the word line selecting signal φR and a source connected to a control node 87 a of the word driver 87 . The word driver 87 brings the corresponding word line WL to the “L” level of the non-selected level when the control node 87 a is at the “L” level and brings the corresponding word line WL to the “H” level of the selection level when the control node 87 a is at the “H” level.

[0067] Next, operation of the row decoders 4 and 5 shown in FIGS. 5 to 7 will be described. FIGS. 8A to 8 F are time charts showing operation conducted when the word line WL corresponding to the predecoding signal X 0 is normal and the normal word line WL is selected. In this case, the fuse 70 a corresponding to the signal X 0 will not be cut off.

[0068] First, at time t 1 , when the precharging signal /PC falls to the “L” level of the activation level, the P channel MOS transistor 75 in FIG. 6 is rendered conductive to bring the level of the node N 70 , that is, the hit signal φH, to the “H” level, and the P channel MOS transistor 84 in FIG. 7 is rendered conductive to bring the level of the node N 80 to the “H” level.

[0069] Next, at time t 2 , the precharging signal /PC is brought to the “H” level of the inactivation level to render the P channel MOS transistors 75 and 84 non-conductive, so that precharging of the nodes N 70 and N 80 is stopped. At the same time, the predecoding signal X 0 is brought to the “H” level of the activation level to render the N channel MOS transistor 71 a in FIG. 6 conductive to bring the signal φH down to the “L” level and render the N channel MOS transistor 80 in FIG. 7 conductive to bring the node N 80 to the “L” level. As a result, the N channel MOS transistor 74 in FIG. 6 becomes non-conductive, while the N channel MOS transistor 83 of FIG. 7 becomes conductive.

[0070] Then, at time t 3 when the word line selecting signal φR is brought to the “H” level, the word driver 87 in FIG. 7 is activated to bring the word line WL corresponding to the predecoding signal X 0 to the “H” level of the selection level. Since the N channel MOS transistor 74 in FIG. 6 is non-conductive, the word driver 6 will not be activated, so that the spare word line SWL remains unchanged at the “L” level of the non-selected level. At time t 4 , when the signals X 0 and φR attain the “L” level of the inactivation level, the word line WL attains the “L” level of the non-selected level.

[0071] FIGS. 9A to 9 F are time charts showing operation conducted when the word line WL corresponding to the predecoding signal X 0 is defective and the defective word line WL is selected. In this case, the fuse 70 a corresponding to the signal X 0 is cut off. Assume here that the signal LTB is at the “L” level of the inactivation level and the N channel MOS transistors 72 a to 72 d are non-conductive.

[0072] Operation conducted before the precharging signal /PC attains the “L” level of the activation level and the nodes N 70 and N 80 are precharged to the “H” level from time t 1 to time 2 is the same as that described with reference to FIGS. 8A to 8 F. When the predecoding signal X 0 is brought to the “H” level of the activation level at time t 2 , the N channel MOS transistor 71 a in FIG. 6 is rendered conductive, while the hit signal φH remains unchanged at the “H” level because the fuse 70 a is cut off.

[0073] On the other hand, when the predecoding signal X 0 is brought to the “H” level of the activation level, the N channel MOS transistor 80 in FIG. 7 is rendered conductive, so that the node N 80 attains the “L” level and the inverter 85 outputs the “H” level. However, since the signal φH is at the “H” level, the N channel MOS transistor 82 is rendered conductive and the gate of the N channel MOS transistor 83 remains unchanged at the “L” level. Accordingly, the N channel MOS transistor 74 in FIG. 6 is rendered conductive, while the N channel MOS transistor 83 in FIG. 7 is not rendered conductive.

[0074] Then, at time T 3 , when the word line selecting signal φR rises to the “H” level of the activation level, the word driver 76 in FIG. 6 is activated to bring the spare word line SWL to the “H” level of the selection level. Since the N channel MOS transistor 83 in FIG. 7 is non-conductive, the word driver 87 is not activated, so that the defective word line WL corresponding to the predecoding signal X 0 remains unchanged at the “L” level of the non-selected level. When at time t 4 , the signals X 0 and φR attain the “L” level of the inactivation level, the spare word line SWL attains the “L” level of the non-selected level.

[0075] In the pre-LT state return mode, the signal LTB attains the “H” level of the activation level to render the N channel MOS transistors 72 a to 72 d in FIG. 6 conductive, whereby the redundant row decoder 5 becomes equivalent to a state where none of the fuses 70 a to 70 d is cut off. In this case, the word line WL corresponding to the row address signal RA 0 to RAi is brought to the “H” level irrespective of cut-off of the fuses 70 a to 70 d . Accordingly, when a memory cell MC corresponding to the row address signal RA 0 to RAi is defective, no data writing/reading is normally conducted.

[0076] Next, a method of testing the DRAM will be described. First, with numerous DRAM chips formed on a semiconductor wafer, a wafer test is performed. In the wafer test, with a test probe being in contact with a pad of each DRAM chip, the test is performed to determine whether each memory cell MC of each DRAM chip is normal or not under predetermined wafer test conditions.

[0077] When there exists a memory cell row containing a defective memory cell MC, the fuse in FIG. 6 (e.g. 70 a ) corresponding to the memory cell row in question is cut off and the memory cell row is replaced by a spare memory cell row. In addition, a regular external power supply potential VCC is applied to selectively connect the fuses 48 to 51 , so that tuning of the internal power supply potential intVCC is conducted.

[0078] Thereafter, the semiconductor wafer is vertically and horizontally cut to cut out each DRAM chip, and normal DRAM chips and remedied DRAM chips are accommodated in packages to make products.

[0079] Next, a final test of each DRAM product is conducted. At the final test, with each DRAM product mounted on a test board, a test is performed to determine whether each memory cell MC of each DRAM product is normal or not under predetermined final test conditions. Normal DRAM products are shipped and DRAM products whose memory cells MC are newly detected being defective are subjected to a defective mode analysis. Difference in results of the wafer test and the final test derives from different test conditions. While the wafer test is conducted with a test probe being in contact with a pad of each DRAM chip, the final test is conducted with each DRAM product mounted on a test board under more severer conditions than those of actual use. Since it is preferable that results of the wafer test and the final test coincide with each other, results of the final test are analyzed and the analysis results are fed back into the wafer test conditions.

[0080] FIG. 10 is a flow chart showing a method of analyzing the DRAM illustrated in FIGS. 1 to 9 F. In FIG. 10 , at step S 1 , set the pre-LT state return mode by an address key. As a result, the signal LTB attains the “H” level of the activation level, so that the N channel MOS transistor 47 in FIG. 4 and the N channel MOS transistors 72 a to 72 d in FIG. 6 are rendered conductive to return the DRAM to a state before laser trimming, that is, to a state at the wafer test.

[0081] Next at Step S 2 , conduct an analysis of a DRAM defective mode to obtain new wafer test conditions. More specifically, perform a test of a DRAM product to be tested under current wafer test conditions or under various wafer test conditions to compare a test result and a final test result. Then, seek for a new wafer test condition under which the same results as those of the final test are obtained.

[0082] Next, at Step S 3 , with respect to a DRAM product to be tested, perform a test under new wafer test conditions to determine at step S 4 whether the defective DRAM product can be remedied at the stage of the wafer test or not. When it can not be remedied, return to Step S 2 to analyze a defective mode again to obtain new wafer test conditions. When at Step S 4 the determination is made that the product can be remedied, test a DRAM product at step S 5 which is determined to be normal at the final test under new wafer test conditions to determine whether the DRAM product is rejected as a defective product or not.

[0083] When at step S 5 the determination is made that the normal DRAM product is rejected, return to step S 2 to again analyze a defective mode and obtain new wafer test conditions. When at step S 5 the determination is made that the normal DRAM product is not rejected, determination is made at step S 6 that the new wafer test conditions are adopted.

[0084] In the present embodiment, since by setting the pre-LT state return mode, a DRAM product can be returned to a state before laser trimming, that is, a state at the wafer test, a defective mode can be accurately analyzed to obtain optimum wafer test conditions. It is therefore possible to drastically reduce an analysis time and improve a yield.

[0085] Although the present embodiment has been described with respect to a case where the present invention is applied to a method of replacing a memory cell row containing a defective memory cell by a spare memory cell row, it is clearly understood that the present invention is applicable also to a method of replacing a memory cell column containing a defective memory cell by a spare memory cell column.

[0086] Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.