DETAILED DESCRIPTION OF THE INVENTION

[0076] A semiconductor device according to a first embodiment of the invention will now be described with reference to FIGS. 1 and 2 . FIG. 1 is a circuit diagram of a bistable memory cell 100 consisting of one enhancement-mode IGFET “pull-up” element 110 and one NDR-FET “pull-down” element 120 , and FIG. 2 is a current-vs.-voltage plot illustrating the operational characteristics of the bistable memory cell of FIG. 1 .

[0077] As is shown in FIG. 1, a positive voltage V _cc is supplied to a drain electrode and gate electrode of IGFET 110 , and a source electrode of IGFET 110 is connected together with a drain electrode of NDR-FET 120 to a common control terminal at potential V _control , and a source electrode of NDR-FET 120 is connected to a ground terminal. With its drain electrode and gate electrode biased at the same potential, IGFET 110 operates in a saturation mode. A current flowing in IGFET 110 , I _IGFET ) is directly dependent on a voltage difference between its drain electrode potential and its source electrode potential, V _cc -V _control , and increases as V _cc -V _control increases, i.e. as V _control decreases below V _cc . A positive voltage V _bias is supplied to the gate electrode of NDR-FET 120 , such that a current flowing in NDR-FET 120 , I _NDR-FET , will exceed that of IGFET 110 over a range of values for V _control . I _NDR-FET is dependent on a difference between its drain electrode potential and its source electrode potential, V _control , at first increasing rapidly as V _control increases (i.e., operating as a conventional FET), reaching a peak value when V _control is equal to a critical voltage V _NDR , and rapidly decreasing to nearly zero as V _control increases beyond the critical voltage V _NDR (i.e., operating as an NDR FET).

[0078] Now the operation of memory circuit 100 of FIG. 1 will be described. FIG. 2 shows a current-vs.-voltage (I-V) characteristic curve I _IGFET of IGFET 110 obtained by changing a control voltage V _control applied to a control terminal in a range between 0 and V _cc , superimposed with the I-V characteristic curve I _NDRFET of NDR-FET 120 . A stable operating point of circuit 100 occurs at a point where I-V characteristic curve I _IGFET of IGFET 110 crosses an I-V characteristic curve I _NDRFET of NDR-FET 120 and additionally the characteristic curves I _IGFET and I _NDRFET have different gradient signs (positive, negative, or zero). (A crossing point where both characteristic curves I _IGFET and I _NDRFET have positive or negative gradient is not a stable operating point.) Therefore it is understood that circuit 100 is stable when a potential V _control at a control terminal is one of two values V _low and V _cc as shown in FIG. 2 . Accordingly, circuit 100 can be used as a bistable memory cell by applying a potential of one of the two values V _low and V _cc to control terminal as a write voltage. If the value of V _control falls slightly below that of a stable operating point, the IGFET current I _IGFET becomes higher than the NDR-FET current I _NDR-FET , causing the value of V _control to be increased toward V _cc , to restore it to that of the stable operating point. Thus IGFET 110 serves as a “pull-up” device. If the value of V _control increases slightly above that of a stable operating point, the NDR-FET current I _NDR-FET becomes higher than the IGFET current I _IGFET causing the value of V _control to be decreased toward 0 V (ground potential), to restore it to that of the stable operating point. Thus NDR-FET 120 serves as a “pull-down” device.

[0079] In this manner, a bistable memory cell can be obtained when an NDR-FET and an IGFET are formed on the same semiconductor substrate. Data can be written or read from such cell 100 in any conventional fashion known to those in the art.

[0080] NDR FET 120 and IGFET 110 can thus share a number of common structural features, including isolation regions, source/drain regions, gate insulating layers, gate electrode layers, contact layers, etc., and be manufactured according to a common set of processing operations. This latter feature ensures that the present invention is easily integrable into contemporary conventional wafer manufacturing facilities.

[0081] For the discusson below, except where otherwise noted, like numbered structures referenced in the text and in the drawings are intended to correspond to the same structures as previously discussed in connection with FIGS. 1 and 2 .

[0082] A semiconductor circuit according a second embodiment of the invention will now be described with reference to FIGS. 3 and 4 . FIG. 3 is a circuit diagram of a bistable memory cell 100 consisting of one NDR-FET “pull-up” element 120 and one enhancement-mode IGFET “pull-down” element 110 , and FIG. 4 is a current-vs.-voltage plot illustrating the operational characteristics of the bistable memory cell of FIG. 3 .

[0083] As is shown in FIG. 3, a positive voltage V _cc is supplied to the drain electrode of NDR-FET 120 , the source electrode of NDR-FET 120 is connected together with the drain electrode of IGFET 110 and the gate electrode of IGFET 110 to a common control terminal at potential V _control , and the source electrode of IGFET 110 is connected to a ground terminal. With its drain electrode and gate electrode biased at the same potential, IGFET 110 again operates in the saturation mode. The current flowing in IGFET 110 , I _IGFET , is directly dependent on the difference between its drain electrode potential and its source electrode potential, V _control , and increases as V _control increases. A positive voltage V _bias is supplied to the gate electrode of NDR-FET 120 , such that the current flowing in the NDR-FET, I _NDR-FET , will exceed that of IGFET 110 over a range of values for V _control . I _NDR-FET is dependent on the difference between its drain electrode potential and its source electrode potential, V _cc -V _control , at first increasing rapidly as V _cc -V _control increases, reaching a peak value when V _cc -V _control is equal to a critical voltage V _NDR , and rapidly decreasing to nearly zero as V _cc -V _control increases beyond the critical voltage V _NDR .

[0084] Now the operation of circuit 100 of FIG. 3 will be described. FIG. 4 shows the current-vs.-voltage (I-V) characteristic curve I _IGFET of IGFET 110 obtained by changing the control voltage V _control applied to the control terminal in a range between 0 and V _cc , superimposed with the I-V characteristic curve I _NDR-FET of the NDR-FET. As before, a stable operating point of the circuit is a point where the I-V characteristic curve I _IGFET of IGFET 110 crosses the I-V characteristic curve I _NDRFET of NDR-FET 120 and additionally the characteristic curves I _IGFET and I _NDRFET have different gradient signs (positive, negative, or zero). (A crossing point where both of the characteristic curves I _IGFET and I _NDRFET have positive or negative gradient is not a stable operating point.) Therefore it is understood that the circuit is stable when the potential V _control at the control terminal is one of two values 0 and V _high as shown in FIG. 4 . Accordingly, circuit 100 also can be used as a bistable memory cell by applying a potential of one of the two values 0 and V _high to the control terminal as a write voltage. If the value of V _control falls slightly below that of a stable operating point, the NDR-FET current I _NDR-FET becomes higher than the IGFET current IIGFET, causing the value of V _control to be increased toward V _cc , to restore it to that of the stable operating point. Thus in this embodiment NDR-FET 120 serves as a “pull-up” device. If the value of V _control increases slightly above that of a stable operating point, IGFET current I _IGFET becomes higher than the NDR-FET current I _NDR-FET, causing the value of V _control to be decreased toward 0 V (sound potential), to restore it to that of the stable operating point. Thus IGFET 110 serves as a “pull-down” device in this embodiment. In this manner, a bistable memory cell can be obtained when an NDR-FET and an IGFET are formed on the same semiconductor substrate.

[0085] A semiconductor device according a third embodiment of the invention will now be described with reference to FIGS. 5 and 6 . FIG. 5 is a circuit diagram of a bistable memory cell 100 consisting of one depletion-mode IGFET “pull-up” element 115 and one NDR-FET “pull-down” element 120 , and FIG. 6 is a current-vs.-voltage plot illustrating the operational characteristics of the bistable memory cell of FIG. 5 .

[0086] As is shown in FIG. 5, a positive voltage V _cc is supplied to the drain electrode of IGFET 115 , the gate electrode of IGFET 115 is connected together with the source electrode of IGFET 115 and the drain electrode of NDR-FET 120 to a common control terminal at potential V _control , and the source electrode of NDR-FET 120 is connected to a ground terminal. The current flowing in the IGFET, I _IGFET , is directly dependent on the difference between its drain electrode potential and its source electrode potential, V _cc -V _control and increases as V _cc -V _control increases, i.e. as V _control decreases below V _cc . I _GFET increases relatively slowly as V _cc -V _control increases above a saturation voltage V _Dsat . A positive voltage V _bias is supplied to the gate electrode of NDR-FET 120 , such that the current flowing in the NDR-FET, I _NDR-FET , will exceed that of IGFET 115 over a range of values for V _control . I _NDR-FET is dependent on the difference between its drain electrode potential and its source electrode potential, V _control , at first increasing rapidly as V _control increases, reaching a peak value when V _control is equal to a critical voltage V _NDR , and rapidly decreasing to nearly zero as V _control increases beyond the critical voltage V _NDR .

[0087] Now the operation of the circuit of FIG. 5 will be described. FIG. 6 shows the current-vs.-voltage (I-V) characteristic curve I _IGFET of IGFET 115 obtained by changing the control voltage V _control applied to the control terminal in a range between 0 and V _cc , superimposed with the I-V characteristic curve I _NDR-FET of NDR-FET 120 . A stable operating point of circuit 100 is a point where the I-V characteristic curve I _IGFET of the IGFET crosses the I-V characteristic curve I _NDRFET of the NDR-FET and additionally the characteristic curves I _IGFET and I _NDRFET have different gradient signs (positive, negative, or zero). (A crossing point where both of the characteristic curves I _IGFET and I _NDRFET have positive or negative gradient is not a stable operating point.) Therefore it is understood that the circuit is stable when the potential V _control at the control terminal is one of two values V _low and V _cc as shown in FIG. 6 .

[0088] Accordingly, circuit 100 can be used as a bistable memory cell by applying a potential of one of the two values V _low and V _cc to the control terminal as a write voltage. If the value of V _control falls slightly below that of a stable operating point, the IGFET current I _IGFET becomes higher than the NDR-FET current I _NDR-FET , causing the value of V _control to be increased toward V _cc , to restore it to that of the stable operating point. Thus IGFET 115 serves as a “pull-up” device. If the value of V _control increases slightly above that of a stable operating point, the NDR-FET current I _NDR-FET becomes higher than the IGFET current I _IGFET , causing the value of V _control to be decreased toward 0 V (ground potential), to restore it to that of the stable operating point. Thus NDR-FET 120 serves as a “pull-down” device. In this manner, a bistable memory cell can be obtained when an NDR-FET and an IGFET are formed on the same semiconductor substrate.

[0089] A semiconductor device according a fourth embodiment of the invention will now be described with reference to FIGS. 7 and 8 . FIG. 7 is a circuit diagram of a bistable memory cell 100 consisting of one NDR-FET “pull-up” element 120 and one depletion-mode IGFET “pull-down” element 115 , and FIG. 8 is a current-vs.-voltage plot illustrating the operational characteristics of the bistable memory cell 100 of FIG. 7 .

[0090] As is shown in FIG. 7, a positive voltage V _cc is supplied to the drain electrode of NDR-FET 120 , the source electrode of NDR-FET 120 is connected together with the drain electrode of IGFET 115 to a common control terminal at potential V _control , and the gate electrode of IGFET 115 is connected together with the source electrode of IGFET 115 to a ground terminal. The current flowing in the IGFET, I _IGFET , is directly dependent on the difference between its drain electrode potential and its source electrode potential, V _control , and increases as V _control increases. I _GFET increases relatively slowly as V _control increases above a saturation voltage V _Dsat . A positive voltage V _bias is supplied to the gate electrode of NDR-FET 120 , such that the current flowing in the NDR-FET, I _NDR-FET , will exceed that of IGFET 115 over a range of values for V _control . I _NDR-FET is dependent on the difference between its drain electrode potential and its source electrode potential, V _cc -V _control , at first increasing rapidly as V _cc -V _control increases, reaching a peak value when V _cc -V _control is equal to a critical voltage V _NDR , and rapidly decreasing to nearly zero as V _cc -V _contol increases beyond the critical voltage V _NDR .

[0091] Now the operation of the circuit of FIG. 7 will be described. FIG. 8 shows the current-vs.-voltage (I-V) characteristic curve I _IGFET of IGFET 115 obtained by changing the control voltage V _control applied to the control terminal in a range between 0 and V _cc , superimposed with the I-V characteristic curve I _NDR-FET of the NDR-FET. A stable operating point of the circuit is a point where the I-V characteristic curve I _IGFET of IGFET 115 crosses the I-V characteristic curve I _NDRFET of NDR-FET 120 and additionally the characteristic curves I _IGFET and I _NDRFET have different gradient signs (positive, negative, or zero). (A crossing point where both of the characteristic curves I _IGFET and I _NDRFET have positive or negative gradient is not a stable operating point.) Therefore it is understood that circuit 100 is stable when the potential V _control at the control terminal is one of two values 0 and V _high as shown in FIG. 8 . Accordingly, circuit 100 can be used as a bistable memory cell by applying a potential of one of the two values 0 and V _high to the control terminal as a write voltage. If the value of V _control falls slightly below that of a stable operating point, the NDR-FET current I _NDR-FET becomes higher than the IGFET current I _IGFET , causing the value of V _control to be increased toward V _cc , to restore it to that of the stable operating point. Thus NDR-FET 120 serves as a “pull-up” device. If the value of V _control increases slightly above that of a stable operating point, the IGFET current I _IGFET becomes higher than the NDR-FET current I _NDR-FET , causing the value of V _control to be decreased toward 0 V (ground potential), to restore it to that of the stable operating point. Thus IGFET 115 serves as a “pull-down” device. In this manner, a bistable memory cell 100 can be obtained when an NDR-FET and an IGFET are formed on the same semiconductor substrate.

[0092] A semiconductor device according a fifth embodiment of the invention will now be described with reference to FIGS. 9 and 10 . FIG. 9 is a circuit diagram of a static memory (SRAM) cell 150 consisting of two NDR-FET elements which form a bistable latch 140 and one enhancement-mode IGFET access element, and FIG. 10 is a current-vs.-voltage plot illustrating the operational characteristics of the static memory cell of FIG. 9 .

[0093] As is shown in FIG. 9 , an IGFET 118 is configured as a transfer gate, allowing a data node at potential V _data to be connected to a storage node at potential V _store under the control of an access signal V _access . One of the source/drain electrodes of IGFET 118 is connected to the storage node, the other source/drain electrode of IGFET 118 is connected to the data node, and the gate electrode of IGFET 118 is connected to an access signal terminal (read or write). The source electrode of a first NDR-FET 120 is connected to a ground terminal, the gate electrode of the first NDR-FET 120 is supplied with a first bias voltage V _bias1 , the drain electrode of the first NDR-FET 120 is connected together with the source electrode of a second NDR-FET 130 to the storage node, the gate electrode of the second NDR-FET 130 is supplied with a second bias voltage V _bias2 and the drain electrode of the second NDR-FET 130 is supplied with a positive voltage V _cc . The current flowing in the first NDR-FET, I _NDR1 , is dependent on the difference between its drain electrode potential and its source electrode potential, V _store , at first increasing rapidly as V _store increases, reaching a peak value when V _store is equal to a critical voltage V _NDR1 , and rapidly decreasing to nearly zero as V _store increases beyond the critical voltage V _NDR1 . The bias voltage V _bias1 is sufficiently high so as to ensure that the first NDR-FET is turned on for values of V _store ranging from 0 V (ground potential) to V _NDR1 . The current flowing in the second NDR-FET, I _NDR2 , is dependent on the difference between its drain electrode potential and its source electrode potential, V _cc -V _store , at first increasing rapidly as V _cc -V _store increases, reaching a peak value when V _cc -V _store is equal to a critical voltage V _NDR2 , and rapidly decreasing to nearly zero as V _cc -V _store increases beyond the critical voltage V _NDR2 . The bias voltage V _bias2 is sufficiently high so as to ensure that the second NDR-FET is turned on for values of V _cc -V _store ranging from 0 V (ground potential) to V _NDR2 .

[0094] Now the operation of the bistable latch 140 in the SRAM cell 150 of FIG. 9 will be described. FIG. 10 shows the current-vs.-voltage (I-V) characteristic curve I _NDR1 of the first NDR-FET 120 obtained by changing the storage node voltage V _store in a range between 0 and V _cc , superimposed with the I-V characteristic curve I _NDR2 of the second NDR-FET 130 . A stable operating point of circuit 150 is a point where the I-V characteristic curve I _NDR1 of the first NDR-FET 120 crosses the I-V characteristic curve I _NDR2 of the second NDR-FET 130 and additionally the characteristic curves I _NDR1 and I _NDR2 have different gradient signs (positive, negative, or zero). (A crossing point where both of the characteristic curves I _NDR1 and I _NDR2 have positive or negative gradient is not a stable operating point.) Therefore it is understood that circuit 150 is stable when the potential V _store at the storage node is one of two values 0 and V _cc as shown in FIG. 10 . Accordingly, circuit 150 can be used as a bistable memory cell by applying a potential of one of the two values 0 and V _high to the control terminal as a write voltage. If the value of V _store increases slightly above that of a stable operating point, current I _NDR1 flowing in the first NDR-FET 120 becomes higher than the current I _NDR2 flowing in the second NDR-FET 130 , causing the value of V _store to be decreased toward 0 V (ground potential), to restore it to that of the stable operating point. Thus first NDR-FET 120 serves as a “pull-down” device. If the value of V _store falls slightly below that of a stable operating point, the current I _NDR2 flowing in the second NDR-FET 130 becomes higher than the current I _NDR1 flowing in the first NDR-FET 120 , causing the value of V _store to be increased toward V _cc , to restore it to that of the stable operating point. Thus second NDR-FET 130 serves as a “pull-up” device. IGFET 118 is controlled by the access signal as follows: when the access signal potential is sufficiently high, IGFET 118 is turned on, connecting the data node to the storage node to allow data transfer (reading data from the storage node, or writing data to the storage node); when the access signal potential is low, IGFET 118 is turned off, so that the storage node is electrically isolated from the data node. In this manner, a bistable latch 140 is realized with two series-connected NDR-FET elements, and a static memory cell 150 is obtained when two NDR-FETs and an IGFET are formed on the same semiconductor substrate.

[0095] It will be understood by those skilled in the art that the particular implementation of circuit 100 (i.e., in one of the forms noted above or some apparent variation) will likely vary from application to application. Moreover, it is likely that such circuit will be combined with other well-known circuit elements (including sense amplifiers, buffers, decoders, etc.) for purposes of creating larger memory cell arrays. Furthermore, it is expected that IGFETs and NDR FETs will be combined by skilled artisans to effectuate a number of different memory and logic circuits not shown explicitly herein, and the present invention is by no means limited to the specific examples depicted. For example, multi-valued memory cells can be synthesized through well-known techniques by using appropriate combinations of IGFETS and NDR FETs having different NDR onset behavior.

[0096] A preferred fabrication process flow for manufacturing a semiconductor device comprising one or more NDR-FETs and one or more IGFETs will now be described with reference to FIGS. 11 through 20 , which are schematic cross-sectional views at various steps in the process flow.

[0097] First, as is shown in FIG. 11, a preferred substrate 1000 consisting substantially of silicon (Si) is prepared. Because the NDR-FET and IGFET are n-channel devices, the portions of the substrate in which the NDR-FET(s) and IGFET(s) are to be formed are preferably p-type. P-type wells can be formed in the surface (within the top 1000 nm) of the substrate by ion implantation and/or diffusion, either before or after the definition of “active” areas, in any number of known techniques known to those skilled in the art. It should be noted that substrate 1000 could also be silicon-on-insulator (SOI), and may eventually contain one or more additional layers of silicon-germanium alloy material (not shown).

[0098] Next, as is shown in FIG. 12 , electrically isolated “active” areas 1015 in a surface of substrate 1000 are formed by any of several well-established techniques, including preferably by local oxidation of silicon (LOCOS) and/or shallow trench isolation (STI). The thickness of an isolation oxide layer 1010 typically falls in a range from 100 nm to 700 nm, while a depth of shallow trench isolation structures typically falls in the range from 100 nm to 1000 nm. It should be noted that the precise details of these areas are not critical to the operation of the present invention, but a significant advantage of course lies in the fact that such structures (however formed) can be share by both conventional active devices as well as the NDR devices in accordance with the present teachings.

[0099] Afterwards, ion implantation of dopants into the surface of substrate 1000 is preferably performed (either selectively with a mask or non-selectively) for the purpose of adjusting the threshold voltages of the NDR-FET(s) and IGFET(s) to their desired values. It is possible, of course, that different threshold voltages may be needed, so that additional masking and implanting operations may be needed for separate adjustments to such devices. However, as before, the details of such threshold adjust is not critical to the operation of the present invention, but yet in many instances both time and cost savings can be achieved by sharing such operational step between both conventional active devices as well as the NDR devices.

[0100] Next, as is shown in FIG. 13, a first electrically insulating layer 1020 is preferably formed on the surface of substrate 1000 in active areas 1015 by one of several well-known techniques, including thermal oxidation of silicon, physical vapor deposition and chemical vapor deposition. This electrically insulating layer 1020 can consist entirely or in part of SiO ₂ , SiO _x N _y , Si ₃ N ₄ , or a high-permittivity dielectric material such as metal oxide or metal silicate or their laminates. As with the other processing steps noted above, an advantage of the present invention lies in the fact that this layer can be shared later by both conventional and NDR FET devices.

[0101] If electrically insulating layer 1020 does not contain a sufficiently high density of charge traps as formed, then it is preferable to introduce charge traps at or near the silicon substrate interface. This can be accomplished by one of several known approaches, including ion implantation and/or diffusion of an appropriate species. If electrically insulating layer 1020 is very thin (e.g. less than 1.5 nm) charge traps can be formed by deposition of an additional continuous or discontinuous layer of charge-trapping material such as SiO _x N _y , Si ₃ N ₄ , Si, Ge or metal.

[0102] Two representative examples of techniques to form charge traps near the silicon substrate interface are illustrated in FIGS. 14 and 15 . Other approaches will be apparent to those skilled in the art, and the present invention is by no means limited to such examples.

[0103] In a first approach shown in FIG. 14 a, impurity atoms are selectively implanted into a surface of substrate 1000 in the areas where NDR-FETs are to be formed to form a charge trapping region 1030 neat the silicon substrate interface. These impurity atoms may be dopants such as boron, indium, arsenic and phosphorus, or fluorine, chlorine, or germanium. Electrically insulating layer 1020 may then be selectively removed from the areas where IGFETs are to be formed, as is shown in FIG. 14 b, if it is undesirable to have it remain in those areas. Thus, in this instance, this particular operation (creation of charge trapping layer 1030 ) is performed uniquely for the NDR FETs, but not for the conventional FETs.

[0104] In a second approach shown in FIG. 15 a, impurity atoms can be selectively implanted directly into electrically insulating layer 1020 in the areas where NDR-FETs are to be formed to form a charge trapping region within such insulating layer. These impurity atoms may be dopants such as boron, indium, arsenic and phosphorus, or fluorine, chlorine, or germanium. Again, as before, electrically insulating layer 1020 may then be selectively removed from the areas where IGFETs are to be formed, as is shown in FIG. 15 b, if it is undesirable to have it remain in those areas.

[0105] If electrically insulating layer 1020 is selectively removed from the areas where IGFETs are to be formed, then a high-quality gate insulating film 1040 is then preferably formed next on the surface of substrate 1000 in active areas 1015 , as is shown in FIG. 16 to form a gate insulation layer for such IGFETs. Gate insulating film 1040 can be formed by one of several techniques, including thermal oxidation, physical vapor deposition and chemical vapor deposition. If the formation process for gate insulation layer 1040 uses sufficiently high temperatures, impurities present in the surface of substrate 1000 (as in FIG. 14 ) can be incorporated by diffusion into electrically insulating film 1020 / 1040 to form charge traps in such insulating film near the substrate interface (for illustrative purposes, films 1020 and 1040 are shown as a single composite gate film in FIG. 16 ). Gate insulating film 1040 can consist entirely or in part of SiO ₂ , SiO _x N _y , Si ₃ N ₄ , or a high-permittivity dielectric material such as metal oxide or metal silicate or their laminates.

[0106] In this manner, charge traps are selectively formed in a gate insulating film 1040 in the NDR-FET areas, either by ion implantation and/or diffusion of an appropriate species or by depositing a charge-trapping layer, either before or after part or all of the NDR-FET gate insulating film 1040 has been formed. Again, in the above process steps, features and structures of the NDR FETs are manufactured at the same time and common processing steps as those used for IGFETs in the integrated circuit.

[0107] If a “buried contact” between the gate electrode and source or drain region of the IGFET (or NDR FET) is required, then contact hole(s) are formed in gate insulating film 140 using standard lithography and etching processes. As before, such contacts can also be created at the same time for both types of FETs.

[0108] Next as shown in FIG. 17, a gate electrode film/layer 150 is deposited onto substrate 100 , on top of gate insulating film 14 and patterned using standard lithography and etching processes to form gate electrodes ( FIG. 18 ). The gate electrode material 150 may be polycrystalline silicon (poly-Si) or a silicon-germanium alloy (poly-SiGe), or it may be a metal or conductive metal nitride or conductive metal oxide. An advantage of the present invention, again, is apparent because the gates of both NDR FETs and conventional FETs can be made of the same material, and at the same time.

[0109] If gate electrode material 150 is poly-Si or poly-SiGe, it may doped in-situ during the deposition process or it may be doped ex-situ by ion implantation and/or diffusion, to achieve low resistivity and a proper work function value. Gate electrode 1060 may consist of a multi-layered stack, with a lowest layer providing a desired gate work function and overlying layer(s) providing sufficient thickness and conductivity. After gate patterning, a thermal anneal may be performed in an oxidizing ambient (e.g. O ₂ or H ₂ O) to anneal out any damage to gate insulating film 1050 at the edges of gate electrodes 1060 . If boron is to be incorporated into electrically insulating film 1040 in the NDR-FET areas of substrate 1000 , it can enhance the formation of water-related traps in the electrically insulating film during an anneal in a steam (H ₂ O) ambient.

[0110] As shown in FIG. 19 , source and drain contact regions (electrodes) are then formed by ion implantation of n-type dopants such as arsenic and phosphorus and subsequent thermal annealing to remove damage and to activate the dopants. In this particular implementation, gate electrodes 1060 are sufficiently thick to prevent implanted ions from entering the surface of substrate 1000 underneath the gate electrodes. If boron is incorporated into electrically insulating film 1040 in the NDR-FET areas, it can enhance the formation of water-related traps in the electrically insulating film during an anneal in a steam (H ₂ O) ambient.

[0111] In order to achieve good short-channel IGFET performance (low leakage current when the transistor is turned off), shallow source/drain extension regions (not shown) may be formed first by ion implantation or diffusion in the IGFET areas, either before or after deep source and drain regions. In this case, the deep source and drain regions are offset from the edges of the gate electrode by spacers formed along the sidewalls of the gate electrodes. The sidewall spacers are formed by conformal deposition and anisotropic etching of a spacer film. (The thickness of this spacer film determines the width of the sidewall spacers and hence the offset from the gate electrode.)

[0112] If the shallow source/drain extension regions are to be formed after the deep source and drain regions, then disposable sidewall spacers (e.g. composed of germanium or silicon-germanium, which can be removed selectively with respect to Si, SiO ₂ , SiO _x N _y , Si ₃ N ₄ , metal, metal nitrides and metal oxides) must be used. The dopant concentration in the shallow source/drain extension regions may be lower than the dopant concentration in the deep source and drain regions, to reduce hot-carrier effects which can cause reliability problems. Shallow source/drain extension regions may be formed in the NDR-FET areas simultaneously with the shallow source/drain extension regions in the IGFET areas. The dopant concentration and junction depth of the shallow source/drain extensions for the NDR-FET can be made to be different from those for the NDR-FET, if necessary, by selective (masked) ion implantation.

[0113] As shown in FIG. 20 , device fabrication is completed by deposition of an electrically insulating interlayer film 1080 , formation of contact holes 1085 , filling of contact holes with metal plugs 1090 , deposition and patterning of a metal layer to form interconnections, and a low-temperature (350° C.-450° C.) anneal in a hydrogen-containing ambient (forming gas). Multiple layers of metal wiring, if necessary, may be formed by deposition and patterning of alternate layers of insulating material and metal.

[0114] In this manner, a semiconductor device comprising one or more IGFET elements and one or more NDR-FET elements can be manufactured on a common substrate utilizing a fabrication sequence utilizing conventional processing techniques. For example, an NDR FET and a conventional IGFET share a number of common layers in their respective areas including: a common substrate 1000 ; gate film 1040 and 1040 ′; gate electrode 1060 and 1060 ′; interlayer insulation layer 1080 and 1080 ′; metal plugs/layer 1090 and 1090 ′. Furthermore, they also share certain isolation areas 1010 , and have source/drain regions 1070 and 1070 ′ formed at the same time with common implantation/anneal steps. In some cases, there can be direct sharing of such regions of course, so that the drain of an NDR FET can correspond to a drain/source of an IGFET, or vice versa. It will be understood that other processing steps and/or layers may be performed in addition to those shown above, and these examples are provided merely to illustrate the teachings of the present inventions. For example, additional interconnect and/or insulation layers are typically used in ICs and can also be shared.

[0115] While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. It will be clearly understood by those skilled in the art that foregoing description is merely by way of example and is not a limitation on the scope of the invention, which may be utilized in many types of integrated circuits made with conventional processing technologies. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. Such modifications and combinations, of course, may use other features that are already known in lieu of or in addition to what is disclosed herein. It is therefore intended that the appended claims encompass any such modifications or embodiments. While such claims have been formulated based on the particular embodiments described herein, it should be apparent the scope of the disclosure herein also applies to any novel and non-obvious feature (or combination thereof) disclosed explicitly or implicitly to one of skill in the art, regardless of whether such relates to the claims as provided below, and whether or not it solves and/or mitigates all of the same technical problems described above. Finally, the applicants further reserve the right to pursue new and/or additional claims directed to any such novel and non-obvious features during the prosecution of the present application (and/or any related applications).